2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_PAGING_H__
22 #define __VMM_PAGING_H__
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_util.h>
33 In the following, when we say "page table", we mean the whole 2 or 4 layer
34 page table (PDEs, PTEs), etc.
37 guest-visible paging state
38 This is the state that the guest thinks the machine is using
40 - guest physical memory
41 The physical memory addresses the guest is allowed to use
42 (see shadow page maps, below)
44 (we care about when the current one changes)
45 - guest paging registers (these are never written to hardware)
51 This the state that the machine will actually use when the guest
52 is running. It consists of:
53 - current shadow page table
54 This is the page table actually useed when the guest is running.
55 It is changed/regenerated when the guest page table changes
56 It mostly reflects the guest page table, except that it restricts
57 physical addresses to those the VMM allocates to the guest.
59 This is a mapping from guest physical memory addresses to
60 the current location of the guest physical memory content.
61 It maps from regions of physical memory addresses to regions
62 located in physical memory or elsewhere.
63 (8192,16384) -> MEM(8912,...)
64 (0,8191) -> DISK(65536,..)
65 - guest paging registers (these are written to guest state)
70 This is the state we expect to be operative when the VMM is running.
71 Typically, this is set up by the host os into which we have embedded
72 the VMM, but we include the description here for clarity.
74 This is the page table we use when we are executing in
75 the VMM (or the host os)
81 The reason why the shadow paging state and the host paging state are
82 distinct is to permit the guest to use any virtual address it wants,
83 irrespective of the addresses the VMM or the host os use. These guest
84 virtual addresses are reflected in the shadow paging state. When we
85 exit from the guest, we switch to the host paging state so that any
86 virtual addresses that overlap between the guest and VMM/host now map
87 to the physical addresses epxected by the VMM/host. On AMD SVM, this
88 switch is done by the hardware. On Intel VT, the switch is done
89 by the hardware as well, but we are responsible for manually updating
90 the host state in the vmcs before entering the guest.
96 #define MAX_PDE32_ENTRIES 1024
97 #define MAX_PTE32_ENTRIES 1024
99 #define MAX_PDPE32PAE_ENTRIES 4
100 #define MAX_PDE32PAE_ENTRIES 512
101 #define MAX_PTE32PAE_ENTRIES 512
103 #define MAX_PML4E64_ENTRIES 512
104 #define MAX_PDPE64_ENTRIES 512
105 #define MAX_PDE64_ENTRIES 512
106 #define MAX_PTE64_ENTRIES 512
110 /* Converts an address into a page table index */
111 #define PDE32_INDEX(x) ((((uint_t)x) >> 22) & 0x3ff)
112 #define PTE32_INDEX(x) ((((uint_t)x) >> 12) & 0x3ff)
115 #define PDPE32PAE_INDEX(x) ((((uint_t)x) >> 30) & 0x3)
116 #define PDE32PAE_INDEX(x) ((((uint_t)x) >> 21) & 0x1ff)
117 #define PTE32PAE_INDEX(x) ((((uint_t)x) >> 12) & 0x1ff)
119 #define PML4E64_INDEX(x) ((((ullong_t)x) >> 39) & 0x1ff)
120 #define PDPE64_INDEX(x) ((((ullong_t)x) >> 30) & 0x1ff)
121 #define PDE64_INDEX(x) ((((ullong_t)x) >> 21) & 0x1ff)
122 #define PTE64_INDEX(x) ((((ullong_t)x) >> 12) & 0x1ff)
125 /* Gets the base address needed for a Page Table entry */
126 /* Deprecate these :*/
128 #define PD32_BASE_ADDR(x) (((uint_t)x) >> 12)
129 #define PT32_BASE_ADDR(x) (((uint_t)x) >> 12)
130 #define PD32_4MB_BASE_ADDR(x) (((uint_t)x) >> 22)
132 #define PML4E64_BASE_ADDR(x) (((ullong_t)x) >> 12)
133 #define PDPE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
134 #define PDE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
135 #define PTE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
137 // Accessor functions for the page table structures
138 #define PDE32_T_ADDR(x) (((x).pt_base_addr) << 12)
139 #define PTE32_T_ADDR(x) (((x).page_base_addr) << 12)
140 #define PDE32_4MB_T_ADDR(x) (((x).page_base_addr) << 22)
142 /* Replace The above with these... */
143 #define PAGE_BASE_ADDR(x) ((x) >> 12)
144 #define PAGE_BASE_ADDR_2MB(x) ((x) >> 21)
145 #define PAGE_BASE_ADDR_4MB(x) ((x) >> 22)
147 #define BASE_TO_PAGE_ADDR(x) (((addr_t)x) << 12)
148 #define BASE_TO_PAGE_ADDR_2MB(x) (((addr_t)x) << 21)
149 #define BASE_TO_PAGE_ADDR_4MB(x) (((addr_t)x) << 22)
154 #define PT32_PAGE_OFFSET(x) (((uint_t)x) & 0xfff)
155 #define PD32_4MB_PAGE_OFFSET(x) (((uint_t)x) & 0x003fffff)
157 #define PT32_PAGE_ADDR(x) (((uint_t)x) & 0xfffff000)
158 #define PD32_4MB_PAGE_ADDR(x) (((uint_t)x) & 0xffc00000)
160 #define PT32_PAGE_POWER 12
161 #define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
162 //#define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
163 #define PAGE_POWER 12
164 #define PAGE_SIZE 4096
166 /* use these instead */
167 #define PAGE_OFFSET(x) ((x) & 0xfff)
168 #define PAGE_OFFSET_2MB(x) ((x) & 0x1fffff)
169 #define PAGE_OFFSET_4MB(x) ((x) & 0x3fffff)
171 #define PAGE_POWER 12
172 #define PAGE_POWER_2MB 22
173 #define PAGE_POWER_4MB 21
175 // We shift instead of mask because we don't know the address size
176 #define PAGE_ADDR(x) (((x) >> PAGE_POWER) << PAGE_POWER)
177 #define PAGE_ADDR_2MB(x) (((x) >> PAGE_POWER_2MB) << PAGE_POWER_2MB)
178 #define PAGE_ADDR_4MB(x) (((x) >> PAGE_POWER_4MB) << PAGE_POWER_4MB)
180 #define PAGE_SIZE 4096
181 #define PAGE_SIZE_2MB (4096 * 512)
182 #define PAGE_SIZE_4MB (4096 * 1024)
191 #define CR3_TO_PDE32_PA(cr3) ((addr_t)(((uint_t)cr3) & 0xfffff000))
192 #define CR3_TO_PDPE32PAE_PA(cr3) ((addr_t)(((uint_t)cr3) & 0xffffffe0))
193 #define CR3_TO_PML4E64_PA(cr3) ((addr_t)(((ullong_t)cr3) & 0x000ffffffffff000LL))
195 #define CR3_TO_PDE32_VA(cr3) ((pde32_t *)V3_VAddr((void *)(addr_t)(((uint_t)cr3) & 0xfffff000)))
196 #define CR3_TO_PDPE32PAE_VA(cr3) ((pdpe32pae_t *)V3_VAddr((void *)(addr_t)(((uint_t)cr3) & 0xffffffe0)))
197 #define CR3_TO_PML4E64_VA(cr3) ((pml4e64_t *)V3_VAddr((void *)(addr_t)(((ullong_t)cr3) & 0x000ffffffffff000LL)))
204 /* Page Table Flag Values */
205 #define PT32_HOOK 0x1
206 #define PT32_GUEST_PT 0x2
210 /* We'll use the general form for now....
211 typedef enum {PDE32_ENTRY_NOT_PRESENT, PDE32_ENTRY_PTE32, PDE32_ENTRY_LARGE_PAGE} pde32_entry_type_t;
212 typedef enum {PTE32_ENTRY_NOT_PRESENT, PTE32_ENTRY_PAGE} pte32_entry_type_t;
214 typedef enum {PDPE32PAE_ENTRY_NOT_PRESENT, PDPE32PAE_ENTRY_PAGE} pdpe32pae_entry_type_t;
215 typedef enum {PDE32PAE_ENTRY_NOT_PRESENT, PDE32PAE_ENTRY_PTE32, PDE32PAE_ENTRY_LARGE_PAGE} pde32pae_entry_type_t;
216 typedef enum {PTE32PAE_ENTRY_NOT_PRESENT, PTE32PAE_ENTRY_PAGE} pte32pae_entry_type_t;
218 typedef enum {PML4E64_ENTRY_NOT_PRESENT, PML4E64_ENTRY_PAGE} pml4e64_entry_type_t;
219 typedef enum {PDPE64_ENTRY_NOT_PRESENT, PDPE64_ENTRY_PTE32, PDPE64_ENTRY_LARGE_PAGE} pdpe64_entry_type_t;
220 typedef enum {PDE64_ENTRY_NOT_PRESENT, PDE64_ENTRY_PTE32, PDE64_ENTRY_LARGE_PAGE} pde64_entry_type_t;
221 typedef enum {PTE64_ENTRY_NOT_PRESENT, PTE64_ENTRY_PAGE} pte64_entry_type_t;
225 typedef enum {PT_ENTRY_NOT_PRESENT, PT_ENTRY_LARGE_PAGE, PT_ENTRY_PAGE} pt_entry_type_t;
226 typedef enum {PT_ACCESS_OK, PT_ACCESS_NOT_PRESENT, PT_ACCESS_WRITE_ERROR, PT_ACCESS_USER_ERROR} pt_access_status_t;
229 typedef struct gen_pt {
232 uint_t user_page : 1;
233 } __attribute__((packed)) gen_pt_t;
235 typedef struct pde32 {
238 uint_t user_page : 1;
239 uint_t write_through : 1;
240 uint_t cache_disable : 1;
243 uint_t large_page : 1;
244 uint_t global_page : 1;
246 uint_t pt_base_addr : 20;
247 } __attribute__((packed)) pde32_t;
249 typedef struct pde32_4MB {
252 uint_t user_page : 1;
253 uint_t write_through : 1;
254 uint_t cache_disable : 1;
257 uint_t large_page : 1;
258 uint_t global_page : 1;
262 uint_t page_base_addr : 10;
264 } __attribute__((packed)) pde32_4MB_t;
266 typedef struct pte32 {
269 uint_t user_page : 1;
270 uint_t write_through : 1;
271 uint_t cache_disable : 1;
275 uint_t global_page : 1;
277 uint_t page_base_addr : 20;
278 } __attribute__((packed)) pte32_t;
281 /* 32 bit PAE PAGE STRUCTURES */
282 typedef struct pdpe32pae {
284 uint_t rsvd : 2; // MBZ
285 uint_t write_through : 1;
286 uint_t cache_disable : 1;
289 uint_t rsvd2 : 2; // MBZ
291 uint_t pd_base_addr : 24;
292 uint_t rsvd3 : 28; // MBZ
293 } __attribute__((packed)) pdpe32pae_t;
297 typedef struct pde32pae {
300 uint_t user_page : 1;
301 uint_t write_through : 1;
302 uint_t cache_disable : 1;
305 uint_t large_page : 1;
306 uint_t global_page : 1;
308 uint_t pt_base_addr : 24;
310 } __attribute__((packed)) pde32pae_t;
312 typedef struct pde32pae_2MB {
315 uint_t user_page : 1;
316 uint_t write_through : 1;
317 uint_t cache_disable : 1;
321 uint_t global_page : 1;
325 uint_t page_base_addr : 15;
328 } __attribute__((packed)) pde32pae_2MB_t;
330 typedef struct pte32pae {
333 uint_t user_page : 1;
334 uint_t write_through : 1;
335 uint_t cache_disable : 1;
339 uint_t global_page : 1;
341 uint_t page_base_addr : 24;
343 } __attribute__((packed)) pte32pae_t;
352 /* LONG MODE 64 bit PAGE STRUCTURES */
353 typedef struct pml4e64 {
356 uint_t user_page : 1;
357 uint_t write_through : 1;
358 uint_t cache_disable : 1;
363 ullong_t pdp_base_addr : 40;
364 uint_t available : 11;
365 uint_t no_execute : 1;
366 } __attribute__((packed)) pml4e64_t;
369 typedef struct pdpe64 {
372 uint_t user_page : 1;
373 uint_t write_through : 1;
374 uint_t cache_disable : 1;
377 uint_t large_page : 1;
380 ullong_t pd_base_addr : 40;
381 uint_t available : 11;
382 uint_t no_execute : 1;
383 } __attribute__((packed)) pdpe64_t;
386 // We Don't support this
387 typedef struct pdpe64_1GB {
390 uint_t user_page : 1;
391 uint_t write_through : 1;
392 uint_t cache_disable : 1;
395 uint_t large_page : 1;
396 uint_t global_page : 1;
400 ullong_t page_base_addr : 22;
401 uint_t available : 11;
402 uint_t no_execute : 1;
403 } __attribute__((packed)) pdpe64_1GB_t;
407 typedef struct pde64 {
410 uint_t user_page : 1;
411 uint_t write_through : 1;
412 uint_t cache_disable : 1;
415 uint_t large_page : 1;
416 uint_t global_page : 1;
418 ullong_t pt_base_addr : 40;
419 uint_t available : 11;
420 uint_t no_execute : 1;
421 } __attribute__((packed)) pde64_t;
423 typedef struct pde64_2MB {
426 uint_t user_page : 1;
427 uint_t write_through : 1;
428 uint_t cache_disable : 1;
431 uint_t large_page : 1;
432 uint_t global_page : 1;
436 ullong_t page_base_addr : 31;
437 uint_t available : 11;
438 uint_t no_execute : 1;
439 } __attribute__((packed)) pde64_2MB_t;
442 typedef struct pte64 {
445 uint_t user_page : 1;
446 uint_t write_through : 1;
447 uint_t cache_disable : 1;
451 uint_t global_page : 1;
453 ullong_t page_base_addr : 40;
454 uint_t available : 11;
455 uint_t no_execute : 1;
456 } __attribute__((packed)) pte64_t;
458 /* *************** */
460 typedef struct pf_error_code {
461 uint_t present : 1; // if 0, fault due to page not present
462 uint_t write : 1; // if 1, faulting access was a write
463 uint_t user : 1; // if 1, faulting access was in user mode
464 uint_t rsvd_access : 1; // if 1, fault from reading a 1 from a reserved field (?)
465 uint_t ifetch : 1; // if 1, faulting access was an instr fetch (only with NX)
467 } __attribute__((packed)) pf_error_t;
472 void delete_page_tables_32(pde32_t * pde);
473 void delete_page_tables_32PAE(pdpe32pae_t * pdpe);
474 void delete_page_tables_64(pml4e64_t * pml4);
478 int v3_translate_guest_pt_32(struct guest_info * info, v3_reg_t guest_cr3, addr_t vaddr, addr_t * paddr);
479 int v3_translate_guest_pt_32pae(struct guest_info * info, v3_reg_t guest_cr3, addr_t vaddr, addr_t * paddr);
480 int v3_translate_guest_pt_64(struct guest_info * info, v3_reg_t guest_cr3, addr_t vaddr, addr_t * paddr);
482 int v3_translate_host_pt_32(v3_reg_t host_cr3, addr_t vaddr, addr_t * paddr);
483 int v3_translate_host_pt_32pae(v3_reg_t host_cr3, addr_t vaddr, addr_t * paddr);
484 int v3_translate_host_pt_64(v3_reg_t host_cr3, addr_t vaddr, addr_t * paddr);
487 /* Should these be static? */
488 pt_entry_type_t pde32_lookup(pde32_t * pd, addr_t addr, addr_t * entry);
489 pt_entry_type_t pte32_lookup(pte32_t * pt, addr_t addr, addr_t * entry);
491 pt_entry_type_t pdpe32pae_lookup(pdpe32pae_t * pdp, addr_t addr, addr_t * entry);
492 pt_entry_type_t pde32pae_lookup(pde32pae_t * pd, addr_t addr, addr_t * entry);
493 pt_entry_type_t pte32pae_lookup(pte32pae_t * pt, addr_t addr, addr_t * entry);
495 pt_entry_type_t pml4e64_lookup(pml4e64_t * pml, addr_t addr, addr_t * entry);
496 pt_entry_type_t pdpe64_lookup(pdpe64_t * pdp, addr_t addr, addr_t * entry);
497 pt_entry_type_t pde64_lookup(pde64_t * pd, addr_t addr, addr_t * entry);
498 pt_entry_type_t pte64_lookup(pte64_t * pt, addr_t addr, addr_t * entry);
505 pt_access_status_t inline v3_can_access_pde32(pde32_t * pde, addr_t addr, pf_error_t access_type);
506 pt_access_status_t inline v3_can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
508 pt_access_status_t inline v3_can_access_pdpe32pae(pdpe32pae_t * pdpe, addr_t addr, pf_error_t access_type);
509 pt_access_status_t inline v3_can_access_pde32pae(pde32pae_t * pde, addr_t addr, pf_error_t access_type);
510 pt_access_status_t inline v3_can_access_pte32pae(pte32pae_t * pte, addr_t addr, pf_error_t access_type);
512 pt_access_status_t inline v3_can_access_pml4e64(pml4e64_t * pmle, addr_t addr, pf_error_t access_type);
513 pt_access_status_t inline v3_can_access_pdpe64(pdpe64_t * pdpe, addr_t addr, pf_error_t access_type);
514 pt_access_status_t inline v3_can_access_pde64(pde64_t * pde, addr_t addr, pf_error_t access_type);
515 pt_access_status_t inline v3_can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
524 pde32_t * create_passthrough_pts_32(struct guest_info * guest_info);
525 pdpe32pae_t * create_passthrough_pts_32PAE(struct guest_info * guest_info);
526 pml4e64_t * create_passthrough_pts_64(struct guest_info * info);
531 //#include <palacios/vm_guest.h>
533 void PrintDebugPageTables(pde32_t * pde);
536 void PrintPageTree(v3_vm_cpu_mode_t cpu_mode, addr_t virtual_addr, addr_t cr3);
537 void PrintPageTree_64(addr_t virtual_addr, pml4e64_t * pml);
540 void PrintPT32(addr_t starting_address, pte32_t * pte);
541 void PrintPD32(pde32_t * pde);
542 void PrintPTE32(addr_t virtual_address, pte32_t * pte);
543 void PrintPDE32(addr_t virtual_address, pde32_t * pde);
545 void PrintDebugPageTables32PAE(pdpe32pae_t * pde);
546 void PrintPTE32PAE(addr_t virtual_address, pte32pae_t * pte);
547 void PrintPDE32PAE(addr_t virtual_address, pde32pae_t * pde);
548 void PrintPTE64(addr_t virtual_address, pte64_t * pte);