2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_PAGING_H
22 #define __VMM_PAGING_H
25 #include <palacios/vmm_types.h>
26 #include <palacios/vmm_util.h>
30 In the following, when we say "page table", we mean the whole 2 or 4 layer
31 page table (PDEs, PTEs), etc.
34 guest-visible paging state
35 This is the state that the guest thinks the machine is using
37 - guest physical memory
38 The physical memory addresses the guest is allowed to use
39 (see shadow page maps, below)
41 (we care about when the current one changes)
42 - guest paging registers (these are never written to hardware)
48 This the state that the machine will actually use when the guest
49 is running. It consists of:
50 - current shadow page table
51 This is the page table actually useed when the guest is running.
52 It is changed/regenerated when the guest page table changes
53 It mostly reflects the guest page table, except that it restricts
54 physical addresses to those the VMM allocates to the guest.
56 This is a mapping from guest physical memory addresses to
57 the current location of the guest physical memory content.
58 It maps from regions of physical memory addresses to regions
59 located in physical memory or elsewhere.
60 (8192,16384) -> MEM(8912,...)
61 (0,8191) -> DISK(65536,..)
62 - guest paging registers (these are written to guest state)
67 This is the state we expect to be operative when the VMM is running.
68 Typically, this is set up by the host os into which we have embedded
69 the VMM, but we include the description here for clarity.
71 This is the page table we use when we are executing in
72 the VMM (or the host os)
78 The reason why the shadow paging state and the host paging state are
79 distinct is to permit the guest to use any virtual address it wants,
80 irrespective of the addresses the VMM or the host os use. These guest
81 virtual addresses are reflected in the shadow paging state. When we
82 exit from the guest, we switch to the host paging state so that any
83 virtual addresses that overlap between the guest and VMM/host now map
84 to the physical addresses epxected by the VMM/host. On AMD SVM, this
85 switch is done by the hardware. On Intel VT, the switch is done
86 by the hardware as well, but we are responsible for manually updating
87 the host state in the vmcs before entering the guest.
93 #define MAX_PTE32_ENTRIES 1024
94 #define MAX_PDE32_ENTRIES 1024
96 #define MAX_PTE64_ENTRIES 512
97 #define MAX_PDE64_ENTRIES 512
98 #define MAX_PDPE64_ENTRIES 512
99 #define MAX_PML4E64_ENTRIES 512
102 /* Converts an address into a page table index */
103 #define PDE32_INDEX(x) ((((uint_t)x) >> 22) & 0x3ff)
104 #define PTE32_INDEX(x) ((((uint_t)x) >> 12) & 0x3ff)
106 /* Gets the base address needed for a Page Table entry */
107 #define PD32_BASE_ADDR(x) (((uint_t)x) >> 12)
108 #define PT32_BASE_ADDR(x) (((uint_t)x) >> 12)
109 #define PD32_4MB_BASE_ADDR(x) (((uint_t)x) >> 22)
111 #define PT32_PAGE_ADDR(x) (((uint_t)x) & 0xfffff000)
112 #define PT32_PAGE_OFFSET(x) (((uint_t)x) & 0xfff)
113 #define PT32_PAGE_POWER 12
115 #define PD32_4MB_PAGE_ADDR(x) (((uint_t)x) & 0xffc00000)
116 #define PD32_4MB_PAGE_OFFSET(x) (((uint_t)x) & 0x003fffff)
117 #define PAGE_SIZE_4MB (4096 * 1024)
119 /* The following should be phased out */
120 #define PAGE_OFFSET(x) ((((uint_t)x) & 0xfff))
121 #define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
122 #define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
123 #define PAGE_POWER 12
124 #define PAGE_SIZE 4096
130 #define CR3_TO_PDE32(cr3) (((ulong_t)cr3) & 0xfffff000)
131 #define CR3_TO_PDPTRE(cr3) (((ulong_t)cr3) & 0xffffffe0)
132 #define CR3_TO_PML4E64(cr3) (((ullong_t)cr3) & 0x000ffffffffff000LL)
137 /* Accessor functions for the page table structures */
138 #define PDE32_T_ADDR(x) (((x).pt_base_addr) << 12)
139 #define PTE32_T_ADDR(x) (((x).page_base_addr) << 12)
140 #define PDE32_4MB_T_ADDR(x) (((x).page_base_addr) << 22)
142 /* Page Table Flag Values */
143 #define PT32_HOOK 0x1
144 #define PT32_GUEST_PT 0x2
149 /* PDE 32 bit PAGE STRUCTURES */
150 typedef enum {PDE32_ENTRY_NOT_PRESENT, PDE32_ENTRY_PTE32, PDE32_ENTRY_LARGE_PAGE} pde32_entry_type_t;
151 typedef enum {PT_ACCESS_OK, PT_ENTRY_NOT_PRESENT, PT_WRITE_ERROR, PT_USER_ERROR} pt_access_status_t;
153 typedef struct pde32 {
156 uint_t user_page : 1;
157 uint_t write_through : 1;
158 uint_t cache_disable : 1;
161 uint_t large_page : 1;
162 uint_t global_page : 1;
164 uint_t pt_base_addr : 20;
167 typedef struct pde32_4MB {
170 uint_t user_page : 1;
171 uint_t write_through : 1;
172 uint_t cache_disable : 1;
176 uint_t global_page : 1;
180 uint_t page_base_addr : 10;
184 typedef struct pte32 {
187 uint_t user_page : 1;
188 uint_t write_through : 1;
189 uint_t cache_disable : 1;
193 uint_t global_page : 1;
195 uint_t page_base_addr : 20;
199 /* 32 bit PAE PAGE STRUCTURES */
208 /* LONG MODE 64 bit PAGE STRUCTURES */
209 typedef struct pml4e64 {
219 uint_t pdp_base_addr_lo : 20;
220 uint_t pdp_base_addr_hi : 20;
221 uint_t available : 11;
222 uint_t no_execute : 1;
226 typedef struct pdpe64 {
234 uint_t large_pages : 1;
237 uint_t pd_base_addr_lo : 20;
238 uint_t pd_base_addr_hi : 20;
239 uint_t available : 11;
240 uint_t no_execute : 1;
246 typedef struct pde64 {
251 uint_t large_pages : 1;
252 uint_t reserved2 : 1;
254 uint_t pt_base_addr_lo : 20;
255 uint_t pt_base_addr_hi : 20;
256 uint_t available : 11;
257 uint_t no_execute : 1;
260 typedef struct pte64 {
266 uint_t global_page : 1;
268 uint_t page_base_addr_lo : 20;
269 uint_t page_base_addr_hi : 20;
270 uint_t available : 11;
271 uint_t no_execute : 1;
274 /* *************** */
276 typedef struct pf_error_code {
277 uint_t present : 1; // if 0, fault due to page not present
278 uint_t write : 1; // if 1, faulting access was a write
279 uint_t user : 1; // if 1, faulting access was in user mode
280 uint_t rsvd_access : 1; // if 1, fault from reading a 1 from a reserved field (?)
281 uint_t ifetch : 1; // if 1, faulting access was an instr fetch (only with NX)
285 typedef enum { PDE32 } paging_mode_t;
290 void delete_page_tables_pde32(pde32_t * pde);
293 pde32_entry_type_t pde32_lookup(pde32_t * pd, addr_t addr, addr_t * entry);
294 int pte32_lookup(pte32_t * pte, addr_t addr, addr_t * entry);
296 // This assumes that the page table resides in the host address space
297 // IE. IT DOES NO VM ADDR TRANSLATION
298 int pt32_lookup(pde32_t * pd, addr_t vaddr, addr_t * paddr);
302 pt_access_status_t can_access_pde32(pde32_t * pde, addr_t addr, pf_error_t access_type);
303 pt_access_status_t can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
311 pde32_t * create_passthrough_pde32_pts(struct guest_info * guest_info);
318 void PrintDebugPageTables(pde32_t * pde);
324 void PrintPT32(addr_t starting_address, pte32_t * pte);
325 void PrintPD32(pde32_t * pde);
326 void PrintPTE32(addr_t virtual_address, pte32_t * pte);
327 void PrintPDE32(addr_t virtual_address, pde32_t * pde);