2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_PAGING_H__
22 #define __VMM_PAGING_H__
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_util.h>
32 In the following, when we say "page table", we mean the whole 2 or 4 layer
33 page table (PDEs, PTEs), etc.
36 guest-visible paging state
37 This is the state that the guest thinks the machine is using
39 - guest physical memory
40 The physical memory addresses the guest is allowed to use
41 (see shadow page maps, below)
43 (we care about when the current one changes)
44 - guest paging registers (these are never written to hardware)
50 This the state that the machine will actually use when the guest
51 is running. It consists of:
52 - current shadow page table
53 This is the page table actually useed when the guest is running.
54 It is changed/regenerated when the guest page table changes
55 It mostly reflects the guest page table, except that it restricts
56 physical addresses to those the VMM allocates to the guest.
58 This is a mapping from guest physical memory addresses to
59 the current location of the guest physical memory content.
60 It maps from regions of physical memory addresses to regions
61 located in physical memory or elsewhere.
62 (8192,16384) -> MEM(8912,...)
63 (0,8191) -> DISK(65536,..)
64 - guest paging registers (these are written to guest state)
69 This is the state we expect to be operative when the VMM is running.
70 Typically, this is set up by the host os into which we have embedded
71 the VMM, but we include the description here for clarity.
73 This is the page table we use when we are executing in
74 the VMM (or the host os)
80 The reason why the shadow paging state and the host paging state are
81 distinct is to permit the guest to use any virtual address it wants,
82 irrespective of the addresses the VMM or the host os use. These guest
83 virtual addresses are reflected in the shadow paging state. When we
84 exit from the guest, we switch to the host paging state so that any
85 virtual addresses that overlap between the guest and VMM/host now map
86 to the physical addresses epxected by the VMM/host. On AMD SVM, this
87 switch is done by the hardware. On Intel VT, the switch is done
88 by the hardware as well, but we are responsible for manually updating
89 the host state in the vmcs before entering the guest.
95 #define MAX_PTE32_ENTRIES 1024
96 #define MAX_PDE32_ENTRIES 1024
98 #define MAX_PTE64_ENTRIES 512
99 #define MAX_PDE64_ENTRIES 512
100 #define MAX_PDPE64_ENTRIES 512
101 #define MAX_PML4E64_ENTRIES 512
104 /* Converts an address into a page table index */
105 #define PDE32_INDEX(x) ((((uint_t)x) >> 22) & 0x3ff)
106 #define PTE32_INDEX(x) ((((uint_t)x) >> 12) & 0x3ff)
108 /* Gets the base address needed for a Page Table entry */
109 #define PD32_BASE_ADDR(x) (((uint_t)x) >> 12)
110 #define PT32_BASE_ADDR(x) (((uint_t)x) >> 12)
111 #define PD32_4MB_BASE_ADDR(x) (((uint_t)x) >> 22)
114 #define PML4E64_BASE_ADDR(x) (((ullong_t)x) >> 12)
115 #define PDPE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
116 #define PDE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
117 #define PTE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
119 #define PT32_PAGE_ADDR(x) (((uint_t)x) & 0xfffff000)
120 #define PT32_PAGE_OFFSET(x) (((uint_t)x) & 0xfff)
121 #define PT32_PAGE_POWER 12
123 #define PD32_4MB_PAGE_ADDR(x) (((uint_t)x) & 0xffc00000)
124 #define PD32_4MB_PAGE_OFFSET(x) (((uint_t)x) & 0x003fffff)
125 #define PAGE_SIZE_4MB (4096 * 1024)
127 /* The following should be phased out */
128 #define PAGE_OFFSET(x) ((((uint_t)x) & 0xfff))
129 #define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
130 #define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
131 #define PAGE_POWER 12
132 #define PAGE_SIZE 4096
138 #define CR3_TO_PDE32(cr3) (V3_VAddr((void *)(((ulong_t)cr3) & 0xfffff000)))
139 #define CR3_TO_PDPTRE(cr3) (V3_VAddr((void *)(((ulong_t)cr3) & 0xffffffe0)))
140 #define CR3_TO_PML4E64(cr3) (V3_VAddr((void *)(((ullong_t)cr3) & 0x000ffffffffff000LL)))
145 /* Accessor functions for the page table structures */
146 #define PDE32_T_ADDR(x) (((x).pt_base_addr) << 12)
147 #define PTE32_T_ADDR(x) (((x).page_base_addr) << 12)
148 #define PDE32_4MB_T_ADDR(x) (((x).page_base_addr) << 22)
150 /* Page Table Flag Values */
151 #define PT32_HOOK 0x1
152 #define PT32_GUEST_PT 0x2
157 /* PDE 32 bit PAGE STRUCTURES */
158 typedef enum {PDE32_ENTRY_NOT_PRESENT, PDE32_ENTRY_PTE32, PDE32_ENTRY_LARGE_PAGE} pde32_entry_type_t;
159 typedef enum {PT_ACCESS_OK, PT_ENTRY_NOT_PRESENT, PT_WRITE_ERROR, PT_USER_ERROR} pt_access_status_t;
161 typedef struct pde32 {
164 uint_t user_page : 1;
165 uint_t write_through : 1;
166 uint_t cache_disable : 1;
169 uint_t large_page : 1;
170 uint_t global_page : 1;
172 uint_t pt_base_addr : 20;
175 typedef struct pde32_4MB {
178 uint_t user_page : 1;
179 uint_t write_through : 1;
180 uint_t cache_disable : 1;
184 uint_t global_page : 1;
188 uint_t page_base_addr : 10;
192 typedef struct pte32 {
195 uint_t user_page : 1;
196 uint_t write_through : 1;
197 uint_t cache_disable : 1;
201 uint_t global_page : 1;
203 uint_t page_base_addr : 20;
207 /* 32 bit PAE PAGE STRUCTURES */
216 /* LONG MODE 64 bit PAGE STRUCTURES */
217 typedef struct pml4e64 {
220 uint_t user_page : 1;
221 uint_t write_through : 1;
222 uint_t cache_disable : 1;
227 ullong_t pdp_base_addr : 40;
228 uint_t available : 11;
229 uint_t no_execute : 1;
233 typedef struct pdpe64 {
236 uint_t user_page : 1;
237 uint_t write_through : 1;
238 uint_t cache_disable : 1;
241 uint_t large_page : 1;
244 ullong_t pd_base_addr : 40;
245 uint_t available : 11;
246 uint_t no_execute : 1;
252 typedef struct pde64 {
255 uint_t user_page : 1;
256 uint_t write_through : 1;
257 uint_t cache_disable : 1;
260 uint_t large_page : 1;
261 uint_t reserved2 : 1;
263 ullong_t pt_base_addr : 40;
264 uint_t available : 11;
265 uint_t no_execute : 1;
268 typedef struct pte64 {
271 uint_t user_page : 1;
272 uint_t write_through : 1;
273 uint_t cache_disable : 1;
277 uint_t global_page : 1;
279 ullong_t page_base_addr : 40;
280 uint_t available : 11;
281 uint_t no_execute : 1;
284 /* *************** */
286 typedef struct pf_error_code {
287 uint_t present : 1; // if 0, fault due to page not present
288 uint_t write : 1; // if 1, faulting access was a write
289 uint_t user : 1; // if 1, faulting access was in user mode
290 uint_t rsvd_access : 1; // if 1, fault from reading a 1 from a reserved field (?)
291 uint_t ifetch : 1; // if 1, faulting access was an instr fetch (only with NX)
298 void delete_page_tables_pde32(pde32_t * pde);
301 pde32_entry_type_t pde32_lookup(pde32_t * pd, addr_t addr, addr_t * entry);
302 int pte32_lookup(pte32_t * pte, addr_t addr, addr_t * entry);
304 // This assumes that the page table resides in the host address space
305 // IE. IT DOES NO VM ADDR TRANSLATION
306 int pt32_lookup(pde32_t * pd, addr_t vaddr, addr_t * paddr);
310 pt_access_status_t can_access_pde32(pde32_t * pde, addr_t addr, pf_error_t access_type);
311 pt_access_status_t can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
319 pde32_t * create_passthrough_pts_32(struct guest_info * guest_info);
320 pml4e64_t * create_passthrough_pts_64(struct guest_info * info);
326 void PrintDebugPageTables(pde32_t * pde);
331 void PrintPT32(addr_t starting_address, pte32_t * pte);
332 void PrintPD32(pde32_t * pde);
333 void PrintPTE32(addr_t virtual_address, pte32_t * pte);
334 void PrintPDE32(addr_t virtual_address, pde32_t * pde);
335 void PrintPTE64(addr_t virtual_address, pte64_t * pte);