2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm_types.h>
22 /* .... Giant fucking switch tables */
138 static int get_addr_width(struct guest_info * info, struct x86_instr * instr) {
140 switch (v3_get_vm_cpu_mode(info)) {
142 return (instr->prefixes.addr_size) ? 4 : 2;
148 if (info->segments.cs.db) {
149 return (instr->prefixes.addr_size) ? 2 : 4;
151 return (instr->prefixes.addr_size) ? 4 : 2;
154 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
159 static int get_operand_width(struct guest_info * info, struct x86_instr * instr,
260 switch (v3_get_vm_cpu_mode(info)) {
262 return (instr->prefixes.op_size) ? 4 : 2;
264 if (instr->prefixes.rex_op_size) {
267 return (instr->prefixes.op_size) ? 2 : 4;
272 if (info->segments.cs.db) {
274 return (instr->prefixes.op_size) ? 2 : 4;
276 return (instr->prefixes.op_size) ? 4 : 2;
279 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
283 switch (v3_get_vm_cpu_mode(info)) {
285 PrintError("Invalid instruction given operating mode (%d)\n", form);
294 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
300 switch (v3_get_vm_cpu_mode(info)) {
310 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
319 switch (v3_get_vm_cpu_mode(info)) {
329 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
336 PrintError("Unsupported instruction form %d\n", form);
346 typedef enum {INVALID_ADDR_TYPE, REG, DISP0, DISP8, DISP16, DISP32} modrm_mode_t;
347 typedef enum {INVALID_REG_SIZE, REG64, REG32, REG16, REG8} reg_size_t;
354 } __attribute__((packed));
361 } __attribute__((packed));
368 static inline int decode_gpr(struct guest_info * core,
370 struct x86_operand * reg) {
372 struct v3_gprs * gprs = &(core->vm_regs);
376 reg->operand = (addr_t)&(gprs->rax);
379 reg->operand = (addr_t)&(gprs->rcx);
382 reg->operand = (addr_t)&(gprs->rdx);
385 reg->operand = (addr_t)&(gprs->rbx);
388 if (reg->size == 1) {
389 reg->operand = (addr_t)&(gprs->rax) + 1;
391 reg->operand = (addr_t)&(gprs->rsp);
395 if (reg->size == 1) {
396 reg->operand = (addr_t)&(gprs->rcx) + 1;
398 reg->operand = (addr_t)&(gprs->rbp);
402 if (reg->size == 1) {
403 reg->operand = (addr_t)&(gprs->rdx) + 1;
405 reg->operand = (addr_t)&(gprs->rsi);
409 if (reg->size == 1) {
410 reg->operand = (addr_t)&(gprs->rbx) + 1;
412 reg->operand = (addr_t)&(gprs->rdi);
416 reg->operand = (addr_t)&(gprs->r8);
419 reg->operand = (addr_t)&(gprs->r9);
422 reg->operand = (addr_t)&(gprs->r10);
425 reg->operand = (addr_t)&(gprs->r11);
428 reg->operand = (addr_t)&(gprs->r12);
431 reg->operand = (addr_t)&(gprs->r13);
434 reg->operand = (addr_t)&(gprs->r14);
437 reg->operand = (addr_t)&(gprs->r15);
440 PrintError("Invalid Reg Code (%d)\n", reg_code);
451 static inline int decode_cr(struct guest_info * core,
453 struct x86_operand * reg) {
455 struct v3_ctrl_regs * crs = &(core->ctrl_regs);
457 // PrintDebug("\t Ctrl regs %d\n", reg_code);
461 reg->operand = (addr_t)&(crs->cr0);
464 reg->operand = (addr_t)&(crs->cr2);
467 reg->operand = (addr_t)&(crs->cr3);
470 reg->operand = (addr_t)&(crs->cr4);
474 PrintError("Invalid Reg Code (%d)\n", reg_code);
483 #define ADDR_MASK(val, length) ({ \
484 ullong_t mask = 0x0LL; \
487 mask = 0x00000000000fffffLL; \
490 mask = 0x00000000ffffffffLL; \
493 mask = 0xffffffffffffffffLL; \
501 static int decode_rm_operand16(struct guest_info * core,
502 uint8_t * modrm_instr,
503 struct x86_instr * instr,
504 struct x86_operand * operand,
505 uint8_t * reg_code) {
507 struct v3_gprs * gprs = &(core->vm_regs);
508 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
509 addr_t base_addr = 0;
510 modrm_mode_t mod_mode = 0;
511 uint8_t * instr_cursor = modrm_instr;
513 // PrintDebug("ModRM mod=%d\n", modrm->mod);
515 *reg_code = modrm->reg;
519 if (modrm->mod == 3) {
520 //PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
521 operand->type = REG_OPERAND;
523 decode_gpr(core, modrm->rm, operand);
526 struct v3_segment * seg = NULL;
528 operand->type = MEM_OPERAND;
530 if (modrm->mod == 0) {
532 } else if (modrm->mod == 1) {
534 } else if (modrm->mod == 2) {
537 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
538 v3_print_instr(instr);
544 base_addr = gprs->rbx + ADDR_MASK(gprs->rsi, 2);
547 base_addr = gprs->rbx + ADDR_MASK(gprs->rdi, 2);
550 base_addr = gprs->rbp + ADDR_MASK(gprs->rsi, 2);
553 base_addr = gprs->rbp + ADDR_MASK(gprs->rdi, 2);
556 base_addr = ADDR_MASK(gprs->rsi, 2);
559 base_addr = ADDR_MASK(gprs->rdi, 2);
562 if (modrm->mod == 0) {
566 base_addr = ADDR_MASK(gprs->rbp, 2);
570 base_addr = ADDR_MASK(gprs->rbx, 2);
576 if (mod_mode == DISP8) {
577 base_addr += *(sint8_t *)instr_cursor;
579 } else if (mod_mode == DISP16) {
580 base_addr += *(sint16_t *)instr_cursor;
585 // get appropriate segment
586 if (instr->prefixes.cs_override) {
587 seg = &(core->segments.cs);
588 } else if (instr->prefixes.es_override) {
589 seg = &(core->segments.es);
590 } else if (instr->prefixes.ss_override) {
591 seg = &(core->segments.ss);
592 } else if (instr->prefixes.fs_override) {
593 seg = &(core->segments.fs);
594 } else if (instr->prefixes.gs_override) {
595 seg = &(core->segments.gs);
597 seg = &(core->segments.ds);
600 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
601 get_addr_width(core, instr));
605 return (instr_cursor - modrm_instr);
609 // returns num_bytes parsed
610 static int decode_rm_operand32(struct guest_info * core,
611 uint8_t * modrm_instr,
612 struct x86_instr * instr,
613 struct x86_operand * operand,
614 uint8_t * reg_code) {
616 struct v3_gprs * gprs = &(core->vm_regs);
617 uint8_t * instr_cursor = modrm_instr;
618 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
619 addr_t base_addr = 0;
620 modrm_mode_t mod_mode = 0;
621 uint_t has_sib_byte = 0;
624 *reg_code = modrm->reg;
628 if (modrm->mod == 3) {
629 operand->type = REG_OPERAND;
630 // PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
632 decode_gpr(core, modrm->rm, operand);
635 struct v3_segment * seg = NULL;
637 operand->type = MEM_OPERAND;
639 if (modrm->mod == 0) {
641 } else if (modrm->mod == 1) {
643 } else if (modrm->mod == 2) {
646 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
647 v3_print_instr(instr);
653 base_addr = gprs->rax;
656 base_addr = gprs->rcx;
659 base_addr = gprs->rdx;
662 base_addr = gprs->rbx;
668 if (modrm->mod == 0) {
672 base_addr = gprs->rbp;
676 base_addr = gprs->rsi;
679 base_addr = gprs->rdi;
684 struct sib_byte * sib = (struct sib_byte *)(instr_cursor);
685 int scale = 0x1 << sib->scale;
689 switch (sib->index) {
691 base_addr = gprs->rax;
694 base_addr = gprs->rcx;
697 base_addr = gprs->rdx;
700 base_addr = gprs->rbx;
706 base_addr = gprs->rbp;
709 base_addr = gprs->rsi;
712 base_addr = gprs->rdi;
721 base_addr += ADDR_MASK(gprs->rax, 4);
724 base_addr += ADDR_MASK(gprs->rcx, 4);
727 base_addr += ADDR_MASK(gprs->rdx, 4);
730 base_addr += ADDR_MASK(gprs->rbx, 4);
733 base_addr += ADDR_MASK(gprs->rsp, 4);
736 if (modrm->mod != 0) {
737 base_addr += ADDR_MASK(gprs->rbp, 4);
744 base_addr += ADDR_MASK(gprs->rsi, 4);
747 base_addr += ADDR_MASK(gprs->rdi, 4);
754 if (mod_mode == DISP8) {
755 base_addr += *(sint8_t *)instr_cursor;
757 } else if (mod_mode == DISP32) {
758 base_addr += *(sint32_t *)instr_cursor;
762 // get appropriate segment
763 if (instr->prefixes.cs_override) {
764 seg = &(core->segments.cs);
765 } else if (instr->prefixes.es_override) {
766 seg = &(core->segments.es);
767 } else if (instr->prefixes.ss_override) {
768 seg = &(core->segments.ss);
769 } else if (instr->prefixes.fs_override) {
770 seg = &(core->segments.fs);
771 } else if (instr->prefixes.gs_override) {
772 seg = &(core->segments.gs);
774 seg = &(core->segments.ds);
777 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
778 get_addr_width(core, instr));
782 return (instr_cursor - modrm_instr);
786 int decode_rm_operand64(struct guest_info * core, uint8_t * modrm_instr,
787 struct x86_instr * instr, struct x86_operand * operand,
788 uint8_t * reg_code) {
790 struct v3_gprs * gprs = &(core->vm_regs);
791 uint8_t * instr_cursor = modrm_instr;
792 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
793 addr_t base_addr = 0;
794 modrm_mode_t mod_mode = 0;
795 uint_t has_sib_byte = 0;
800 *reg_code = modrm->reg;
801 *reg_code |= (instr->prefixes.rex_reg << 3);
803 if (modrm->mod == 3) {
804 uint8_t rm_val = modrm->rm;
806 rm_val |= (instr->prefixes.rex_rm << 3);
808 operand->type = REG_OPERAND;
809 // PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
811 decode_gpr(core, rm_val, operand);
813 struct v3_segment * seg = NULL;
814 uint8_t rm_val = modrm->rm;
816 operand->type = MEM_OPERAND;
819 if (modrm->mod == 0) {
821 } else if (modrm->mod == 1) {
823 } else if (modrm->mod == 2) {
826 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
827 v3_print_instr(instr);
834 rm_val |= (instr->prefixes.rex_rm << 3);
838 base_addr = gprs->rax;
841 base_addr = gprs->rcx;
844 base_addr = gprs->rdx;
847 base_addr = gprs->rbx;
850 if (modrm->mod == 0) {
854 base_addr = gprs->rbp;
858 base_addr = gprs->rsi;
861 base_addr = gprs->rdi;
864 base_addr = gprs->r8;
867 base_addr = gprs->r9;
870 base_addr = gprs->r10;
873 base_addr = gprs->r11;
876 base_addr = gprs->r12;
879 base_addr = gprs->r13;
882 base_addr = gprs->r14;
885 base_addr = gprs->r15;
893 struct sib_byte * sib = (struct sib_byte *)(instr_cursor);
894 int scale = 0x1 << sib->scale;
895 uint8_t index_val = sib->index;
896 uint8_t base_val = sib->base;
898 index_val |= (instr->prefixes.rex_sib_idx << 3);
899 base_val |= (instr->prefixes.rex_rm << 3);
905 base_addr = gprs->rax;
908 base_addr = gprs->rcx;
911 base_addr = gprs->rdx;
914 base_addr = gprs->rbx;
920 base_addr = gprs->rbp;
923 base_addr = gprs->rsi;
926 base_addr = gprs->rdi;
929 base_addr = gprs->r8;
932 base_addr = gprs->r9;
935 base_addr = gprs->r10;
938 base_addr = gprs->r11;
941 base_addr = gprs->r12;
944 base_addr = gprs->r13;
947 base_addr = gprs->r14;
950 base_addr = gprs->r15;
959 base_addr += gprs->rax;
962 base_addr += gprs->rcx;
965 base_addr += gprs->rdx;
968 base_addr += gprs->rbx;
971 base_addr += gprs->rsp;
974 if (modrm->mod != 0) {
975 base_addr += gprs->rbp;
982 base_addr += gprs->rsi;
985 base_addr += gprs->rdi;
988 base_addr += gprs->r8;
991 base_addr += gprs->r9;
994 base_addr += gprs->r10;
997 base_addr += gprs->r11;
1000 base_addr += gprs->r12;
1003 base_addr += gprs->r13;
1006 base_addr += gprs->r14;
1009 base_addr += gprs->r15;
1016 if (mod_mode == DISP8) {
1017 base_addr += *(sint8_t *)instr_cursor;
1019 } else if (mod_mode == DISP32) {
1020 base_addr += *(sint32_t *)instr_cursor;
1026 //Segments should be ignored
1027 // get appropriate segment
1029 if (instr->prefixes.cs_override) {
1030 seg = &(core->segments.cs);
1031 } else if (instr->prefixes.es_override) {
1032 seg = &(core->segments.es);
1033 } else if (instr->prefixes.ss_override) {
1034 seg = &(core->segments.ss);
1035 } else if (instr->prefixes.fs_override) {
1036 seg = &(core->segments.fs);
1037 } else if (instr->prefixes.gs_override) {
1038 seg = &(core->segments.gs);
1040 seg = &(core->segments.ds);
1044 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
1045 get_addr_width(core, instr));
1049 return (instr_cursor - modrm_instr);
1055 static int decode_rm_operand(struct guest_info * core,
1056 uint8_t * instr_ptr, // input
1058 struct x86_instr * instr,
1059 struct x86_operand * operand,
1060 uint8_t * reg_code) {
1062 v3_cpu_mode_t mode = v3_get_vm_cpu_mode(core);
1064 operand->size = get_operand_width(core, instr, form);
1068 return decode_rm_operand16(core, instr_ptr, instr, operand, reg_code);
1070 if (instr->prefixes.rex) {
1071 return decode_rm_operand64(core, instr_ptr, instr, operand, reg_code);
1075 case LONG_32_COMPAT:
1076 return decode_rm_operand32(core, instr_ptr, instr, operand, reg_code);
1078 PrintError("Invalid CPU_MODE (%d)\n", mode);
1085 static inline op_form_t op_code_to_form_0f(uint8_t * instr, int * length) {
1090 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[2]);
1092 switch (modrm->reg) {
1100 return INVALID_INSTR;
1161 return INVALID_INSTR;
1166 static op_form_t op_code_to_form(uint8_t * instr, int * length) {
1190 return op_code_to_form_0f(instr, length);
1230 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1232 switch (modrm->reg) {
1246 return INVALID_INSTR;
1250 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1252 switch (modrm->reg) {
1266 return INVALID_INSTR;
1270 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1272 switch (modrm->reg) {
1274 return ADD_IMM2SX_8;
1278 return ADC_IMM2SX_8;
1280 return AND_IMM2SX_8;
1282 return SUB_IMM2SX_8;
1284 return XOR_IMM2SX_8;
1286 return INVALID_INSTR;
1315 return MOV_MEM2AL_8;
1319 return MOV_AL2MEM_8;
1345 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1347 switch (modrm->reg) {
1353 return INVALID_INSTR;
1357 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1359 switch (modrm->reg) {
1365 return INVALID_INSTR;
1371 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1373 switch (modrm->reg) {
1379 return INVALID_INSTR;
1384 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1386 switch (modrm->reg) {
1392 return INVALID_INSTR;
1397 return INVALID_INSTR;
1403 static char * op_form_to_str(op_form_t form) {
1406 case LMSW: return "LMSW";
1407 case SMSW: return "SMSW";
1408 case CLTS: return "CLTS";
1409 case INVLPG: return "INVLPG";
1410 case MOV_CR2: return "MOV_CR2";
1411 case MOV_2CR: return "MOV_2CR";
1412 case MOV_DR2: return "MOV_DR2";
1413 case MOV_2DR: return "MOV_2DR";
1414 case MOV_SR2: return "MOV_SR2";
1415 case MOV_2SR: return "MOV_2SR";
1416 case MOV_MEM2_8: return "MOV_MEM2_8";
1417 case MOV_MEM2: return "MOV_MEM2";
1418 case MOV_2MEM_8: return "MOV_2MEM_8";
1419 case MOV_2MEM: return "MOV_2MEM";
1420 case MOV_MEM2AL_8: return "MOV_MEM2AL_8";
1421 case MOV_MEM2AX: return "MOV_MEM2AX";
1422 case MOV_AL2MEM_8: return "MOV_AL2MEM_8";
1423 case MOV_AX2MEM: return "MOV_AX2MEM";
1424 case MOV_IMM2_8: return "MOV_IMM2_8";
1425 case MOV_IMM2: return "MOV_IMM2";
1426 case MOVS_8: return "MOVS_8";
1427 case MOVS: return "MOVS";
1428 case MOVSX_8: return "MOVSX_8";
1429 case MOVSX: return "MOVSX";
1430 case MOVZX_8: return "MOVZX_8";
1431 case MOVZX: return "MOVZX";
1432 case HLT: return "HLT";
1433 case PUSHF: return "PUSHF";
1434 case POPF: return "POPF";
1435 case ADC_2MEM_8: return "ADC_2MEM_8";
1436 case ADC_2MEM: return "ADC_2MEM";
1437 case ADC_MEM2_8: return "ADC_MEM2_8";
1438 case ADC_MEM2: return "ADC_MEM2";
1439 case ADC_IMM2_8: return "ADC_IMM2_8";
1440 case ADC_IMM2: return "ADC_IMM2";
1441 case ADC_IMM2SX_8: return "ADC_IMM2SX_8";
1442 case ADD_IMM2_8: return "ADD_IMM2_8";
1443 case ADD_IMM2: return "ADD_IMM2";
1444 case ADD_IMM2SX_8: return "ADD_IMM2SX_8";
1445 case ADD_2MEM_8: return "ADD_2MEM_8";
1446 case ADD_2MEM: return "ADD_2MEM";
1447 case ADD_MEM2_8: return "ADD_MEM2_8";
1448 case ADD_MEM2: return "ADD_MEM2";
1449 case AND_MEM2_8: return "AND_MEM2_8";
1450 case AND_MEM2: return "AND_MEM2";
1451 case AND_2MEM_8: return "AND_2MEM_8";
1452 case AND_2MEM: return "AND_2MEM";
1453 case AND_IMM2_8: return "AND_IMM2_8";
1454 case AND_IMM2: return "AND_IMM2";
1455 case AND_IMM2SX_8: return "AND_IMM2SX_8";
1456 case OR_2MEM_8: return "OR_2MEM_8";
1457 case OR_2MEM: return "OR_2MEM";
1458 case OR_MEM2_8: return "OR_MEM2_8";
1459 case OR_MEM2: return "OR_MEM2";
1460 case OR_IMM2_8: return "OR_IMM2_8";
1461 case OR_IMM2: return "OR_IMM2";
1462 case OR_IMM2SX_8: return "OR_IMM2SX_8";
1463 case SUB_2MEM_8: return "SUB_2MEM_8";
1464 case SUB_2MEM: return "SUB_2MEM";
1465 case SUB_MEM2_8: return "SUB_MEM2_8";
1466 case SUB_MEM2: return "SUB_MEM2";
1467 case SUB_IMM2_8: return "SUB_IMM2_8";
1468 case SUB_IMM2: return "SUB_IMM2";
1469 case SUB_IMM2SX_8: return "SUB_IMM2SX_8";
1470 case XOR_2MEM_8: return "XOR_2MEM_8";
1471 case XOR_2MEM: return "XOR_2MEM";
1472 case XOR_MEM2_8: return "XOR_MEM2_8";
1473 case XOR_MEM2: return "XOR_MEM2";
1474 case XOR_IMM2_8: return "XOR_IMM2_8";
1475 case XOR_IMM2: return "XOR_IMM2";
1476 case XOR_IMM2SX_8: return "XOR_IMM2SX_8";
1477 case INC_8: return "INC_8";
1478 case INC: return "INC";
1479 case DEC_8: return "DEC_8";
1480 case DEC: return "DEC";
1481 case NEG_8: return "NEG_8";
1482 case NEG: return "NEG";
1483 case NOT_8: return "NOT_8";
1484 case NOT: return "NOT";
1485 case XCHG_8: return "XCHG_8";
1486 case XCHG: return "XCHG";
1487 case SETB: return "SETB";
1488 case SETBE: return "SETBE";
1489 case SETL: return "SETL";
1490 case SETLE: return "SETLE";
1491 case SETNB: return "SETNB";
1492 case SETNBE: return "SETNBE";
1493 case SETNL: return "SETNL";
1494 case SETNLE: return "SETNLE";
1495 case SETNO: return "SETNO";
1496 case SETNP: return "SETNP";
1497 case SETNS: return "SETNS";
1498 case SETNZ: return "SETNZ";
1499 case SETP: return "SETP";
1500 case SETS: return "SETS";
1501 case SETZ: return "SETZ";
1502 case SETO: return "SETO";
1503 case STOS_8: return "STOS_8";
1504 case STOS: return "STOS";
1505 case INT: return "INT";
1509 return "INVALID_INSTR";