2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm_types.h>
22 /* .... Giant fucking switch tables */
138 static int get_addr_width(struct guest_info * info, struct x86_instr * instr) {
140 switch (v3_get_vm_cpu_mode(info)) {
142 return (instr->prefixes.addr_size) ? 4 : 2;
148 if (info->segments.cs.db) {
149 return (instr->prefixes.addr_size) ? 2 : 4;
151 return (instr->prefixes.addr_size) ? 4 : 2;
154 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
159 static int get_operand_width(struct guest_info * info, struct x86_instr * instr,
259 switch (v3_get_vm_cpu_mode(info)) {
261 return (instr->prefixes.op_size) ? 4 : 2;
263 if (instr->prefixes.rex_op_size) {
266 return (instr->prefixes.op_size) ? 2 : 4;
271 if (info->segments.cs.db) {
273 return (instr->prefixes.op_size) ? 2 : 4;
275 return (instr->prefixes.op_size) ? 4 : 2;
278 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
282 switch (v3_get_vm_cpu_mode(info)) {
284 PrintError("Invalid instruction given operating mode (%d)\n", form);
293 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
299 switch (v3_get_vm_cpu_mode(info)) {
309 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
318 switch (v3_get_vm_cpu_mode(info)) {
328 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
335 PrintError("Unsupported instruction form %d\n", form);
345 typedef enum {INVALID_ADDR_TYPE, REG, DISP0, DISP8, DISP16, DISP32} modrm_mode_t;
346 typedef enum {INVALID_REG_SIZE, REG64, REG32, REG16, REG8} reg_size_t;
353 } __attribute__((packed));
360 } __attribute__((packed));
367 static inline int decode_gpr(struct guest_info * core,
369 struct x86_operand * reg) {
371 struct v3_gprs * gprs = &(core->vm_regs);
375 reg->operand = (addr_t)&(gprs->rax);
378 reg->operand = (addr_t)&(gprs->rcx);
381 reg->operand = (addr_t)&(gprs->rdx);
384 reg->operand = (addr_t)&(gprs->rbx);
387 if (reg->size == 1) {
388 reg->operand = (addr_t)&(gprs->rax) + 1;
390 reg->operand = (addr_t)&(gprs->rsp);
394 if (reg->size == 1) {
395 reg->operand = (addr_t)&(gprs->rcx) + 1;
397 reg->operand = (addr_t)&(gprs->rbp);
401 if (reg->size == 1) {
402 reg->operand = (addr_t)&(gprs->rdx) + 1;
404 reg->operand = (addr_t)&(gprs->rsi);
408 if (reg->size == 1) {
409 reg->operand = (addr_t)&(gprs->rbx) + 1;
411 reg->operand = (addr_t)&(gprs->rdi);
415 reg->operand = (addr_t)&(gprs->r8);
418 reg->operand = (addr_t)&(gprs->r9);
421 reg->operand = (addr_t)&(gprs->r10);
424 reg->operand = (addr_t)&(gprs->r11);
427 reg->operand = (addr_t)&(gprs->r12);
430 reg->operand = (addr_t)&(gprs->r13);
433 reg->operand = (addr_t)&(gprs->r14);
436 reg->operand = (addr_t)&(gprs->r15);
439 PrintError("Invalid Reg Code (%d)\n", reg_code);
450 static inline int decode_cr(struct guest_info * core,
452 struct x86_operand * reg) {
454 struct v3_ctrl_regs * crs = &(core->ctrl_regs);
456 // PrintDebug("\t Ctrl regs %d\n", reg_code);
460 reg->operand = (addr_t)&(crs->cr0);
463 reg->operand = (addr_t)&(crs->cr2);
466 reg->operand = (addr_t)&(crs->cr3);
469 reg->operand = (addr_t)&(crs->cr4);
473 PrintError("Invalid Reg Code (%d)\n", reg_code);
482 #define ADDR_MASK(val, length) ({ \
483 ullong_t mask = 0x0LL; \
486 mask = 0x00000000000fffffLL; \
489 mask = 0x00000000ffffffffLL; \
492 mask = 0xffffffffffffffffLL; \
500 static int decode_rm_operand16(struct guest_info * core,
501 uint8_t * modrm_instr,
502 struct x86_instr * instr,
503 struct x86_operand * operand,
504 uint8_t * reg_code) {
506 struct v3_gprs * gprs = &(core->vm_regs);
507 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
508 addr_t base_addr = 0;
509 modrm_mode_t mod_mode = 0;
510 uint8_t * instr_cursor = modrm_instr;
512 // PrintDebug("ModRM mod=%d\n", modrm->mod);
514 *reg_code = modrm->reg;
518 if (modrm->mod == 3) {
519 //PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
520 operand->type = REG_OPERAND;
522 decode_gpr(core, modrm->rm, operand);
525 struct v3_segment * seg = NULL;
527 operand->type = MEM_OPERAND;
529 if (modrm->mod == 0) {
531 } else if (modrm->mod == 1) {
533 } else if (modrm->mod == 2) {
536 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
537 v3_print_instr(instr);
543 base_addr = gprs->rbx + ADDR_MASK(gprs->rsi, 2);
546 base_addr = gprs->rbx + ADDR_MASK(gprs->rdi, 2);
549 base_addr = gprs->rbp + ADDR_MASK(gprs->rsi, 2);
552 base_addr = gprs->rbp + ADDR_MASK(gprs->rdi, 2);
555 base_addr = ADDR_MASK(gprs->rsi, 2);
558 base_addr = ADDR_MASK(gprs->rdi, 2);
561 if (modrm->mod == 0) {
565 base_addr = ADDR_MASK(gprs->rbp, 2);
569 base_addr = ADDR_MASK(gprs->rbx, 2);
575 if (mod_mode == DISP8) {
576 base_addr += *(sint8_t *)instr_cursor;
578 } else if (mod_mode == DISP16) {
579 base_addr += *(sint16_t *)instr_cursor;
584 // get appropriate segment
585 if (instr->prefixes.cs_override) {
586 seg = &(core->segments.cs);
587 } else if (instr->prefixes.es_override) {
588 seg = &(core->segments.es);
589 } else if (instr->prefixes.ss_override) {
590 seg = &(core->segments.ss);
591 } else if (instr->prefixes.fs_override) {
592 seg = &(core->segments.fs);
593 } else if (instr->prefixes.gs_override) {
594 seg = &(core->segments.gs);
596 seg = &(core->segments.ds);
599 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
600 get_addr_width(core, instr));
604 return (instr_cursor - modrm_instr);
608 // returns num_bytes parsed
609 static int decode_rm_operand32(struct guest_info * core,
610 uint8_t * modrm_instr,
611 struct x86_instr * instr,
612 struct x86_operand * operand,
613 uint8_t * reg_code) {
615 struct v3_gprs * gprs = &(core->vm_regs);
616 uint8_t * instr_cursor = modrm_instr;
617 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
618 addr_t base_addr = 0;
619 modrm_mode_t mod_mode = 0;
620 uint_t has_sib_byte = 0;
623 *reg_code = modrm->reg;
627 if (modrm->mod == 3) {
628 operand->type = REG_OPERAND;
629 // PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
631 decode_gpr(core, modrm->rm, operand);
634 struct v3_segment * seg = NULL;
636 operand->type = MEM_OPERAND;
638 if (modrm->mod == 0) {
640 } else if (modrm->mod == 1) {
642 } else if (modrm->mod == 2) {
645 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
646 v3_print_instr(instr);
652 base_addr = gprs->rax;
655 base_addr = gprs->rcx;
658 base_addr = gprs->rdx;
661 base_addr = gprs->rbx;
667 if (modrm->mod == 0) {
671 base_addr = gprs->rbp;
675 base_addr = gprs->rsi;
678 base_addr = gprs->rdi;
684 struct sib_byte * sib = (struct sib_byte *)(instr_cursor);
685 int scale = 0x1 << sib->scale;
689 switch (sib->index) {
691 base_addr = gprs->rax;
694 base_addr = gprs->rcx;
697 base_addr = gprs->rdx;
700 base_addr = gprs->rbx;
706 base_addr = gprs->rbp;
709 base_addr = gprs->rsi;
712 base_addr = gprs->rdi;
721 base_addr += ADDR_MASK(gprs->rax, 4);
724 base_addr += ADDR_MASK(gprs->rcx, 4);
727 base_addr += ADDR_MASK(gprs->rdx, 4);
730 base_addr += ADDR_MASK(gprs->rbx, 4);
733 base_addr += ADDR_MASK(gprs->rsp, 4);
736 if (modrm->mod != 0) {
737 base_addr += ADDR_MASK(gprs->rbp, 4);
741 base_addr += ADDR_MASK(gprs->rsi, 4);
744 base_addr += ADDR_MASK(gprs->rdi, 4);
751 if (mod_mode == DISP8) {
752 base_addr += *(sint8_t *)instr_cursor;
754 } else if (mod_mode == DISP32) {
755 base_addr += *(sint32_t *)instr_cursor;
759 // get appropriate segment
760 if (instr->prefixes.cs_override) {
761 seg = &(core->segments.cs);
762 } else if (instr->prefixes.es_override) {
763 seg = &(core->segments.es);
764 } else if (instr->prefixes.ss_override) {
765 seg = &(core->segments.ss);
766 } else if (instr->prefixes.fs_override) {
767 seg = &(core->segments.fs);
768 } else if (instr->prefixes.gs_override) {
769 seg = &(core->segments.gs);
771 seg = &(core->segments.ds);
774 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
775 get_addr_width(core, instr));
779 return (instr_cursor - modrm_instr);
783 int decode_rm_operand64(struct guest_info * core, uint8_t * modrm_instr,
784 struct x86_instr * instr, struct x86_operand * operand,
785 uint8_t * reg_code) {
787 struct v3_gprs * gprs = &(core->vm_regs);
788 uint8_t * instr_cursor = modrm_instr;
789 struct modrm_byte * modrm = (struct modrm_byte *)modrm_instr;
790 addr_t base_addr = 0;
791 modrm_mode_t mod_mode = 0;
792 uint_t has_sib_byte = 0;
797 *reg_code = modrm->reg;
798 *reg_code |= (instr->prefixes.rex_reg << 3);
800 if (modrm->mod == 3) {
801 uint8_t rm_val = modrm->rm;
803 rm_val |= (instr->prefixes.rex_rm << 3);
805 operand->type = REG_OPERAND;
806 // PrintDebug("first operand = Register (RM=%d)\n",modrm->rm);
808 decode_gpr(core, rm_val, operand);
810 struct v3_segment * seg = NULL;
811 uint8_t rm_val = modrm->rm;
813 operand->type = MEM_OPERAND;
816 if (modrm->mod == 0) {
818 } else if (modrm->mod == 1) {
820 } else if (modrm->mod == 2) {
823 PrintError("Instruction format error: Invalid mod_rm mode (%d)\n", modrm->mod);
824 v3_print_instr(instr);
831 rm_val |= (instr->prefixes.rex_rm << 3);
835 base_addr = gprs->rax;
838 base_addr = gprs->rcx;
841 base_addr = gprs->rdx;
844 base_addr = gprs->rbx;
847 if (modrm->mod == 0) {
851 base_addr = gprs->rbp;
855 base_addr = gprs->rsi;
858 base_addr = gprs->rdi;
861 base_addr = gprs->r8;
864 base_addr = gprs->r9;
867 base_addr = gprs->r10;
870 base_addr = gprs->r11;
873 base_addr = gprs->r12;
876 base_addr = gprs->r13;
879 base_addr = gprs->r14;
882 base_addr = gprs->r15;
891 struct sib_byte * sib = (struct sib_byte *)(instr_cursor);
892 int scale = 0x1 << sib->scale;
893 uint8_t index_val = sib->index;
894 uint8_t base_val = sib->base;
896 index_val |= (instr->prefixes.rex_sib_idx << 3);
897 base_val |= (instr->prefixes.rex_rm << 3);
903 base_addr = gprs->rax;
906 base_addr = gprs->rcx;
909 base_addr = gprs->rdx;
912 base_addr = gprs->rbx;
918 base_addr = gprs->rbp;
921 base_addr = gprs->rsi;
924 base_addr = gprs->rdi;
927 base_addr = gprs->r8;
930 base_addr = gprs->r9;
933 base_addr = gprs->r10;
936 base_addr = gprs->r11;
939 base_addr = gprs->r12;
942 base_addr = gprs->r13;
945 base_addr = gprs->r14;
948 base_addr = gprs->r15;
957 base_addr += gprs->rax;
960 base_addr += gprs->rcx;
963 base_addr += gprs->rdx;
966 base_addr += gprs->rbx;
969 base_addr += gprs->rsp;
972 if (modrm->mod != 0) {
973 base_addr += gprs->rbp;
977 base_addr += gprs->rsi;
980 base_addr += gprs->rdi;
983 base_addr += gprs->r8;
986 base_addr += gprs->r9;
989 base_addr += gprs->r10;
992 base_addr += gprs->r11;
995 base_addr += gprs->r12;
998 base_addr += gprs->r13;
1001 base_addr += gprs->r14;
1004 base_addr += gprs->r15;
1011 if (mod_mode == DISP8) {
1012 base_addr += *(sint8_t *)instr_cursor;
1014 } else if (mod_mode == DISP32) {
1015 base_addr += *(sint32_t *)instr_cursor;
1021 //Segments should be ignored
1022 // get appropriate segment
1024 if (instr->prefixes.cs_override) {
1025 seg = &(core->segments.cs);
1026 } else if (instr->prefixes.es_override) {
1027 seg = &(core->segments.es);
1028 } else if (instr->prefixes.ss_override) {
1029 seg = &(core->segments.ss);
1030 } else if (instr->prefixes.fs_override) {
1031 seg = &(core->segments.fs);
1032 } else if (instr->prefixes.gs_override) {
1033 seg = &(core->segments.gs);
1035 seg = &(core->segments.ds);
1039 operand->operand = ADDR_MASK(get_addr_linear(core, base_addr, seg),
1040 get_addr_width(core, instr));
1044 return (instr_cursor - modrm_instr);
1050 static int decode_rm_operand(struct guest_info * core,
1051 uint8_t * instr_ptr, // input
1053 struct x86_instr * instr,
1054 struct x86_operand * operand,
1055 uint8_t * reg_code) {
1057 v3_cpu_mode_t mode = v3_get_vm_cpu_mode(core);
1059 operand->size = get_operand_width(core, instr, form);
1063 return decode_rm_operand16(core, instr_ptr, instr, operand, reg_code);
1065 if (instr->prefixes.rex) {
1066 return decode_rm_operand64(core, instr_ptr, instr, operand, reg_code);
1070 case LONG_32_COMPAT:
1071 return decode_rm_operand32(core, instr_ptr, instr, operand, reg_code);
1073 PrintError("Invalid CPU_MODE (%d)\n", mode);
1080 static inline op_form_t op_code_to_form_0f(uint8_t * instr, int * length) {
1085 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[2]);
1087 switch (modrm->reg) {
1095 return INVALID_INSTR;
1156 return INVALID_INSTR;
1161 static op_form_t op_code_to_form(uint8_t * instr, int * length) {
1185 return op_code_to_form_0f(instr, length);
1225 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1227 switch (modrm->reg) {
1241 return INVALID_INSTR;
1245 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1247 switch (modrm->reg) {
1261 return INVALID_INSTR;
1265 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1267 switch (modrm->reg) {
1269 return ADD_IMM2SX_8;
1273 return ADC_IMM2SX_8;
1275 return AND_IMM2SX_8;
1277 return SUB_IMM2SX_8;
1279 return XOR_IMM2SX_8;
1281 return INVALID_INSTR;
1310 return MOV_MEM2AL_8;
1314 return MOV_AL2MEM_8;
1340 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1342 switch (modrm->reg) {
1348 return INVALID_INSTR;
1352 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1354 switch (modrm->reg) {
1360 return INVALID_INSTR;
1366 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1368 switch (modrm->reg) {
1374 return INVALID_INSTR;
1379 struct modrm_byte * modrm = (struct modrm_byte *)&(instr[1]);
1381 switch (modrm->reg) {
1387 return INVALID_INSTR;
1392 return INVALID_INSTR;
1398 static char * op_form_to_str(op_form_t form) {
1401 case LMSW: return "LMSW";
1402 case SMSW: return "SMSW";
1403 case CLTS: return "CLTS";
1404 case INVLPG: return "INVLPG";
1405 case MOV_CR2: return "MOV_CR2";
1406 case MOV_2CR: return "MOV_2CR";
1407 case MOV_DR2: return "MOV_DR2";
1408 case MOV_2DR: return "MOV_2DR";
1409 case MOV_SR2: return "MOV_SR2";
1410 case MOV_2SR: return "MOV_2SR";
1411 case MOV_MEM2_8: return "MOV_MEM2_8";
1412 case MOV_MEM2: return "MOV_MEM2";
1413 case MOV_2MEM_8: return "MOV_2MEM_8";
1414 case MOV_2MEM: return "MOV_2MEM";
1415 case MOV_MEM2AL_8: return "MOV_MEM2AL_8";
1416 case MOV_MEM2AX: return "MOV_MEM2AX";
1417 case MOV_AL2MEM_8: return "MOV_AL2MEM_8";
1418 case MOV_AX2MEM: return "MOV_AX2MEM";
1419 case MOV_IMM2_8: return "MOV_IMM2_8";
1420 case MOV_IMM2: return "MOV_IMM2";
1421 case MOVS_8: return "MOVS_8";
1422 case MOVS: return "MOVS";
1423 case MOVSX_8: return "MOVSX_8";
1424 case MOVSX: return "MOVSX";
1425 case MOVZX_8: return "MOVZX_8";
1426 case MOVZX: return "MOVZX";
1427 case HLT: return "HLT";
1428 case PUSHF: return "PUSHF";
1429 case POPF: return "POPF";
1430 case ADC_2MEM_8: return "ADC_2MEM_8";
1431 case ADC_2MEM: return "ADC_2MEM";
1432 case ADC_MEM2_8: return "ADC_MEM2_8";
1433 case ADC_MEM2: return "ADC_MEM2";
1434 case ADC_IMM2_8: return "ADC_IMM2_8";
1435 case ADC_IMM2: return "ADC_IMM2";
1436 case ADC_IMM2SX_8: return "ADC_IMM2SX_8";
1437 case ADD_IMM2_8: return "ADD_IMM2_8";
1438 case ADD_IMM2: return "ADD_IMM2";
1439 case ADD_IMM2SX_8: return "ADD_IMM2SX_8";
1440 case ADD_2MEM_8: return "ADD_2MEM_8";
1441 case ADD_2MEM: return "ADD_2MEM";
1442 case ADD_MEM2_8: return "ADD_MEM2_8";
1443 case ADD_MEM2: return "ADD_MEM2";
1444 case AND_MEM2_8: return "AND_MEM2_8";
1445 case AND_MEM2: return "AND_MEM2";
1446 case AND_2MEM_8: return "AND_2MEM_8";
1447 case AND_2MEM: return "AND_2MEM";
1448 case AND_IMM2_8: return "AND_IMM2_8";
1449 case AND_IMM2: return "AND_IMM2";
1450 case AND_IMM2SX_8: return "AND_IMM2SX_8";
1451 case OR_2MEM_8: return "OR_2MEM_8";
1452 case OR_2MEM: return "OR_2MEM";
1453 case OR_MEM2_8: return "OR_MEM2_8";
1454 case OR_MEM2: return "OR_MEM2";
1455 case OR_IMM2_8: return "OR_IMM2_8";
1456 case OR_IMM2: return "OR_IMM2";
1457 case OR_IMM2SX_8: return "OR_IMM2SX_8";
1458 case SUB_2MEM_8: return "SUB_2MEM_8";
1459 case SUB_2MEM: return "SUB_2MEM";
1460 case SUB_MEM2_8: return "SUB_MEM2_8";
1461 case SUB_MEM2: return "SUB_MEM2";
1462 case SUB_IMM2_8: return "SUB_IMM2_8";
1463 case SUB_IMM2: return "SUB_IMM2";
1464 case SUB_IMM2SX_8: return "SUB_IMM2SX_8";
1465 case XOR_2MEM_8: return "XOR_2MEM_8";
1466 case XOR_2MEM: return "XOR_2MEM";
1467 case XOR_MEM2_8: return "XOR_MEM2_8";
1468 case XOR_MEM2: return "XOR_MEM2";
1469 case XOR_IMM2_8: return "XOR_IMM2_8";
1470 case XOR_IMM2: return "XOR_IMM2";
1471 case XOR_IMM2SX_8: return "XOR_IMM2SX_8";
1472 case INC_8: return "INC_8";
1473 case INC: return "INC";
1474 case DEC_8: return "DEC_8";
1475 case DEC: return "DEC";
1476 case NEG_8: return "NEG_8";
1477 case NEG: return "NEG";
1478 case NOT_8: return "NOT_8";
1479 case NOT: return "NOT";
1480 case XCHG_8: return "XCHG_8";
1481 case XCHG: return "XCHG";
1482 case SETB: return "SETB";
1483 case SETBE: return "SETBE";
1484 case SETL: return "SETL";
1485 case SETLE: return "SETLE";
1486 case SETNB: return "SETNB";
1487 case SETNBE: return "SETNBE";
1488 case SETNL: return "SETNL";
1489 case SETNLE: return "SETNLE";
1490 case SETNO: return "SETNO";
1491 case SETNP: return "SETNP";
1492 case SETNS: return "SETNS";
1493 case SETNZ: return "SETNZ";
1494 case SETP: return "SETP";
1495 case SETS: return "SETS";
1496 case SETZ: return "SETZ";
1497 case SETO: return "SETO";
1498 case STOS_8: return "STOS_8";
1499 case STOS: return "STOS";
1500 case INT: return "INT";
1504 return "INVALID_INSTR";