1 /* Northwestern University */
2 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
7 #include <palacios/vmm_types.h>
10 /* 16 bit guest state */
11 #define VMCS_GUEST_ES_SELECTOR 0x00000800
12 #define VMCS_GUEST_CS_SELECTOR 0x00000802
13 #define VMCS_GUEST_SS_SELECTOR 0x00000804
14 #define VMCS_GUEST_DS_SELECTOR 0x00000806
15 #define VMCS_GUEST_FS_SELECTOR 0x00000808
16 #define VMCS_GUEST_GS_SELECTOR 0x0000080A
17 #define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
18 #define VMCS_GUEST_TR_SELECTOR 0x0000080E
20 /* 16 bit host state */
21 #define VMCS_HOST_ES_SELECTOR 0x00000C00
22 #define VMCS_HOST_CS_SELECTOR 0x00000C02
23 #define VMCS_HOST_SS_SELECTOR 0x00000C04
24 #define VMCS_HOST_DS_SELECTOR 0x00000C06
25 #define VMCS_HOST_FS_SELECTOR 0x00000C08
26 #define VMCS_HOST_GS_SELECTOR 0x00000C0A
27 #define VMCS_HOST_TR_SELECTOR 0x00000C0C
29 /* 64 bit control fields */
30 #define IO_BITMAP_A_ADDR 0x00002000
31 #define IO_BITMAP_A_ADDR_HIGH 0x00002001
32 #define IO_BITMAP_B_ADDR 0x00002002
33 #define IO_BITMAP_B_ADDR_HIGH 0x00002003
34 // Only with "Use MSR Bitmaps" enabled
35 #define MSR_BITMAPS 0x00002004
36 #define MSR_BITMAPS_HIGH 0x00002005
38 #define VM_EXIT_MSR_STORE_ADDR 0x00002006
39 #define VM_EXIT_MSR_STORE_ADDR_HIGH 0x00002007
40 #define VM_EXIT_MSR_LOAD_ADDR 0x00002008
41 #define VM_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009
42 #define VM_ENTRY_MSR_LOAD_ADDR 0x0000200A
43 #define VM_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200B
44 #define VMCS_EXEC_PTR 0x0000200C
45 #define VMCS_EXEC_PTR_HIGH 0x0000200D
46 #define TSC_OFFSET 0x00002010
47 #define TSC_OFFSET_HIGH 0x00002011
48 // Only with "Use TPR Shadow" enabled
49 #define VIRT_APIC_PAGE_ADDR 0x00002012
50 #define VIRT_APIC_PAGE_ADDR_HIGH 0x00002013
54 /* 64 bit guest state fields */
55 #define VMCS_LINK_PTR 0x00002800
56 #define VMCS_LINK_PTR_HIGH 0x00002801
57 #define GUEST_IA32_DEBUGCTL 0x00002802
58 #define GUEST_IA32_DEBUGCTL_HIGH 0x00002803
61 /* 32 bit control fields */
62 #define PIN_VM_EXEC_CTRLS 0x00004000
63 #define PROC_VM_EXEC_CTRLS 0x00004002
64 #define EXCEPTION_BITMAP 0x00004004
65 #define PAGE_FAULT_ERROR_MASK 0x00004006
66 #define PAGE_FAULT_ERROR_MATCH 0x00004008
67 #define CR3_TARGET_COUNT 0x0000400A
68 #define VM_EXIT_CTRLS 0x0000400C
69 #define VM_EXIT_MSR_STORE_COUNT 0x0000400E
70 #define VM_EXIT_MSR_LOAD_COUNT 0x00004010
71 #define VM_ENTRY_CTRLS 0x00004012
72 #define VM_ENTRY_MSR_LOAD_COUNT 0x00004014
73 #define VM_ENTRY_INT_INFO_FIELD 0x00004016
74 #define VM_ENTRY_EXCEPTION_ERROR 0x00004018
75 #define VM_ENTRY_INSTR_LENGTH 0x0000401A
76 // Only with "Use TPR Shadow" Enabled
77 #define TPR_THRESHOLD 0x0000401C
81 /* 32 bit Read Only data fields */
82 #define VM_INSTR_ERROR 0x00004400
83 #define EXIT_REASON 0x00004402
84 #define VM_EXIT_INT_INFO 0x00004404
85 #define VM_EXIT_INT_ERROR 0x00004406
86 #define IDT_VECTOR_INFO 0x00004408
87 #define IDT_VECTOR_ERROR 0x0000440A
88 #define VM_EXIT_INSTR_LENGTH 0x0000440C
89 #define VMX_INSTR_INFO 0x0000440E
91 /* 32 bit Guest state fields */
92 #define GUEST_ES_LIMIT 0x00004800
93 #define GUEST_CS_LIMIT 0x00004802
94 #define GUEST_SS_LIMIT 0x00004804
95 #define GUEST_DS_LIMIT 0x00004806
96 #define GUEST_FS_LIMIT 0x00004808
97 #define GUEST_GS_LIMIT 0x0000480A
98 #define GUEST_LDTR_LIMIT 0x0000480C
99 #define GUEST_TR_LIMIT 0x0000480E
100 #define GUEST_GDTR_LIMIT 0x00004810
101 #define GUEST_IDTR_LIMIT 0x00004812
102 #define GUEST_ES_ACCESS 0x00004814
103 #define GUEST_CS_ACCESS 0x00004816
104 #define GUEST_SS_ACCESS 0x00004818
105 #define GUEST_DS_ACCESS 0x0000481A
106 #define GUEST_FS_ACCESS 0x0000481C
107 #define GUEST_GS_ACCESS 0x0000481E
108 #define GUEST_LDTR_ACCESS 0x00004820
109 #define GUEST_TR_ACCESS 0x00004822
110 #define GUEST_INT_STATE 0x00004824
111 #define GUEST_ACTIVITY_STATE 0x00004826
112 #define GUEST_SMBASE 0x00004828
113 #define GUEST_IA32_SYSENTER_CS 0x0000482A
116 /* 32 bit host state field */
117 #define HOST_IA32_SYSENTER_CS 0x00004C00
119 /* Natural Width Control Fields */
120 #define CR0_GUEST_HOST_MASK 0x00006000
121 #define CR4_GUEST_HOST_MASK 0x00006002
122 #define CR0_READ_SHADOW 0x00006004
123 #define CR4_READ_SHADOW 0x00006006
124 #define CR3_TARGET_VALUE_0 0x00006008
125 #define CR3_TARGET_VALUE_1 0x0000600A
126 #define CR3_TARGET_VALUE_2 0x0000600C
127 #define CR3_TARGET_VALUE_3 0x0000600E
130 /* Natural Width Read Only Fields */
131 #define EXIT_QUALIFICATION 0x00006400
132 #define IO_RCX 0x00006402
133 #define IO_RSI 0x00006404
134 #define IO_RDI 0x00006406
135 #define IO_RIP 0x00006408
136 #define GUEST_LINEAR_ADDR 0x0000640A
138 /* Natural Width Guest State Fields */
139 #define GUEST_CR0 0x00006800
140 #define GUEST_CR3 0x00006802
141 #define GUEST_CR4 0x00006804
142 #define GUEST_ES_BASE 0x00006806
143 #define GUEST_CS_BASE 0x00006808
144 #define GUEST_SS_BASE 0x0000680A
145 #define GUEST_DS_BASE 0x0000680C
146 #define GUEST_FS_BASE 0x0000680E
147 #define GUEST_GS_BASE 0x00006810
148 #define GUEST_LDTR_BASE 0x00006812
149 #define GUEST_TR_BASE 0x00006814
150 #define GUEST_GDTR_BASE 0x00006816
151 #define GUEST_IDTR_BASE 0x00006818
152 #define GUEST_DR7 0x0000681A
153 #define GUEST_RSP 0x0000681C
154 #define GUEST_RIP 0x0000681E
155 #define GUEST_RFLAGS 0x00006820
156 #define GUEST_PENDING_DEBUG_EXCS 0x00006822
157 #define GUEST_IA32_SYSENTER_ESP 0x00006824
158 #define GUEST_IA32_SYSENTER_EIP 0x00006826
161 /* Natural Width Host State Fields */
162 #define HOST_CR0 0x00006C00
163 #define HOST_CR3 0x00006C02
164 #define HOST_CR4 0x00006C04
165 #define HOST_FS_BASE 0x00006C06
166 #define HOST_GS_BASE 0x00006C08
167 #define HOST_TR_BASE 0x00006C0A
168 #define HOST_GDTR_BASE 0x00006C0C
169 #define HOST_IDTR_BASE 0x00006C0E
170 #define HOST_IA32_SYSENTER_ESP 0x00006C10
171 #define HOST_IA32_SYSENTER_EIP 0x00006C12
172 #define HOST_RSP 0x00006C14
173 #define HOST_RIP 0x00006C16
175 /* Pin Based VM Execution Controls */
176 /* INTEL MANUAL: 20-10 vol 3B */
177 #define EXTERNAL_INTERRUPT_EXITING 0x00000001
178 #define NMI_EXITING 0x00000008
179 #define VIRTUAL_NMIS 0x00000020
182 /* Processor Based VM Execution Controls */
183 /* INTEL MANUAL: 20-11 vol. 3B */
184 #define INTERRUPT_WINDOWS_EXIT 0x00000004
185 #define USE_TSC_OFFSETTING 0x00000008
186 #define HLT_EXITING 0x00000080
187 #define INVLPG_EXITING 0x00000200
188 #define MWAIT_EXITING 0x00000400
189 #define RDPMC_EXITING 0x00000800
190 #define RDTSC_EXITING 0x00001000
191 #define CR8_LOAD_EXITING 0x00080000
192 #define CR8_STORE_EXITING 0x00100000
193 #define USE_TPR_SHADOW 0x00200000
194 #define NMI_WINDOW_EXITING 0x00400000
195 #define MOVDR_EXITING 0x00800000
196 #define UNCONDITION_IO_EXITING 0x01000000
197 #define USE_IO_BITMAPS 0x02000000
198 #define USE_MSR_BITMAPS 0x10000000
199 #define MONITOR_EXITING 0x20000000
200 #define PAUSE_EXITING 0x40000000
202 /* VM-Exit Controls */
203 /* INTEL MANUAL: 20-16 vol. 3B */
204 #define HOST_ADDR_SPACE_SIZE 0x00000200
205 #define ACK_IRQ_ON_EXIT 0x00008000
208 #define VM_EXIT_REASON_INFO_EXCEPTION_OR_NMI 0
209 #define VM_EXIT_REASON_EXTERNAL_INTR 1
210 #define VM_EXIT_REASON_TRIPLE_FAULT 2
211 #define VM_EXIT_REASON_INIT_SIGNAL 3
212 #define VM_EXIT_REASON_STARTUP_IPI 4
213 #define VM_EXIT_REASON_IO_SMI 5
214 #define VM_EXIT_REASON_OTHER_SMI 6
215 #define VM_EXIT_REASON_INTR_WINDOW 7
216 #define VM_EXIT_REASON_NMI_WINDOW 8
217 #define VM_EXIT_REASON_TASK_SWITCH 9
218 #define VM_EXIT_REASON_CPUID 10
219 #define VM_EXIT_REASON_HLT 12
220 #define VM_EXIT_REASON_INVD 13
221 #define VM_EXIT_REASON_INVLPG 14
222 #define VM_EXIT_REASON_RDPMC 15
223 #define VM_EXIT_REASON_RDTSC 16
224 #define VM_EXIT_REASON_RSM 17
225 #define VM_EXIT_REASON_VMCALL 18
226 #define VM_EXIT_REASON_VMCLEAR 19
227 #define VM_EXIT_REASON_VMLAUNCH 20
228 #define VM_EXIT_REASON_VMPTRLD 21
229 #define VM_EXIT_REASON_VMPTRST 22
230 #define VM_EXIT_REASON_VMREAD 23
231 #define VM_EXIT_REASON_VMRESUME 24
232 #define VM_EXIT_REASON_VMWRITE 25
233 #define VM_EXIT_REASON_VMXOFF 26
234 #define VM_EXIT_REASON_VMXON 27
235 #define VM_EXIT_REASON_CR_REG_ACCESSES 28
236 #define VM_EXIT_REASON_MOV_DR 29
237 #define VM_EXIT_REASON_IO_INSTR 30
238 #define VM_EXIT_REASON_RDMSR 31
239 #define VM_EXIT_REASON_WRMSR 32
240 #define VM_EXIT_REASON_ENTRY_FAIL_INVALID_GUEST_STATE 33
241 #define VM_EXIT_REASON_ENTRY_FAIL_MSR_LOAD 34
242 #define VM_EXIT_REASON_MWAIT 36
243 #define VM_EXIT_REASON_MONITOR 39
244 #define VM_EXIT_REASON_PAUSE 40
245 #define VM_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 41
246 #define VM_EXIT_REASON_TPR_BELOW_THRESHOLD 43
249 extern char *exception_names[];
250 extern char *exception_type_names[];
261 #define PACKED __attribute__((packed))
266 /* VMCS Exit QUALIFICATIONs */
267 struct VMExitIOQual {
268 uint_t accessSize : 3 PACKED; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes)
269 uint_t dir : 1 PACKED; // (0: Out ;; 1: In)
270 uint_t string : 1 PACKED; // (0: not string ;; 1: string)
271 uint_t REP : 1 PACKED; // (0: not REP ;; 1: REP)
272 uint_t opEnc : 1 PACKED; // (0: DX ;; 1: immediate)
273 uint_t rsvd : 9 PACKED; // Set to 0
274 uint_t port : 16 PACKED; // IO Port Number
279 struct VMExitDBGQual {
280 uint_t B0 : 1 PACKED; // Breakpoint 0 condition met
281 uint_t B1 : 1 PACKED; // Breakpoint 1 condition met
282 uint_t B2 : 1 PACKED; // Breakpoint 2 condition met
283 uint_t B3 : 1 PACKED; // Breakpoint 3 condition met
284 uint_t rsvd : 9 PACKED; // reserved to 0
285 uint_t BD : 1 PACKED; // detected DBG reg access
286 uint_t BS : 1 PACKED; // cause either single instr or taken branch
290 struct VMExitTSQual {
291 uint_t selector : 16 PACKED; // selector of destination TSS
292 uint_t rsvd : 14 PACKED; // reserved to 0
293 uint_t src : 2 PACKED; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT)
296 struct VMExitCRQual {
297 uint_t crID : 4 PACKED; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit)
298 uint_t accessType : 2 PACKED; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW)
299 uint_t lmswOpType : 1 PACKED; // (0: register ; 1: memory)
300 uint_t rsvd1 : 1 PACKED; // reserved to 0
301 uint_t gpr : 4 PACKED; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
302 uint_t rsvd2 : 4 PACKED; // reserved to 0
303 uint_t lmswSrc : 16 PACKED; // src data for lmsw
306 struct VMExitMovDRQual {
307 uint_t regID : 3 PACKED; // debug register number
308 uint_t rsvd1 : 1 PACKED; // reserved to 0
309 uint_t dir : 1 PACKED; // (0: MOV to DR , 1: MOV from DR)
310 uint_t rsvd2 : 3 PACKED; // reserved to 0
311 uint_t gpr : 4 PACKED; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
314 /* End Exit Qualifications */
316 /* Exit Vector Info */
317 struct VMExitIntInfo {
318 uint_t nr : 8 PACKED; // IRQ number, exception vector, NMI = 2
319 uint_t type : 3 PACKED; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
320 uint_t errorCode : 1 PACKED; // 1: error Code present
321 uint_t iret : 1 PACKED; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
322 uint_t rsvd : 18 PACKED; // always 0
323 uint_t valid : 1 PACKED; // always 1 if valid
329 /* End Exit Vector Info */
334 /* Segment Selector Access Rights (32 bits) */
335 /* INTEL Manual: 20-4 vol 3B */
339 uint_t descType : 1 PACKED;
340 uint_t dpl : 2 PACKED;
341 uint_t present : 1 PACKED;
342 uchar_t rsvd1 PACKED;
343 uint_t avail : 1 PACKED ;
344 uint_t L : 1 PACKED ; // CS only (64 bit active), reserved otherwise
345 uint_t DB : 1 PACKED ;
346 uint_t granularity : 1 PACKED ;
347 uint_t unusable : 1 PACKED ;
348 uint_t rsvd2 : 15 PACKED ;
356 union SegAccess access;
358 uint_t baseAddr ; // should be 64 bits?
363 struct VMCSGuestStateArea {
364 /* (1) Guest State Area */
365 /* (1.1) Guest Register State */
366 uint_t cr0 ; // should be 64 bits?
367 uint_t cr3 ; // should be 64 bits?
368 uint_t cr4 ; // should be 64 bits?
369 uint_t dr7 ; // should be 64 bits?
370 uint_t rsp ; // should be 64 bits?
371 uint_t rip ; // should be 64 bits?
372 uint_t rflags ; // should be 64 bits?
375 struct VMCSSegment cs ;
376 struct VMCSSegment ss ;
377 struct VMCSSegment ds ;
378 struct VMCSSegment es ;
379 struct VMCSSegment fs ;
380 struct VMCSSegment gs ;
381 struct VMCSSegment ldtr ;
382 struct VMCSSegment tr ;
384 struct VMCSSegment gdtr ;
385 struct VMCSSegment idtr ;
390 ullong_t sysenter_esp ; // should be 64 bits?
391 ullong_t sysenter_eip ; // should be 64 bits?
395 /* (1.2) Guest Non-register State */
396 uint_t activity ; /* (0=Active, 1=HLT, 2=Shutdown, 3=Wait-for-SIPI)
397 (listed in MSR: IA32_VMX_MISC) */
399 uint_t interrupt_state ; // see Table 20-3 (page 20-6) INTEL MANUAL 3B
401 ullong_t pending_dbg_exceptions ; // should be 64 bits?
402 /* Table 20-4 page 20-8 INTEL MANUAL 3B */
404 ullong_t vmcs_link ; // should be set to 0xffffffff_ffffffff
408 int CopyOutVMCSGuestStateArea(struct VMCSGuestStateArea *p);
409 int CopyInVMCSGuestStateArea(struct VMCSGuestStateArea *p);
413 struct VMCSHostStateArea {
414 /* (2) Host State Area */
415 ullong_t cr0 ; // Should be 64 bits?
416 ullong_t cr3 ; // should be 64 bits?
417 ullong_t cr4 ; // should be 64 bits?
418 ullong_t rsp ; // should be 64 bits?
419 ullong_t rip ; // should be 64 bits?
421 ushort_t csSelector ;
422 ushort_t ssSelector ;
423 ushort_t dsSelector ;
424 ushort_t esSelector ;
425 ushort_t fsSelector ;
426 ushort_t gsSelector ;
427 ushort_t trSelector ;
429 ullong_t fsBaseAddr ; // Should be 64 bits?
430 ullong_t gsBaseAddr ; // Should be 64 bits?
431 ullong_t trBaseAddr ; // Should be 64 bits?
432 ullong_t gdtrBaseAddr ; // Should be 64 bits?
433 ullong_t idtrBaseAddr ; // Should be 64 bits?
438 ullong_t sysenter_esp ; // Should be 64 bits?
439 ullong_t sysenter_eip ; // Should be 64 bits?
443 int CopyOutVMCSHostStateArea(struct VMCSHostStateArea *p);
444 int CopyInVMCSHostStateArea(struct VMCSHostStateArea *p);
447 struct VMCSExecCtrlFields {
448 uint_t pinCtrls ; // Table 20-5, Vol 3B. (pg. 20-10)
449 uint_t procCtrls ; // Table 20-6, Vol 3B. (pg. 20-11)
451 uint_t pageFaultErrorMask ;
452 uint_t pageFaultErrorMatch ;
456 uint_t cr0GuestHostMask ; // Should be 64 bits?
457 uint_t cr0ReadShadow ; // Should be 64 bits?
458 uint_t cr4GuestHostMask ; // Should be 64 bits?
459 uint_t cr4ReadShadow ; // Should be 64 bits?
460 uint_t cr3TargetValue0 ; // should be 64 bits?
461 uint_t cr3TargetValue1 ; // should be 64 bits?
462 uint_t cr3TargetValue2 ; // should be 64 bits?
463 uint_t cr3TargetValue3 ; // should be 64 bits?
464 uint_t cr3TargetCount ;
468 /* these fields enabled if "use TPR shadow"==1 */
469 /* may not need them */
470 ullong_t virtApicPageAddr ;
471 // uint_t virtApicPageAddrHigh
472 uint_t tprThreshold ;
475 ullong_t MSRBitmapsBaseAddr;
478 ullong_t vmcsExecPtr ;
482 int CopyOutVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
483 int CopyInVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
488 struct VMCSExitCtrlFields {
489 uint_t exitCtrls ; // Table 20-7, Vol. 3B (pg. 20-16)
490 uint_t msrStoreCount ;
491 ullong_t msrStoreAddr ;
492 uint_t msrLoadCount ;
493 ullong_t msrLoadAddr ;
496 int CopyOutVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
497 int CopyInVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
501 struct VMCSEntryCtrlFields {
502 uint_t entryCtrls ; // Table 20-9, Vol. 3B (pg. 20-18)
503 uint_t msrLoadCount ;
504 ullong_t msrLoadAddr ;
505 uint_t intInfo ; // Table 20-10, Vol. 3B (pg. 20-19)
506 uint_t exceptionErrorCode ;
511 int CopyOutVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
512 int CopyInVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
515 struct VMCSExitInfoFields {
516 uint_t reason; // Table 20-11, Vol. 3B (pg. 20-20)
517 uint_t qualification ; // Should be 64 bits?
519 uint_t intErrorCode ;
520 uint_t idtVectorInfo ;
521 uint_t idtVectorErrorCode ;
523 ullong_t guestLinearAddr ; // Should be 64 bits?
525 ullong_t ioRCX ; // Should be 64 bits?
526 ullong_t ioRSI ; // Should be 64 bits?
527 ullong_t ioRDI ; // Should be 64 bits?
528 ullong_t ioRIP ; // Should be 64 bits?
529 uint_t instrErrorField ;
534 int CopyOutVMCSExitInfoFields(struct VMCSExitInfoFields *p);
541 uint_t exitCtrlFlags;
542 struct VMCSGuestStateArea guestStateArea ;
543 struct VMCSHostStateArea hostStateArea ;
544 struct VMCSExecCtrlFields execCtrlFields ;
545 struct VMCSExitCtrlFields exitCtrlFields ;
546 struct VMCSEntryCtrlFields entryCtrlFields ;
547 struct VMCSExitInfoFields exitInfoFields ;
551 int CopyOutVMCSData(struct VMCSData *p);
552 int CopyInVMCSData(struct VMCSData *p);
565 void PrintTrace_VMX_Regs(struct VMXRegs *regs);
566 void PrintTrace_VMCSData(struct VMCSData * vmcs);
567 void PrintTrace_VMCSGuestStateArea(struct VMCSGuestStateArea * guestState);
568 void PrintTrace_VMCSHostStateArea(struct VMCSHostStateArea * hostState);
569 void PrintTrace_VMCSExecCtrlFields(struct VMCSExecCtrlFields * execCtrls);
570 void PrintTrace_VMCSExitCtrlFields(struct VMCSExitCtrlFields * exitCtrls);
571 void PrintTrace_VMCSEntryCtrlFields(struct VMCSEntryCtrlFields * entryCtrls);
572 void PrintTrace_VMCSExitInfoFields(struct VMCSExitInfoFields * exitInfo);
573 void PrintTrace_VMCSSegment(char * segname, struct VMCSSegment * seg, int abbr);
576 extern uint_t VMCS_WRITE();
577 extern uint_t VMCS_READ();
579 //uint_t VMCSRead(uint_t tag, void * val);
582 #include <palacios/vmcs_gen.h>