3 * This file is part of the Palacios Virtual Machine Monitor developed
4 * by the V3VEE Project with funding from the United States National
5 * Science Foundation and the Department of Energy.
7 * The V3VEE Project is a joint project between Northwestern University
8 * and the University of New Mexico. You can find out more at
11 * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
12 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
13 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Peter Dinda <pdinda@northwestern.edu>
17 * Jack Lange <jarusl@cs.northwestern.edu>
19 * This is free software. You are permitted to use,
20 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
30 #include <palacios/vmm_types.h>
33 /* 16 bit guest state */
34 #define VMCS_GUEST_ES_SELECTOR 0x00000800
35 #define VMCS_GUEST_CS_SELECTOR 0x00000802
36 #define VMCS_GUEST_SS_SELECTOR 0x00000804
37 #define VMCS_GUEST_DS_SELECTOR 0x00000806
38 #define VMCS_GUEST_FS_SELECTOR 0x00000808
39 #define VMCS_GUEST_GS_SELECTOR 0x0000080A
40 #define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
41 #define VMCS_GUEST_TR_SELECTOR 0x0000080E
43 /* 16 bit host state */
44 #define VMCS_HOST_ES_SELECTOR 0x00000C00
45 #define VMCS_HOST_CS_SELECTOR 0x00000C02
46 #define VMCS_HOST_SS_SELECTOR 0x00000C04
47 #define VMCS_HOST_DS_SELECTOR 0x00000C06
48 #define VMCS_HOST_FS_SELECTOR 0x00000C08
49 #define VMCS_HOST_GS_SELECTOR 0x00000C0A
50 #define VMCS_HOST_TR_SELECTOR 0x00000C0C
52 /* 64 bit control fields */
53 #define IO_BITMAP_A_ADDR 0x00002000
54 #define IO_BITMAP_A_ADDR_HIGH 0x00002001
55 #define IO_BITMAP_B_ADDR 0x00002002
56 #define IO_BITMAP_B_ADDR_HIGH 0x00002003
57 // Only with "Use MSR Bitmaps" enabled
58 #define MSR_BITMAPS 0x00002004
59 #define MSR_BITMAPS_HIGH 0x00002005
61 #define VM_EXIT_MSR_STORE_ADDR 0x00002006
62 #define VM_EXIT_MSR_STORE_ADDR_HIGH 0x00002007
63 #define VM_EXIT_MSR_LOAD_ADDR 0x00002008
64 #define VM_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009
65 #define VM_ENTRY_MSR_LOAD_ADDR 0x0000200A
66 #define VM_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200B
67 #define VMCS_EXEC_PTR 0x0000200C
68 #define VMCS_EXEC_PTR_HIGH 0x0000200D
69 #define TSC_OFFSET 0x00002010
70 #define TSC_OFFSET_HIGH 0x00002011
71 // Only with "Use TPR Shadow" enabled
72 #define VIRT_APIC_PAGE_ADDR 0x00002012
73 #define VIRT_APIC_PAGE_ADDR_HIGH 0x00002013
77 /* 64 bit guest state fields */
78 #define VMCS_LINK_PTR 0x00002800
79 #define VMCS_LINK_PTR_HIGH 0x00002801
80 #define GUEST_IA32_DEBUGCTL 0x00002802
81 #define GUEST_IA32_DEBUGCTL_HIGH 0x00002803
84 /* 32 bit control fields */
85 #define PIN_VM_EXEC_CTRLS 0x00004000
86 #define PROC_VM_EXEC_CTRLS 0x00004002
87 #define EXCEPTION_BITMAP 0x00004004
88 #define PAGE_FAULT_ERROR_MASK 0x00004006
89 #define PAGE_FAULT_ERROR_MATCH 0x00004008
90 #define CR3_TARGET_COUNT 0x0000400A
91 #define VM_EXIT_CTRLS 0x0000400C
92 #define VM_EXIT_MSR_STORE_COUNT 0x0000400E
93 #define VM_EXIT_MSR_LOAD_COUNT 0x00004010
94 #define VM_ENTRY_CTRLS 0x00004012
95 #define VM_ENTRY_MSR_LOAD_COUNT 0x00004014
96 #define VM_ENTRY_INT_INFO_FIELD 0x00004016
97 #define VM_ENTRY_EXCEPTION_ERROR 0x00004018
98 #define VM_ENTRY_INSTR_LENGTH 0x0000401A
99 // Only with "Use TPR Shadow" Enabled
100 #define TPR_THRESHOLD 0x0000401C
104 /* 32 bit Read Only data fields */
105 #define VM_INSTR_ERROR 0x00004400
106 #define EXIT_REASON 0x00004402
107 #define VM_EXIT_INT_INFO 0x00004404
108 #define VM_EXIT_INT_ERROR 0x00004406
109 #define IDT_VECTOR_INFO 0x00004408
110 #define IDT_VECTOR_ERROR 0x0000440A
111 #define VM_EXIT_INSTR_LENGTH 0x0000440C
112 #define VMX_INSTR_INFO 0x0000440E
114 /* 32 bit Guest state fields */
115 #define GUEST_ES_LIMIT 0x00004800
116 #define GUEST_CS_LIMIT 0x00004802
117 #define GUEST_SS_LIMIT 0x00004804
118 #define GUEST_DS_LIMIT 0x00004806
119 #define GUEST_FS_LIMIT 0x00004808
120 #define GUEST_GS_LIMIT 0x0000480A
121 #define GUEST_LDTR_LIMIT 0x0000480C
122 #define GUEST_TR_LIMIT 0x0000480E
123 #define GUEST_GDTR_LIMIT 0x00004810
124 #define GUEST_IDTR_LIMIT 0x00004812
125 #define GUEST_ES_ACCESS 0x00004814
126 #define GUEST_CS_ACCESS 0x00004816
127 #define GUEST_SS_ACCESS 0x00004818
128 #define GUEST_DS_ACCESS 0x0000481A
129 #define GUEST_FS_ACCESS 0x0000481C
130 #define GUEST_GS_ACCESS 0x0000481E
131 #define GUEST_LDTR_ACCESS 0x00004820
132 #define GUEST_TR_ACCESS 0x00004822
133 #define GUEST_INT_STATE 0x00004824
134 #define GUEST_ACTIVITY_STATE 0x00004826
135 #define GUEST_SMBASE 0x00004828
136 #define GUEST_IA32_SYSENTER_CS 0x0000482A
139 /* 32 bit host state field */
140 #define HOST_IA32_SYSENTER_CS 0x00004C00
142 /* Natural Width Control Fields */
143 #define CR0_GUEST_HOST_MASK 0x00006000
144 #define CR4_GUEST_HOST_MASK 0x00006002
145 #define CR0_READ_SHADOW 0x00006004
146 #define CR4_READ_SHADOW 0x00006006
147 #define CR3_TARGET_VALUE_0 0x00006008
148 #define CR3_TARGET_VALUE_1 0x0000600A
149 #define CR3_TARGET_VALUE_2 0x0000600C
150 #define CR3_TARGET_VALUE_3 0x0000600E
153 /* Natural Width Read Only Fields */
154 #define EXIT_QUALIFICATION 0x00006400
155 #define IO_RCX 0x00006402
156 #define IO_RSI 0x00006404
157 #define IO_RDI 0x00006406
158 #define IO_RIP 0x00006408
159 #define GUEST_LINEAR_ADDR 0x0000640A
161 /* Natural Width Guest State Fields */
162 #define GUEST_CR0 0x00006800
163 #define GUEST_CR3 0x00006802
164 #define GUEST_CR4 0x00006804
165 #define GUEST_ES_BASE 0x00006806
166 #define GUEST_CS_BASE 0x00006808
167 #define GUEST_SS_BASE 0x0000680A
168 #define GUEST_DS_BASE 0x0000680C
169 #define GUEST_FS_BASE 0x0000680E
170 #define GUEST_GS_BASE 0x00006810
171 #define GUEST_LDTR_BASE 0x00006812
172 #define GUEST_TR_BASE 0x00006814
173 #define GUEST_GDTR_BASE 0x00006816
174 #define GUEST_IDTR_BASE 0x00006818
175 #define GUEST_DR7 0x0000681A
176 #define GUEST_RSP 0x0000681C
177 #define GUEST_RIP 0x0000681E
178 #define GUEST_RFLAGS 0x00006820
179 #define GUEST_PENDING_DEBUG_EXCS 0x00006822
180 #define GUEST_IA32_SYSENTER_ESP 0x00006824
181 #define GUEST_IA32_SYSENTER_EIP 0x00006826
184 /* Natural Width Host State Fields */
185 #define HOST_CR0 0x00006C00
186 #define HOST_CR3 0x00006C02
187 #define HOST_CR4 0x00006C04
188 #define HOST_FS_BASE 0x00006C06
189 #define HOST_GS_BASE 0x00006C08
190 #define HOST_TR_BASE 0x00006C0A
191 #define HOST_GDTR_BASE 0x00006C0C
192 #define HOST_IDTR_BASE 0x00006C0E
193 #define HOST_IA32_SYSENTER_ESP 0x00006C10
194 #define HOST_IA32_SYSENTER_EIP 0x00006C12
195 #define HOST_RSP 0x00006C14
196 #define HOST_RIP 0x00006C16
198 /* Pin Based VM Execution Controls */
199 /* INTEL MANUAL: 20-10 vol 3B */
200 #define EXTERNAL_INTERRUPT_EXITING 0x00000001
201 #define NMI_EXITING 0x00000008
202 #define VIRTUAL_NMIS 0x00000020
205 /* Processor Based VM Execution Controls */
206 /* INTEL MANUAL: 20-11 vol. 3B */
207 #define INTERRUPT_WINDOWS_EXIT 0x00000004
208 #define USE_TSC_OFFSETTING 0x00000008
209 #define HLT_EXITING 0x00000080
210 #define INVLPG_EXITING 0x00000200
211 #define MWAIT_EXITING 0x00000400
212 #define RDPMC_EXITING 0x00000800
213 #define RDTSC_EXITING 0x00001000
214 #define CR8_LOAD_EXITING 0x00080000
215 #define CR8_STORE_EXITING 0x00100000
216 #define USE_TPR_SHADOW 0x00200000
217 #define NMI_WINDOW_EXITING 0x00400000
218 #define MOVDR_EXITING 0x00800000
219 #define UNCONDITION_IO_EXITING 0x01000000
220 #define USE_IO_BITMAPS 0x02000000
221 #define USE_MSR_BITMAPS 0x10000000
222 #define MONITOR_EXITING 0x20000000
223 #define PAUSE_EXITING 0x40000000
225 /* VM-Exit Controls */
226 /* INTEL MANUAL: 20-16 vol. 3B */
227 #define HOST_ADDR_SPACE_SIZE 0x00000200
228 #define ACK_IRQ_ON_EXIT 0x00008000
239 /* VMCS Exit QUALIFICATIONs */
240 struct VMExitIOQual {
241 uint32_t accessSize : 3; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes)
242 uint32_t dir : 1; // (0: Out ;; 1: In)
243 uint32_t string : 1; // (0: not string ;; 1: string)
244 uint32_t REP : 1; // (0: not REP ;; 1: REP)
245 uint32_t opEnc : 1; // (0: DX ;; 1: immediate)
246 uint32_t rsvd : 9; // Set to 0
247 uint32_t port : 16; // IO Port Number
248 } __attribute__((packed));
252 struct VMExitDBGQual {
253 uint32_t B0 : 1; // Breakpoint 0 condition met
254 uint32_t B1 : 1; // Breakpoint 1 condition met
255 uint32_t B2 : 1; // Breakpoint 2 condition met
256 uint32_t B3 : 1; // Breakpoint 3 condition met
257 uint32_t rsvd : 9; // reserved to 0
258 uint32_t BD : 1; // detected DBG reg access
259 uint32_t BS : 1; // cause either single instr or taken branch
260 } __attribute__((packed));
263 struct VMExitTSQual {
264 uint32_t selector : 16; // selector of destination TSS
265 uint32_t rsvd : 14; // reserved to 0
266 uint32_t src : 2; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT)
267 } __attribute__((packed));
269 struct VMExitCRQual {
270 uint32_t crID : 4; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit)
271 uint32_t accessType : 2; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW)
272 uint32_t lmswOpType : 1; // (0: register ; 1: memory)
273 uint32_t rsvd1 : 1; // reserved to 0
274 uint32_t gpr : 4; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
275 uint32_t rsvd2 : 4; // reserved to 0
276 uint32_t lmswSrc : 16; // src data for lmsw
277 } __attribute__((packed));
279 struct VMExitMovDRQual {
280 uint32_t regID : 3; // debug register number
281 uint32_t rsvd1 : 1; // reserved to 0
282 uint32_t dir : 1; // (0: MOV to DR , 1: MOV from DR)
283 uint32_t rsvd2 : 3; // reserved to 0
284 uint32_t gpr : 4; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
285 } __attribute__((packed));
287 /* End Exit Qualifications */
289 /* Exit Vector Info */
290 struct VMExitIntInfo {
291 uint32_t nr : 8; // IRQ number, exception vector, NMI = 2
292 uint32_t type : 3; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
293 uint32_t errorCode : 1; // 1: error Code present
294 uint32_t iret : 1; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
295 uint32_t rsvd : 18; // always 0
296 uint32_t valid : 1; // always 1 if valid
297 } __attribute__((packed));
302 /* End Exit Vector Info */
307 /* Segment Selector Access Rights (32 bits) */
308 /* INTEL Manual: 20-4 vol 3B */
311 struct vmcs_segment {
321 uint32_t desc_type : 1;
323 uint32_t present : 1;
326 uint32_t long_mode : 1; // CS only (64 bit active), reserved otherwise
328 uint32_t granularity : 1;
329 uint32_t unusable : 1;
331 } __attribute__((packed));
332 } __attribute__((packed));
333 } __attribute__((packed)) access;
338 struct VMCSGuestStateArea {
339 /* (1) Guest State Area */
340 /* (1.1) Guest Register State */
341 uint32_t cr0 ; // should be 64 bits?
342 uint32_t cr3 ; // should be 64 bits?
343 uint32_t cr4 ; // should be 64 bits?
344 uint32_t dr7 ; // should be 64 bits?
345 uint32_t rsp ; // should be 64 bits?
346 uint32_t rip ; // should be 64 bits?
347 uint32_t rflags ; // should be 64 bits?
350 struct VMCSSegment cs ;
351 struct VMCSSegment ss ;
352 struct VMCSSegment ds ;
353 struct VMCSSegment es ;
354 struct VMCSSegment fs ;
355 struct VMCSSegment gs ;
356 struct VMCSSegment ldtr ;
357 struct VMCSSegment tr ;
359 struct VMCSSegment gdtr ;
360 struct VMCSSegment idtr ;
364 uint32_t sysenter_cs ;
365 uint64_t sysenter_esp ; // should be 64 bits?
366 uint64_t sysenter_eip ; // should be 64 bits?
370 /* (1.2) Guest Non-register State */
371 uint32_t activity ; /* (0=Active, 1=HLT, 2=Shutdown, 3=Wait-for-SIPI)
372 (listed in MSR: IA32_VMX_MISC) */
374 uint32_t interrupt_state ; // see Table 20-3 (page 20-6) INTEL MANUAL 3B
376 uint64_t pending_dbg_exceptions ; // should be 64 bits?
377 /* Table 20-4 page 20-8 INTEL MANUAL 3B */
379 uint64_t vmcs_link ; // should be set to 0xffffffff_ffffffff
383 int CopyOutVMCSGuestStateArea(struct VMCSGuestStateArea * p);
384 int CopyInVMCSGuestStateArea(struct VMCSGuestStateArea * p);
388 struct VMCSHostStateArea {
389 /* (2) Host State Area */
407 addr_t gdtrBaseAddr ;
408 addr_t idtrBaseAddr ;
412 uint32_t sysenter_cs ;
413 addr_t sysenter_esp ;
414 addr_t sysenter_eip ;
418 int CopyOutVMCSHostStateArea(struct VMCSHostStateArea *p);
419 int CopyInVMCSHostStateArea(struct VMCSHostStateArea *p);
422 struct VMCSExecCtrlFields {
423 uint32_t pinCtrls ; // Table 20-5, Vol 3B. (pg. 20-10)
424 uint32_t procCtrls ; // Table 20-6, Vol 3B. (pg. 20-11)
425 uint32_t execBitmap ;
426 uint32_t pageFaultErrorMask ;
427 uint32_t pageFaultErrorMatch ;
431 uint32_t cr0GuestHostMask ; // Should be 64 bits?
432 uint32_t cr0ReadShadow ; // Should be 64 bits?
433 uint32_t cr4GuestHostMask ; // Should be 64 bits?
434 uint32_t cr4ReadShadow ; // Should be 64 bits?
435 uint32_t cr3TargetValue0 ; // should be 64 bits?
436 uint32_t cr3TargetValue1 ; // should be 64 bits?
437 uint32_t cr3TargetValue2 ; // should be 64 bits?
438 uint32_t cr3TargetValue3 ; // should be 64 bits?
439 uint32_t cr3TargetCount ;
443 /* these fields enabled if "use TPR shadow"==1 */
444 /* may not need them */
445 uint64_t virtApicPageAddr ;
446 // uint32_t virtApicPageAddrHigh
447 uint32_t tprThreshold ;
450 uint64_t MSRBitmapsBaseAddr;
452 uint64_t vmcsExecPtr ;
455 int CopyOutVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
456 int CopyInVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
461 struct VMCSExitCtrlFields {
462 uint32_t exitCtrls ; // Table 20-7, Vol. 3B (pg. 20-16)
463 uint32_t msrStoreCount ;
464 uint64_t msrStoreAddr ;
465 uint32_t msrLoadCount ;
466 uint64_t msrLoadAddr ;
469 int CopyOutVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
470 int CopyInVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
474 struct VMCSEntryCtrlFields {
475 uint32_t entryCtrls ; // Table 20-9, Vol. 3B (pg. 20-18)
476 uint32_t msrLoadCount ;
477 uint64_t msrLoadAddr ;
478 uint32_t intInfo ; // Table 20-10, Vol. 3B (pg. 20-19)
479 uint32_t exceptionErrorCode ;
480 uint32_t instrLength ;
484 int CopyOutVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
485 int CopyInVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
488 struct VMCSExitInfoFields {
489 uint32_t reason; // Table 20-11, Vol. 3B (pg. 20-20)
490 uint32_t qualification ; // Should be 64 bits?
492 uint32_t intErrorCode ;
493 uint32_t idtVectorInfo ;
494 uint32_t idtVectorErrorCode ;
495 uint32_t instrLength ;
496 uint64_t guestLinearAddr ; // Should be 64 bits?
498 uint64_t ioRCX ; // Should be 64 bits?
499 uint64_t ioRSI ; // Should be 64 bits?
500 uint64_t ioRDI ; // Should be 64 bits?
501 uint64_t ioRIP ; // Should be 64 bits?
502 uint32_t instrErrorField ;
507 int CopyOutVMCSExitInfoFields(struct VMCSExitInfoFields *p);
514 uint32_t exitCtrlFlags;
515 struct VMCSGuestStateArea guestStateArea ;
516 struct VMCSHostStateArea hostStateArea ;
517 struct VMCSExecCtrlFields execCtrlFields ;
518 struct VMCSExitCtrlFields exitCtrlFields ;
519 struct VMCSEntryCtrlFields entryCtrlFields ;
520 struct VMCSExitInfoFields exitInfoFields ;
524 int CopyOutVMCSData(struct VMCSData *p);
525 int CopyInVMCSData(struct VMCSData *p);
538 void PrintTrace_VMX_Regs(struct VMXRegs *regs);
539 void PrintTrace_VMCSData(struct VMCSData * vmcs);
540 void PrintTrace_VMCSGuestStateArea(struct VMCSGuestStateArea * guestState);
541 void PrintTrace_VMCSHostStateArea(struct VMCSHostStateArea * hostState);
542 void PrintTrace_VMCSExecCtrlFields(struct VMCSExecCtrlFields * execCtrls);
543 void PrintTrace_VMCSExitCtrlFields(struct VMCSExitCtrlFields * exitCtrls);
544 void PrintTrace_VMCSEntryCtrlFields(struct VMCSEntryCtrlFields * entryCtrls);
545 void PrintTrace_VMCSExitInfoFields(struct VMCSExitInfoFields * exitInfo);
546 void PrintTrace_VMCSSegment(char * segname, struct VMCSSegment * seg, int abbr);
549 //uint_t VMCSRead(uint_t tag, void * val);
552 #endif // ! __V3VEE__