Palacios Public Git Repository

To checkout Palacios execute

  git clone http://v3vee.org/palacios/palacios.web/palacios.git
This will give you the master branch. You probably want the devel branch or one of the release branches. To switch to the devel branch, simply execute
  cd palacios
  git checkout --track -b devel origin/devel
The other branches are similar.


Corrected RTC timer bug (nvram)
[palacios.git] / palacios / include / palacios / svm.h
1 /* 
2  * This file is part of the Palacios Virtual Machine Monitor developed
3  * by the V3VEE Project with funding from the United States National 
4  * Science Foundation and the Department of Energy.  
5  *
6  * The V3VEE Project is a joint project between Northwestern University
7  * and the University of New Mexico.  You can find out more at 
8  * http://www.v3vee.org
9  *
10  * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> 
11  * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org> 
12  * All rights reserved.
13  *
14  * Author: Jack Lange <jarusl@cs.northwestern.edu>
15  *
16  * This is free software.  You are permitted to use,
17  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
18  */
19
20 #ifndef __SVM_H
21 #define __SVM_H
22
23
24
25
26 #ifdef __V3VEE__
27
28 #include <palacios/vmm.h>
29
30
31 #include <palacios/vmcb.h>
32 #include <palacios/vmm_util.h>
33
34 #define CPUID_EXT_FEATURE_IDS_ecx_svm_avail 0x00000004
35
36 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
37 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
38 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_np  0x00000001
39
40 #define EFER_MSR_svm_enable      0x00001000
41
42 /************/
43 /* SVM MSRs */
44 /************/
45 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
46 /************/
47
48 // SVM VM_CR MSR 
49 #define SVM_VM_CR_MSR             0xc0010114
50 #define SVM_VM_CR_MSR_dpd         0x00000001
51 #define SVM_VM_CR_MSR_r_init      0x00000002
52 #define SVM_VM_CR_MSR_dis_a20m    0x00000004
53 #define SVM_VM_CR_MSR_lock        0x00000008
54 #define SVM_VM_CR_MSR_svmdis      0x00000010
55
56 #define SVM_IGNNE_MSR             0xc0010115
57
58 // SMM Signal Control Register 
59 #define SVM_SMM_CTL_MSR           0xc0010116
60 #define SVM_SMM_CTL_MSR_dismiss   0x00000001
61 #define SVM_SMM_CTL_MSR_enter     0x00000002
62 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
63 #define SVM_SMM_CTL_MSR_exit      0x00000008
64 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
65
66 #define SVM_VM_HSAVE_PA_MSR      0xc0010117
67
68 #define SVM_KEY_MSR              0xc0010118
69
70 /******/
71
72
73
74
75 #define SVM_HANDLER_SUCCESS   0x0
76 #define SVM_HANDLER_ERROR     0x1
77 #define SVM_HANDLER_HALT      0x2
78
79 int v3_is_svm_capable();
80
81 void v3_init_svm_cpu(int cpu_id);
82 void v3_deinit_svm_cpu(int cpu_id);
83
84
85 int v3_init_svm_vmcb(struct guest_info * core, v3_vm_class_t vm_class);
86 int v3_deinit_svm_vmcb(struct guest_info * core);
87
88 int v3_svm_enter(struct guest_info * info);
89 int v3_start_svm_guest(struct guest_info *info);
90
91 #endif
92
93
94
95 #endif