4 #include <geekos/vmm.h>
6 #define CPUID_FEATURE_IDS 0x80000001
7 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
9 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
10 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
13 #define EFER_MSR 0xc0000080
14 #define EFER_MSR_svm_enable 0x00001000
19 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
23 #define SVM_VM_CR_MSR 0xc0010114
24 #define SVM_VM_CR_MSR_dpd 0x00000001
25 #define SVM_VM_CR_MSR_r_init 0x00000002
26 #define SVM_VM_CR_MSR_dis_a20m 0x00000004
27 #define SVM_VM_CR_MSR_lock 0x00000008
28 #define SVM_VM_CR_MSR_svmdis 0x00000010
30 #define SVM_IGNNE_MSR 0xc0010115
32 /* SMM Signal Control Register */
33 #define SVM_SMM_CTL_MSR 0xc0010116
34 #define SVM_SMM_CTL_MSR_dismiss 0x00000001
35 #define SVM_SMM_CTL_MSR_enter 0x00000002
36 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
37 #define SVM_SMM_CTL_MSR_exit 0x00000008
38 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
40 #define SVM_VM_HSAVE_PA_MSR 0xc0010117
41 #define SVM_KEY_MSR 0xc0010118