1 #ifndef __PALACIOS_PWRSTAT_H__
2 #define __PALACIOS_PWRSTAT_H__
4 /* THESE ARE INTEL SPECIFIC (Sandy Bridge and up) */
6 #define SANDY_BRIDGE_E3_MODEL_NO 0x2A
7 #define SANDY_BRIDGE_E5_MODEL_NO 0x2D
8 #define IVY_BRIDGE_MODEL_NO 0x3A
9 /* WARNING WARNING: this is speculation... */
10 #define HASWELL_MODEL_NO 0x4A
12 #ifdef MSR_RAPL_POWER_UNIT
13 // assume the rest are also defined by the kernel's msr include
14 // except for special ones here
17 // assume none are defined by the kernel's msr include
18 #define MSR_RAPL_POWER_UNIT 0x606
19 #define MSR_PKG_POWER_LIMIT 0x610
20 #define MSR_PKG_ENERGY_STATUS 0x611
21 #define MSR_PKG_PERF_STATUS 0x613
22 #define MSR_PKG_POWER_INFO 0x614
25 #define MSR_PP0_POWER_LIMIT 0x638
26 #define MSR_PP0_ENERGY_STATUS 0x639
27 #define MSR_PP0_POLICY 0x63A
28 #define MSR_PP0_PERF_STATUS 0x63B
30 /* PP1 RAPL Domain, may reflect to uncore devices */
31 #define MSR_PP1_POWER_LIMIT 0x640
32 #define MSR_PP1_ENERGY_STATUS 0x641
33 #define MSR_PP1_POLICY 0x642
35 /* DRAM RAPL Domain */
36 #define MSR_DRAM_POWER_LIMIT 0x618
37 #define MSR_DRAM_ENERGY_STATUS 0x619
38 #define MSR_DRAM_PERF_STATUS 0x61B
39 #define MSR_DRAM_POWER_INFO 0x61C
43 /* RAPL UNIT BITMASK */
44 #define POWER_UNIT_OFFSET 0
45 #define POWER_UNIT_MASK 0x0F
47 #define ENERGY_UNIT_OFFSET 0x08
48 #define ENERGY_UNIT_MASK 0x1F00
50 #define TIME_UNIT_OFFSET 0x10
51 #define TIME_UNIT_MASK 0xF0000