4 #include <lwk/kernel.h>
7 * Structure definitions for SMP machines following the
8 * Intel Multiprocessing Specification 1.1 and 1.4.
12 * This tag identifies where the SMP configuration
16 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
19 * A maximum of 255 APICs with the current APIC ID architecture.
23 struct intel_mp_floating
25 char mpf_signature[4]; /* "_MP_" */
26 unsigned int mpf_physptr; /* Configuration table address */
27 unsigned char mpf_length; /* Our length (paragraphs) */
28 unsigned char mpf_specification;/* Specification version */
29 unsigned char mpf_checksum; /* Checksum (makes sum 0) */
30 unsigned char mpf_feature1; /* Standard or configuration ? */
31 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
32 unsigned char mpf_feature3; /* Unused (0) */
33 unsigned char mpf_feature4; /* Unused (0) */
34 unsigned char mpf_feature5; /* Unused (0) */
36 sizecheck_struct(intel_mp_floating, 16);
38 struct mp_config_table
40 char mpc_signature[4];
41 #define MPC_SIGNATURE "PCMP"
42 unsigned short mpc_length; /* Size of table */
43 char mpc_spec; /* 0x01 */
46 char mpc_productid[12];
47 unsigned int mpc_oemptr; /* 0 if not present */
48 unsigned short mpc_oemsize; /* 0 if not present */
49 unsigned short mpc_oemcount;
50 unsigned int mpc_lapic; /* APIC address */
51 unsigned int reserved;
54 /* Followed by entries */
56 #define MP_PROCESSOR 0
62 struct mpc_config_processor
64 unsigned char mpc_type;
65 unsigned char mpc_apicid; /* Local APIC number */
66 unsigned char mpc_apicver; /* Its versions */
67 unsigned char mpc_cpuflag;
68 #define CPU_ENABLED 1 /* Processor is available */
69 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
70 unsigned int mpc_cpufeature;
71 #define CPU_STEPPING_MASK 0x0F
72 #define CPU_MODEL_MASK 0xF0
73 #define CPU_FAMILY_MASK 0xF00
74 unsigned int mpc_featureflag; /* CPUID feature value */
75 unsigned int mpc_reserved[2];
80 unsigned char mpc_type;
81 unsigned char mpc_busid;
82 unsigned char mpc_bustype[6];
85 /* List of Bus Type string values, Intel MP Spec. */
86 #define BUSTYPE_EISA "EISA"
87 #define BUSTYPE_ISA "ISA"
88 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
89 #define BUSTYPE_MCA "MCA"
90 #define BUSTYPE_VL "VL" /* Local bus */
91 #define BUSTYPE_PCI "PCI"
92 #define BUSTYPE_PCMCIA "PCMCIA"
93 #define BUSTYPE_CBUS "CBUS"
94 #define BUSTYPE_CBUSII "CBUSII"
95 #define BUSTYPE_FUTURE "FUTURE"
96 #define BUSTYPE_MBI "MBI"
97 #define BUSTYPE_MBII "MBII"
98 #define BUSTYPE_MPI "MPI"
99 #define BUSTYPE_MPSA "MPSA"
100 #define BUSTYPE_NUBUS "NUBUS"
101 #define BUSTYPE_TC "TC"
102 #define BUSTYPE_VME "VME"
103 #define BUSTYPE_XPRESS "XPRESS"
105 struct mpc_config_ioapic
107 unsigned char mpc_type;
108 unsigned char mpc_apicid;
109 unsigned char mpc_apicver;
110 unsigned char mpc_flags;
111 #define MPC_APIC_USABLE 0x01
112 unsigned int mpc_apicaddr;
115 struct mpc_config_intsrc
117 unsigned char mpc_type;
118 unsigned char mpc_irqtype;
119 unsigned short mpc_irqflag;
120 unsigned char mpc_srcbus;
121 unsigned char mpc_srcbusirq;
122 unsigned char mpc_dstapic;
123 unsigned char mpc_dstirq;
126 enum mp_irq_source_types {
133 #define MP_IRQDIR_DEFAULT 0
134 #define MP_IRQDIR_HIGH 1
135 #define MP_IRQDIR_LOW 3
138 struct mpc_config_lintsrc
140 unsigned char mpc_type;
141 unsigned char mpc_irqtype;
142 unsigned short mpc_irqflag;
143 unsigned char mpc_srcbusid;
144 unsigned char mpc_srcbusirq;
145 unsigned char mpc_destapic;
146 #define MP_APIC_ALL 0xFF
147 unsigned char mpc_destapiclint;
151 * Default configurations
153 * 1 2 CPU ISA 82489DX
154 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
155 * 3 2 CPU EISA 82489DX
156 * 4 2 CPU MCA 82489DX
162 #define MAX_MP_BUSSES 256
163 /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
164 #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
171 extern unsigned char mp_bus_id_to_type [MAX_MP_BUSSES];
172 extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
174 extern unsigned int boot_cpu_physical_apicid;
175 extern int smp_found_config;
176 extern void find_mp_config(void);
177 extern void get_mp_config(void);
178 extern int nr_ioapics;
179 extern unsigned char apic_version [MAX_APICS];
180 extern int mp_irq_entries;
181 extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES];
182 extern int mpc_default_type;
183 extern unsigned long mp_lapic_addr;
187 extern void mp_register_lapic (u8 id, u8 enabled);
188 extern void mp_register_lapic_address (u64 address);
190 #ifdef CONFIG_X86_IO_APIC
191 extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
192 extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi);
193 extern void mp_config_acpi_legacy_irqs (void);
194 extern int mp_register_gsi (u32 gsi, int triggering, int polarity);
195 #endif /*CONFIG_X86_IO_APIC*/
198 extern int using_apic_timer;
200 #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
204 unsigned long mask[PHYSID_ARRAY_SIZE];
207 typedef struct physid_mask physid_mask_t;
209 #define physid_set(physid, map) set_bit(physid, (map).mask)
210 #define physid_clear(physid, map) clear_bit(physid, (map).mask)
211 #define physid_isset(physid, map) test_bit(physid, (map).mask)
212 #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
214 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
215 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
216 #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
217 #define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS)
218 #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
219 #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
220 #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
221 #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
222 #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
223 #define physids_coerce(map) ((map).mask[0])
225 #define physids_promote(physids) \
227 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
228 __physid_mask.mask[0] = physids; \
232 #define physid_mask_of_physid(physid) \
234 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
235 physid_set(physid, __physid_mask); \
239 #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
240 #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
242 extern physid_mask_t phys_cpu_present_map;