2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
12 #include <lwk/linkage.h>
15 #include <arch/desc.h>
16 #include <arch/segment.h>
17 #include <arch/pgtable.h>
18 #include <arch/page.h>
20 #include <arch/cache.h>
22 /* we are not able to switch in one step to the final KERNEL ADRESS SPACE
23 * because we need identity-mapped pages.
28 .section .bootstrap.text
36 movl $(__KERNEL_DS), %eax
38 lgdt gdt32_descr - __START_KERNEL_map
40 /* Enable PAE mode and PGE */
42 btsl $5, %eax /* enable PAE */
43 btsl $7, %eax /* enable PGE */
46 /* Setup early boot page tables */
47 movl $(init_level4_pgt - __START_KERNEL_map), %eax
50 /* Enable Long Mode */
56 btsl $31, %eax /* enable paging */
57 btsl $0, %eax /* enable protected mode */
60 /* coldstart uses a hard-coded address for real_mode_data */
64 * At this point we're in long mode but 32-bit compatibility mode.
65 * This jump transitions us into true 64-bit mode.
67 ljmp $__KERNEL_CS, $(startup_64 - __START_KERNEL_map)
68 #endif /* CONFIG_CRAY_XT */
75 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
76 * and someone has loaded an identity mapped page table
77 * for us. These identity mapped page tables map all of the
78 * kernel pages and possibly all of memory.
80 * %esi holds a physical pointer to real_mode_data.
82 * We come here either directly from a 64bit bootloader, or from
83 * arch/x86_64/boot/compressed/head.S.
85 * We only come here initially at boot nothing else comes here.
87 * Since we may be loaded at an address different from what we were
88 * compiled to run at we first fixup the physical addresses in our page
89 * tables and then reload them.
92 /* Compute the delta between the address I am compiled to run at and the
93 * address I am actually running at.
95 leaq _text(%rip), %rbp
96 subq $_text - __START_KERNEL_map, %rbp
98 /* Is the address not 2M aligned? */
100 andl $~LARGE_PAGE_MASK, %eax
104 /* Is the address too large? */
105 leaq _text(%rip), %rdx
106 movq $PGDIR_SIZE, %rax
110 /* Fixup the physical addresses in the page table
112 addq %rbp, init_level4_pgt + 0(%rip)
113 addq %rbp, init_level4_pgt + (258*8)(%rip)
114 addq %rbp, init_level4_pgt + (511*8)(%rip)
116 addq %rbp, level3_ident_pgt + 0(%rip)
117 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
119 /* Add an Identity mapping if I am above 1G */
120 leaq _text(%rip), %rdi
121 andq $LARGE_PAGE_MASK, %rdi
124 shrq $PUD_SHIFT, %rax
125 andq $(PTRS_PER_PUD - 1), %rax
128 leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
129 leaq level3_ident_pgt(%rip), %rbx
130 movq %rdx, 0(%rbx, %rax, 8)
133 shrq $PMD_SHIFT, %rax
134 andq $(PTRS_PER_PMD - 1), %rax
135 leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
136 leaq level2_spare_pgt(%rip), %rbx
137 movq %rdx, 0(%rbx, %rax, 8)
140 /* Fixup the kernel text+data virtual addresses
142 leaq level2_kernel_pgt(%rip), %rdi
144 /* See if it is a valid page table entry */
148 /* Go to the next page */
153 /* Fixup phys_base */
154 addq %rbp, phys_base(%rip)
156 addq %rbp, trampoline_level4_pgt + 0(%rip)
157 addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
158 #ifdef CONFIG_ACPI_SLEEP
159 addq %rbp, wakeup_level4_pgt + 0(%rip)
160 addq %rbp, wakeup_level4_pgt + (511*8)(%rip)
163 /* Due to ENTRY(), sometimes the empty space gets filled with
164 * zeros. Better take a jmp than relying on empty space being
165 * filled with 0x90 (nop)
167 jmp secondary_startup_64
168 ENTRY(secondary_startup_64)
170 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
171 * and someone has loaded a mapped page table.
173 * %esi holds a physical pointer to real_mode_data.
175 * We come here either from startup_64 (using physical addresses)
176 * or from trampoline.S (using virtual addresses).
178 * Using virtual addresses from trampoline.S removes the need
179 * to have any identity mapped pages in the kernel page table
180 * after the boot processor executes this code.
183 /* Enable PAE mode and PGE */
189 /* Setup early boot stage 4 level pagetables. */
190 movq $(init_level4_pgt - __START_KERNEL_map), %rax
191 addq phys_base(%rip), %rax
194 /* Ensure I am executing from virtual addresses */
199 /* Check if nx is implemented */
200 movl $0x80000001, %eax
204 /* Setup EFER (Extended Feature Enable Register) */
207 btsl $_EFER_SCE, %eax /* Enable System Call */
208 btl $20,%edi /* No Execute supported? */
211 1: wrmsr /* Make changes effective */
214 #define CR0_PM 1 /* protected mode */
215 #define CR0_MP (1<<1)
216 #define CR0_ET (1<<4)
217 #define CR0_NE (1<<5)
218 #define CR0_WP (1<<16)
219 #define CR0_AM (1<<18)
220 #define CR0_PAGING (1<<31)
221 movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
222 /* Make changes effective */
225 /* Setup a boot time stack */
226 movq init_rsp(%rip),%rsp
228 /* zero EFLAGS after setting rsp */
233 * We must switch to a new descriptor in kernel space for the GDT
234 * because soon the kernel won't have access anymore to the userspace
235 * addresses where we're currently running on. We have to do that here
236 * because in 32bit we couldn't load a 64bit linear address.
238 lgdt cpu_gdt_descr(%rip)
240 /* set up data segments. actually 0 would do too */
241 movl $__KERNEL_DS,%eax
247 * We don't really need to load %fs or %gs, but load them anyway
248 * to kill any stale realmode selectors. This allows execution
255 * Setup up a dummy PDA. this is just for some early bootup code
256 * that does in_interrupt()
258 movl $MSR_GS_BASE,%ecx
259 movq $empty_zero_page,%rax
264 /* esi is pointer to real mode structure with interesting info.
268 /* Finally jump to run C code and to be on real kernel address
269 * Since we are running on identity-mapped space we have to jump
270 * to the full 64bit address, this is only possible as indirect
271 * jump. In addition we need to ensure %cs is set so we make this
274 movq initial_code(%rip),%rax
275 pushq $0 # fake return address to stop unwinder
276 pushq $__KERNEL_CS # set correct cs
277 pushq %rax # target address in negative space
280 /* SMP bootup changes these two */
284 .quad x86_64_start_kernel
287 .quad bootstrap_task_union+TASK_SIZE-8
292 ENTRY(early_idt_handler)
293 cmpl $2,early_recursion_flag(%rip)
295 incl early_recursion_flag(%rip)
297 movq 8(%rsp),%rsi # get rip
300 leaq early_idt_msg(%rip),%rdi
302 cmpl $2,early_recursion_flag(%rip)
307 early_recursion_flag:
311 .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
317 #define NEXT_PAGE(name) \
321 /* Automate the creation of 1 to 1 mapping pmd entries */
322 #define PMDS(START, PERM, COUNT) \
325 .quad (START) + (i << 21) + (PERM) ; \
330 * This default setting generates an ident mapping at address 0x100000
331 * and a mapping for the kernel that precisely maps virtual address
332 * 0xffffffff80000000 to physical address 0x000000. (always using
333 * 2Mbyte large pages provided by PAE mode)
335 NEXT_PAGE(init_level4_pgt)
336 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
338 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
340 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
341 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
343 NEXT_PAGE(level3_ident_pgt)
344 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
347 NEXT_PAGE(level3_kernel_pgt)
349 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
350 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
351 #ifndef CONFIG_CRAY_XT
354 .quad level2_seastar_pgt - __START_KERNEL_map + _KERNPG_TABLE
357 NEXT_PAGE(level2_ident_pgt)
358 /* Since I easily can, map the first 1G.
359 * Don't set NX because code runs from these pages.
361 PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
363 NEXT_PAGE(level2_kernel_pgt)
364 /* 40MB kernel mapping. The kernel code cannot be bigger than that.
365 When you change this change KERNEL_TEXT_SIZE in page.h too. */
366 /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
367 PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE)
368 /* Module mapping starts here */
369 .fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0
371 #ifdef CONFIG_CRAY_XT
372 NEXT_PAGE(level2_seastar_pgt)
374 .quad 0x00000000ffe00193
377 NEXT_PAGE(level2_spare_pgt)
387 .word gdt_end-cpu_gdt_table-1
395 #ifdef CONFIG_CRAY_XT
399 .word gdt_end-cpu_gdt_table-1
400 .long cpu_gdt_table-__START_KERNEL_map
404 /* This must match the first entry in level2_kernel_pgt */
405 .quad 0x0000000000000000
407 /* We need valid kernel segments for data and code in long mode too
408 * IRET will check the segment types kkeil 2000/10/28
409 * Also sysret mandates a special GDT layout
412 .section .data.page_aligned, "aw"
415 /* The TLS descriptors are currently at a different place compared to i386.
416 Hopefully nobody expects them at a fixed place (Wine?) */
419 .quad 0x0000000000000000 /* NULL descriptor */
420 .quad 0x00cf9b000000ffff /* __KERNEL32_CS */
421 .quad 0x00af9b000000ffff /* __KERNEL_CS */
422 .quad 0x00cf93000000ffff /* __KERNEL_DS */
423 .quad 0x00cffb000000ffff /* __USER32_CS */
424 .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */
425 .quad 0x00affb000000ffff /* __USER_CS */
426 .quad 0x0 /* unused */
429 .quad 0,0,0 /* three TLS descriptors */
430 .quad 0x0000f40000000000 /* node/CPU stored in limit */
432 /* asm/segment.h:GDT_ENTRIES must match this */
433 /* This should be a multiple of the cache line size */
434 /* GDTs of other CPUs are now dynamically allocated */
436 /* zero the remaining page */
437 .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
439 .section .bss, "aw", @nobits
440 .align L1_CACHE_BYTES
444 .section .bss.page_aligned, "aw", @nobits
446 ENTRY(empty_zero_page)