7 #define EFLAGS_CF (1<<0) // carry out
8 // next bit reserved and must be 1
9 #define EFLAGS_PF (1<<2) // ?
10 // next bit reserved and must be zero
11 #define EFLAGS_AF (1<<4) // ?
12 // next bit reserved and must be zero
13 #define EFLAGS_ZF (1<<6) // zero
14 #define EFLAGS_SF (1<<7) // sign
15 #define EFLAGS_TF (1<<8) // Trap flag
16 #define EFLAGS_IF (1<<9) // Interrupt Enable
17 #define EFLAGS_DF (1<<10) // ?
18 #define EFLAGS_OF (1<<11) // overflow
19 #define EFLAGS_IOPL_LO (1<<12) // IO privilege level low bit
20 #define EFLAGS_IOPL_HI (1<<13) // IO privilege level low bit
21 #define EFLAGS_NT (1<<14) // Nested Task
22 // next bit reserved and must be zero
23 #define EFLAGS_RF (1<<16) // Resume Flag
24 #define EFLAGS_VM (1<<17) // V8086 mode
25 #define EFLAGS_AC (1<<18) // Alignment Check
26 #define EFLAGS_VIF (1<<19) // Virtual interrupt flag
27 #define EFLAGS_VIP (1<<20) // Virtual interrupt pending
28 #define EFLAGS_ID (1<<21) // identification flag
29 // remaining bits reserved and must be zero
32 #define IOPL(r) ( ( (r) & (EFLAGS_IOPL_LO | EFLAGS_IOPL_HI)) >> 12 )
38 #define CR0_PE (1<<0) // protection enabled (protected mode)
39 #define CR0_MP (1<<1) // monitor coprocessor exists?
40 #define CR0_EM (1<<2) // Emulation (set = no FPU)
41 #define CR0_TS (1<<3) // Task switched (enable = avoid FPU/SSE context save on HW task switch)
42 #define CR0_ET (1<<4) // extension type (FPU on 386/486, reserved afterward)
43 #define CR0_NE (1<<5) // numeric error enable (FPU) (PC-style = disabled)
44 // next group of bits are reserved
45 #define CR0_WP (1<<16) // write protect (disallow supervisor access to user pages)
46 // next bit is reserved
47 #define CR0_AM (1<<17) // alignment mask
48 // next group of bits are reserved
49 #define CR0_NW (1<<29) // not write through
50 #define CR0_CD (1<<30) // cache disable
51 #define CR0_PG (1<<31) // paging enable
55 // All of CR1 is reserved
60 // CR2 is the linear address of a page fault (output only)
61 // only useful in a page fault context
66 // CR3 is the page table base register and friends
68 #define CR3_PWT (1<<3) // page-level writes transparent
69 #define CR3_PCD (1<<4) // page-level cache disable (avoid caching the first level page table)
71 #define CR3_PAGE_DIRECTORY_BASE_ADDRESS(reg) ((reg)&0xfffff000)
76 #define CR4_VME (1<<0) // V8086 mode extensions (set = inter/except handling extensions on)
77 #define CR4_PVI (1<<1) // Protected mode virtual interrupts (VIF)
78 #define CR4_TSD (1<<2) // Time stamp disable (disallow rdstc for ring>0)
79 #define CR4_DE (1<<3) // Debugging extensions (debug registers)
80 #define CR4_PSE (1<<4) // Page size extensions (allow 4 MB pages)
81 #define CR4_PAE (1<<5) // Physical Address Extensions (36+ bit addressing (PAE + IA32e)
82 #define CR4_MCE (1<<6) // Machine Check enable (allow generation of MC exception)
83 #define CR4_PGE (1<<7) // Page global enable (allow global pages)
84 #define CR4_PCE (1<<8) // Performance counter enable (allow access to any ring)
85 #define CR4_OSFXSR (1<<9) // OS Support for FXSAVE/RSTOR (fast FPU/SSE context instructions)
86 #define CR4_OSMMEXCEPT (1<<10) // OS Support for unmasked SIMD FP exceptions (SSE)
87 // next two bits reserved and set to zero
88 #define CR4_VMXE (1<<13) // Allow the VMX instruction
89 // rest of the bits reserved and set to zero
