bios/seabios/src/pirtable.c

   1 // PIR table generation (for emulators)
   2 //
   3 // Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
   4 // Copyright (C) 2002  MandrakeSoft S.A.
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "pci.h" // struct pir_header
   9 #include "util.h" // checksum
  10 #include "biosvar.h" // SET_EBDA
  11
  12 u16 PirOffset VAR16VISIBLE;
  13
  14 struct pir_table {
  15     struct pir_header pir;
  16     struct pir_slot slots[6];
  17 } PACKED;
  18
  19 extern struct pir_table PIR_TABLE;
  20 #if CONFIG_PIRTABLE && !CONFIG_COREBOOT
  21 struct pir_table PIR_TABLE __aligned(16) VAR16EXPORT = {
  22     .pir = {
  23         .version = 0x0100,
  24         .size = sizeof(struct pir_table),
  25         .router_devfunc = 0x08,
  26         .compatible_devid = 0x122e8086,
  27     },
  28     .slots = {
  29         {
  30             // first slot entry PCI-to-ISA (embedded)
  31             .dev = 1<<3,
  32             .links = {
  33                 {.link = 0x60, .bitmap = 0xdef8}, // INTA#
  34                 {.link = 0x61, .bitmap = 0xdef8}, // INTB#
  35                 {.link = 0x62, .bitmap = 0xdef8}, // INTC#
  36                 {.link = 0x63, .bitmap = 0xdef8}, // INTD#
  37             },
  38             .slot_nr = 0, // embedded
  39         }, {
  40             // second slot entry: 1st PCI slot
  41             .dev = 2<<3,
  42             .links = {
  43                 {.link = 0x61, .bitmap = 0xdef8}, // INTA#
  44                 {.link = 0x62, .bitmap = 0xdef8}, // INTB#
  45                 {.link = 0x63, .bitmap = 0xdef8}, // INTC#
  46                 {.link = 0x60, .bitmap = 0xdef8}, // INTD#
  47             },
  48             .slot_nr = 1,
  49         }, {
  50             // third slot entry: 2nd PCI slot
  51             .dev = 3<<3,
  52             .links = {
  53                 {.link = 0x62, .bitmap = 0xdef8}, // INTA#
  54                 {.link = 0x63, .bitmap = 0xdef8}, // INTB#
  55                 {.link = 0x60, .bitmap = 0xdef8}, // INTC#
  56                 {.link = 0x61, .bitmap = 0xdef8}, // INTD#
  57             },
  58             .slot_nr = 2,
  59         }, {
  60             // 4th slot entry: 3rd PCI slot
  61             .dev = 4<<3,
  62             .links = {
  63                 {.link = 0x63, .bitmap = 0xdef8}, // INTA#
  64                 {.link = 0x60, .bitmap = 0xdef8}, // INTB#
  65                 {.link = 0x61, .bitmap = 0xdef8}, // INTC#
  66                 {.link = 0x62, .bitmap = 0xdef8}, // INTD#
  67             },
  68             .slot_nr = 3,
  69         }, {
  70             // 5th slot entry: 4rd PCI slot
  71             .dev = 5<<3,
  72             .links = {
  73                 {.link = 0x60, .bitmap = 0xdef8}, // INTA#
  74                 {.link = 0x61, .bitmap = 0xdef8}, // INTB#
  75                 {.link = 0x62, .bitmap = 0xdef8}, // INTC#
  76                 {.link = 0x63, .bitmap = 0xdef8}, // INTD#
  77             },
  78             .slot_nr = 4,
  79         }, {
  80             // 6th slot entry: 5rd PCI slot
  81             .dev = 6<<3,
  82             .links = {
  83                 {.link = 0x61, .bitmap = 0xdef8}, // INTA#
  84                 {.link = 0x62, .bitmap = 0xdef8}, // INTB#
  85                 {.link = 0x63, .bitmap = 0xdef8}, // INTC#
  86                 {.link = 0x60, .bitmap = 0xdef8}, // INTD#
  87             },
  88             .slot_nr = 5,
  89         },
  90     }
  91 };
  92 #endif // CONFIG_PIRTABLE && !CONFIG_COREBOOT
  93
  94 void
  95 create_pirtable(void)
  96 {
  97     if (! CONFIG_PIRTABLE)
  98         return;
  99
 100     dprintf(3, "init PIR table\n");
 101
 102     PIR_TABLE.pir.signature = PIR_SIGNATURE;
 103     PIR_TABLE.pir.checksum -= checksum(&PIR_TABLE, sizeof(PIR_TABLE));
 104     PirOffset = (u32)&PIR_TABLE.pir - BUILD_BIOS_ADDR;
 105 }