From: Kyle Hale <kh@u.northwestern.edu>
Date: Tue, 25 Mar 2014 18:44:50 +0000 (-0500)
Subject: expose RTM cap in CPUID
X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?p=palacios.git;a=commitdiff_plain;h=e42b257e5364f8ddba2c86668631013859cb2e46

expose RTM cap in CPUID
---

diff --git a/palacios/include/extensions/trans_mem.h b/palacios/include/extensions/trans_mem.h
index f8d980e..68a1636 100644
--- a/palacios/include/extensions/trans_mem.h
+++ b/palacios/include/extensions/trans_mem.h
@@ -19,6 +19,38 @@
  * This is free software.  You are permitted to use,
  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
  *
+ 
+RTM Implementation Wishlist (roughly in order of priority)
+Kyle Hale, Maciek Swiech 2014
+
+From Intel Architecture Instruction Set Extensions Programming Reference, Section 8.3, p.8-6
+link: http://software.intel.com/sites/default/files/m/9/2/3/41604
+
+- on XABORT / abort RAX needs to be set with the reason
+- architectural registers need to be saved / restored 
+- exceptions that misuse of TSX instructions can raise
+- abort on interrupts, asynchronous events
+- abort on CPUID, PAUSE
+- abort on non-writeback memory ops, including ifetches to uncacheable mem
+- RTM-debugger support
+- RTM nesting
+- parameterized cache model, for generating hardware configuration-based aborts
+
+- to be able to model specific implementations, add options (runtime or compiletime) to abort on:
+    * x86/mmx state changes, (also fxstor, fxsave),
+    * cli, sti, popfd, popfq, clts
+    * mov to segment regs, pop segment regs, lds, les, lfs, lgs, lss, swapgs, wrfsbase, wrgsbase, lgdt, sgdt, lidt, sidt, lldt, sldt, ltr, 
+      str, far call, far jmp, far ret, far iret, mov to DRx, mov to cr0-4, cr8 lmsw
+    * sysenter, syscall, sysexit, sysret
+    * clflush, invd, wbinvd, invlpg, invpcid
+    * memory instructions with temporal hints (e.g. movntdqa)
+    * xsave, xsaveopt, xrstor
+    * interrupts: INTn, INTO
+    * IO: in, ins, rep ins, out, outs, rep outs, and variants
+    * VMX instructions
+    * smx: getsec
+    * ud2, rsm, rdmsr, wrmsr, hlt, monitor, mwait, xsetbv, vzeroupper, maskmovq, v/maskmovdqu
+    
  *
  *
  * We claim that we can have a single, shared "cache"-like box
diff --git a/palacios/src/extensions/ext_trans_mem.c b/palacios/src/extensions/ext_trans_mem.c
index 82c89ee..9042e55 100644
--- a/palacios/src/extensions/ext_trans_mem.c
+++ b/palacios/src/extensions/ext_trans_mem.c
@@ -1508,6 +1508,34 @@ tm_record_access (struct  v3_trans_mem * tm,
 }
 
 
+static void
+tm_prepare_cpuid (struct v3_vm_info * vm)
+{
+
+    V3_Print(vm, VCORE_NONE, "TM INIT | enabling RTM cap in CPUID\n");
+
+    /* increase max CPUID function to 7 (extended feature flags enumeration) */
+    v3_cpuid_add_fields(vm,0x0,    
+            0xf, 0x7,      
+            0, 0,
+            0, 0,
+            0, 0);
+
+
+    /* do the same for AMD */
+    v3_cpuid_add_fields(vm,0x80000000, 
+            0xffffffff, 0x80000007,   
+            0, 0,
+            0, 0,
+            0, 0);
+
+
+    /* enable RTM (CPUID.07H.EBX.RTM = 1) */
+    v3_cpuid_add_fields(vm, 0x07, 0, 0, (1<<11), 0, 0, 0, 0, 0);
+    v3_cpuid_add_fields(vm, 0x80000007, 0, 0, (1<<11), 0, 0, 0, 0, 0);
+}
+
+
 static int 
 init_trans_mem (struct v3_vm_info * vm, 
                 v3_cfg_tree_t * cfg, 
@@ -1553,6 +1581,8 @@ init_trans_mem (struct v3_vm_info * vm,
     *priv_data = tms;
     tm_global_state = tms;
 
+    tm_prepare_cpuid(vm);
+
     return 0;
 
 out_err1:
@@ -2283,3 +2313,4 @@ v3_tm_decode_rtm_instrs (struct guest_info * info,
     return 0;
 }
 
+