From: Jack Lange Date: Wed, 24 Jun 2009 18:02:04 +0000 (-0500) Subject: first cut at cleaning up the VMX mess X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?p=palacios.git;a=commitdiff_plain;h=1316eb77b6d89245583446dab3345f749c415764 first cut at cleaning up the VMX mess --- diff --git a/palacios/include/palacios/vm_guest.h b/palacios/include/palacios/vm_guest.h index a3a4888..7568636 100644 --- a/palacios/include/palacios/vm_guest.h +++ b/palacios/include/palacios/vm_guest.h @@ -81,9 +81,9 @@ struct v3_dbg_regs { }; struct v3_segment { - ushort_t selector; + uint16_t selector; uint_t limit; - ullong_t base; + uint64_t base; uint_t type : 4; uint_t system : 1; uint_t dpl : 2; @@ -116,7 +116,7 @@ struct v3_profiler; struct guest_info { - ullong_t rip; + uint64_t rip; uint_t cpl; diff --git a/palacios/include/palacios/vmcs.h b/palacios/include/palacios/vmcs.h index 5c78dd6..ab53e1f 100644 --- a/palacios/include/palacios/vmcs.h +++ b/palacios/include/palacios/vmcs.h @@ -31,23 +31,23 @@ /* 16 bit guest state */ -#define VMCS_GUEST_ES_SELECTOR 0x00000800 -#define VMCS_GUEST_CS_SELECTOR 0x00000802 -#define VMCS_GUEST_SS_SELECTOR 0x00000804 -#define VMCS_GUEST_DS_SELECTOR 0x00000806 -#define VMCS_GUEST_FS_SELECTOR 0x00000808 -#define VMCS_GUEST_GS_SELECTOR 0x0000080A -#define VMCS_GUEST_LDTR_SELECTOR 0x0000080C -#define VMCS_GUEST_TR_SELECTOR 0x0000080E +#define VMCS_GUEST_ES_SELECTOR 0x00000800 +#define VMCS_GUEST_CS_SELECTOR 0x00000802 +#define VMCS_GUEST_SS_SELECTOR 0x00000804 +#define VMCS_GUEST_DS_SELECTOR 0x00000806 +#define VMCS_GUEST_FS_SELECTOR 0x00000808 +#define VMCS_GUEST_GS_SELECTOR 0x0000080A +#define VMCS_GUEST_LDTR_SELECTOR 0x0000080C +#define VMCS_GUEST_TR_SELECTOR 0x0000080E /* 16 bit host state */ -#define VMCS_HOST_ES_SELECTOR 0x00000C00 -#define VMCS_HOST_CS_SELECTOR 0x00000C02 -#define VMCS_HOST_SS_SELECTOR 0x00000C04 -#define VMCS_HOST_DS_SELECTOR 0x00000C06 -#define VMCS_HOST_FS_SELECTOR 0x00000C08 -#define VMCS_HOST_GS_SELECTOR 0x00000C0A -#define VMCS_HOST_TR_SELECTOR 0x00000C0C +#define VMCS_HOST_ES_SELECTOR 0x00000C00 +#define VMCS_HOST_CS_SELECTOR 0x00000C02 +#define VMCS_HOST_SS_SELECTOR 0x00000C04 +#define VMCS_HOST_DS_SELECTOR 0x00000C06 +#define VMCS_HOST_FS_SELECTOR 0x00000C08 +#define VMCS_HOST_GS_SELECTOR 0x00000C0A +#define VMCS_HOST_TR_SELECTOR 0x00000C0C /* 64 bit control fields */ #define IO_BITMAP_A_ADDR 0x00002000 @@ -204,140 +204,96 @@ /* Processor Based VM Execution Controls */ /* INTEL MANUAL: 20-11 vol. 3B */ -#define INTERRUPT_WINDOWS_EXIT 0x00000004 -#define USE_TSC_OFFSETTING 0x00000008 -#define HLT_EXITING 0x00000080 -#define INVLPG_EXITING 0x00000200 -#define MWAIT_EXITING 0x00000400 -#define RDPMC_EXITING 0x00000800 -#define RDTSC_EXITING 0x00001000 -#define CR8_LOAD_EXITING 0x00080000 -#define CR8_STORE_EXITING 0x00100000 -#define USE_TPR_SHADOW 0x00200000 -#define NMI_WINDOW_EXITING 0x00400000 -#define MOVDR_EXITING 0x00800000 -#define UNCONDITION_IO_EXITING 0x01000000 -#define USE_IO_BITMAPS 0x02000000 -#define USE_MSR_BITMAPS 0x10000000 -#define MONITOR_EXITING 0x20000000 -#define PAUSE_EXITING 0x40000000 +#define INTERRUPT_WINDOWS_EXIT 0x00000004 +#define USE_TSC_OFFSETTING 0x00000008 +#define HLT_EXITING 0x00000080 +#define INVLPG_EXITING 0x00000200 +#define MWAIT_EXITING 0x00000400 +#define RDPMC_EXITING 0x00000800 +#define RDTSC_EXITING 0x00001000 +#define CR8_LOAD_EXITING 0x00080000 +#define CR8_STORE_EXITING 0x00100000 +#define USE_TPR_SHADOW 0x00200000 +#define NMI_WINDOW_EXITING 0x00400000 +#define MOVDR_EXITING 0x00800000 +#define UNCONDITION_IO_EXITING 0x01000000 +#define USE_IO_BITMAPS 0x02000000 +#define USE_MSR_BITMAPS 0x10000000 +#define MONITOR_EXITING 0x20000000 +#define PAUSE_EXITING 0x40000000 /* VM-Exit Controls */ /* INTEL MANUAL: 20-16 vol. 3B */ -#define HOST_ADDR_SPACE_SIZE 0x00000200 -#define ACK_IRQ_ON_EXIT 0x00008000 - -// Exit Reasons -#define VM_EXIT_REASON_INFO_EXCEPTION_OR_NMI 0 -#define VM_EXIT_REASON_EXTERNAL_INTR 1 -#define VM_EXIT_REASON_TRIPLE_FAULT 2 -#define VM_EXIT_REASON_INIT_SIGNAL 3 -#define VM_EXIT_REASON_STARTUP_IPI 4 -#define VM_EXIT_REASON_IO_SMI 5 -#define VM_EXIT_REASON_OTHER_SMI 6 -#define VM_EXIT_REASON_INTR_WINDOW 7 -#define VM_EXIT_REASON_NMI_WINDOW 8 -#define VM_EXIT_REASON_TASK_SWITCH 9 -#define VM_EXIT_REASON_CPUID 10 -#define VM_EXIT_REASON_HLT 12 -#define VM_EXIT_REASON_INVD 13 -#define VM_EXIT_REASON_INVLPG 14 -#define VM_EXIT_REASON_RDPMC 15 -#define VM_EXIT_REASON_RDTSC 16 -#define VM_EXIT_REASON_RSM 17 -#define VM_EXIT_REASON_VMCALL 18 -#define VM_EXIT_REASON_VMCLEAR 19 -#define VM_EXIT_REASON_VMLAUNCH 20 -#define VM_EXIT_REASON_VMPTRLD 21 -#define VM_EXIT_REASON_VMPTRST 22 -#define VM_EXIT_REASON_VMREAD 23 -#define VM_EXIT_REASON_VMRESUME 24 -#define VM_EXIT_REASON_VMWRITE 25 -#define VM_EXIT_REASON_VMXOFF 26 -#define VM_EXIT_REASON_VMXON 27 -#define VM_EXIT_REASON_CR_REG_ACCESSES 28 -#define VM_EXIT_REASON_MOV_DR 29 -#define VM_EXIT_REASON_IO_INSTR 30 -#define VM_EXIT_REASON_RDMSR 31 -#define VM_EXIT_REASON_WRMSR 32 -#define VM_EXIT_REASON_ENTRY_FAIL_INVALID_GUEST_STATE 33 -#define VM_EXIT_REASON_ENTRY_FAIL_MSR_LOAD 34 -#define VM_EXIT_REASON_MWAIT 36 -#define VM_EXIT_REASON_MONITOR 39 -#define VM_EXIT_REASON_PAUSE 40 -#define VM_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 41 -#define VM_EXIT_REASON_TPR_BELOW_THRESHOLD 43 - - -extern char *exception_names[]; -extern char *exception_type_names[]; - - - - -typedef void VMCS; +#define HOST_ADDR_SPACE_SIZE 0x00000200 +#define ACK_IRQ_ON_EXIT 0x00008000 + + + + + +typedef void vmcs_t; /* VMCS Exit QUALIFICATIONs */ struct VMExitIOQual { - uint_t accessSize : 3; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes) - uint_t dir : 1; // (0: Out ;; 1: In) - uint_t string : 1; // (0: not string ;; 1: string) - uint_t REP : 1; // (0: not REP ;; 1: REP) - uint_t opEnc : 1; // (0: DX ;; 1: immediate) - uint_t rsvd : 9; // Set to 0 - uint_t port : 16; // IO Port Number + uint32_t accessSize : 3; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes) + uint32_t dir : 1; // (0: Out ;; 1: In) + uint32_t string : 1; // (0: not string ;; 1: string) + uint32_t REP : 1; // (0: not REP ;; 1: REP) + uint32_t opEnc : 1; // (0: DX ;; 1: immediate) + uint32_t rsvd : 9; // Set to 0 + uint32_t port : 16; // IO Port Number } __attribute__((packed)); struct VMExitDBGQual { - uint_t B0 : 1; // Breakpoint 0 condition met - uint_t B1 : 1; // Breakpoint 1 condition met - uint_t B2 : 1; // Breakpoint 2 condition met - uint_t B3 : 1; // Breakpoint 3 condition met - uint_t rsvd : 9; // reserved to 0 - uint_t BD : 1; // detected DBG reg access - uint_t BS : 1; // cause either single instr or taken branch + uint32_t B0 : 1; // Breakpoint 0 condition met + uint32_t B1 : 1; // Breakpoint 1 condition met + uint32_t B2 : 1; // Breakpoint 2 condition met + uint32_t B3 : 1; // Breakpoint 3 condition met + uint32_t rsvd : 9; // reserved to 0 + uint32_t BD : 1; // detected DBG reg access + uint32_t BS : 1; // cause either single instr or taken branch } __attribute__((packed)); struct VMExitTSQual { - uint_t selector : 16; // selector of destination TSS - uint_t rsvd : 14; // reserved to 0 - uint_t src : 2; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT) + uint32_t selector : 16; // selector of destination TSS + uint32_t rsvd : 14; // reserved to 0 + uint32_t src : 2; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT) } __attribute__((packed)); struct VMExitCRQual { - uint_t crID : 4; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit) - uint_t accessType : 2; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW) - uint_t lmswOpType : 1; // (0: register ; 1: memory) - uint_t rsvd1 : 1; // reserved to 0 - uint_t gpr : 4; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs) - uint_t rsvd2 : 4; // reserved to 0 - uint_t lmswSrc : 16; // src data for lmsw + uint32_t crID : 4; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit) + uint32_t accessType : 2; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW) + uint32_t lmswOpType : 1; // (0: register ; 1: memory) + uint32_t rsvd1 : 1; // reserved to 0 + uint32_t gpr : 4; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs) + uint32_t rsvd2 : 4; // reserved to 0 + uint32_t lmswSrc : 16; // src data for lmsw } __attribute__((packed)); struct VMExitMovDRQual { - uint_t regID : 3; // debug register number - uint_t rsvd1 : 1; // reserved to 0 - uint_t dir : 1; // (0: MOV to DR , 1: MOV from DR) - uint_t rsvd2 : 3; // reserved to 0 - uint_t gpr : 4; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs) + uint32_t regID : 3; // debug register number + uint32_t rsvd1 : 1; // reserved to 0 + uint32_t dir : 1; // (0: MOV to DR , 1: MOV from DR) + uint32_t rsvd2 : 3; // reserved to 0 + uint32_t gpr : 4; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs) } __attribute__((packed)); /* End Exit Qualifications */ /* Exit Vector Info */ struct VMExitIntInfo { - uint_t nr : 8; // IRQ number, exception vector, NMI = 2 - uint_t type : 3; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception - uint_t errorCode : 1; // 1: error Code present - uint_t iret : 1; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2) - uint_t rsvd : 18; // always 0 - uint_t valid : 1; // always 1 if valid + uint32_t nr : 8; // IRQ number, exception vector, NMI = 2 + uint32_t type : 3; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception + uint32_t errorCode : 1; // 1: error Code present + uint32_t iret : 1; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2) + uint32_t rsvd : 18; // always 0 + uint32_t valid : 1; // always 1 if valid } __attribute__((packed)); @@ -350,75 +306,77 @@ struct VMExitIntInfo { /* Segment Selector Access Rights (32 bits) */ /* INTEL Manual: 20-4 vol 3B */ -union SegAccess { - struct { - uchar_t type; - uint_t descType : 1; - uint_t dpl : 2; - uint_t present : 1; - uchar_t rsvd1; - uint_t avail : 1; - uint_t L : 1; // CS only (64 bit active), reserved otherwise - uint_t DB : 1; - uint_t granularity : 1; - uint_t unusable : 1; - uint_t rsvd2 : 15; - } __attribute__((packed)) as_fields; - uint_t as_dword; -} __attribute__((packed)); -struct VMCSSegment { - ushort_t selector ; - union SegAccess access; - uint_t limit ; - uint_t baseAddr ; // should be 64 bits? +struct vmcs_segment { + uint16_t selector; + uint32_t limit; + addr_t baseAddr; + + struct { + union { + uint32_t value; + struct { + uint8_t type; + uint32_t desc_type : 1; + uint32_t dpl : 2; + uint32_t present : 1; + uint8_t rsvd1; + uint32_t avail : 1; + uint32_t long_mode : 1; // CS only (64 bit active), reserved otherwise + uint32_t DB : 1; + uint32_t granularity : 1; + uint32_t unusable : 1; + uint32_t rsvd2 : 15; + } __attribute__((packed)); + } __attribute__((packed)); + } __attribute__((packed)) access; }; struct VMCSGuestStateArea { - /* (1) Guest State Area */ - /* (1.1) Guest Register State */ - uint_t cr0 ; // should be 64 bits? - uint_t cr3 ; // should be 64 bits? - uint_t cr4 ; // should be 64 bits? - uint_t dr7 ; // should be 64 bits? - uint_t rsp ; // should be 64 bits? - uint_t rip ; // should be 64 bits? - uint_t rflags ; // should be 64 bits? - - - struct VMCSSegment cs ; - struct VMCSSegment ss ; - struct VMCSSegment ds ; - struct VMCSSegment es ; - struct VMCSSegment fs ; - struct VMCSSegment gs ; - struct VMCSSegment ldtr ; - struct VMCSSegment tr ; - - struct VMCSSegment gdtr ; - struct VMCSSegment idtr ; - - // MSRs - ullong_t dbg_ctrl ; - uint_t sysenter_cs ; - ullong_t sysenter_esp ; // should be 64 bits? - ullong_t sysenter_eip ; // should be 64 bits? - - uint_t smbase ; - - /* (1.2) Guest Non-register State */ - uint_t activity ; /* (0=Active, 1=HLT, 2=Shutdown, 3=Wait-for-SIPI) - (listed in MSR: IA32_VMX_MISC) */ - - uint_t interrupt_state ; // see Table 20-3 (page 20-6) INTEL MANUAL 3B - - ullong_t pending_dbg_exceptions ; // should be 64 bits? - /* Table 20-4 page 20-8 INTEL MANUAL 3B */ - - ullong_t vmcs_link ; // should be set to 0xffffffff_ffffffff + /* (1) Guest State Area */ + /* (1.1) Guest Register State */ + uint32_t cr0 ; // should be 64 bits? + uint32_t cr3 ; // should be 64 bits? + uint32_t cr4 ; // should be 64 bits? + uint32_t dr7 ; // should be 64 bits? + uint32_t rsp ; // should be 64 bits? + uint32_t rip ; // should be 64 bits? + uint32_t rflags ; // should be 64 bits? + + + struct VMCSSegment cs ; + struct VMCSSegment ss ; + struct VMCSSegment ds ; + struct VMCSSegment es ; + struct VMCSSegment fs ; + struct VMCSSegment gs ; + struct VMCSSegment ldtr ; + struct VMCSSegment tr ; + + struct VMCSSegment gdtr ; + struct VMCSSegment idtr ; + + // MSRs + uint64_t dbg_ctrl ; + uint32_t sysenter_cs ; + uint64_t sysenter_esp ; // should be 64 bits? + uint64_t sysenter_eip ; // should be 64 bits? + + uint32_t smbase ; + + /* (1.2) Guest Non-register State */ + uint32_t activity ; /* (0=Active, 1=HLT, 2=Shutdown, 3=Wait-for-SIPI) + (listed in MSR: IA32_VMX_MISC) */ + + uint32_t interrupt_state ; // see Table 20-3 (page 20-6) INTEL MANUAL 3B + + uint64_t pending_dbg_exceptions ; // should be 64 bits? + /* Table 20-4 page 20-8 INTEL MANUAL 3B */ + + uint64_t vmcs_link ; // should be set to 0xffffffff_ffffffff }; @@ -428,32 +386,32 @@ int CopyInVMCSGuestStateArea(struct VMCSGuestStateArea * p); struct VMCSHostStateArea { - /* (2) Host State Area */ - ullong_t cr0 ; // Should be 64 bits? - ullong_t cr3 ; // should be 64 bits? - ullong_t cr4 ; // should be 64 bits? - ullong_t rsp ; // should be 64 bits? - ullong_t rip ; // should be 64 bits? - - ushort_t csSelector ; - ushort_t ssSelector ; - ushort_t dsSelector ; - ushort_t esSelector ; - ushort_t fsSelector ; - ushort_t gsSelector ; - ushort_t trSelector ; - - ullong_t fsBaseAddr ; // Should be 64 bits? - ullong_t gsBaseAddr ; // Should be 64 bits? - ullong_t trBaseAddr ; // Should be 64 bits? - ullong_t gdtrBaseAddr ; // Should be 64 bits? - ullong_t idtrBaseAddr ; // Should be 64 bits? - - - /* MSRs */ - uint_t sysenter_cs ; - ullong_t sysenter_esp ; // Should be 64 bits? - ullong_t sysenter_eip ; // Should be 64 bits? + /* (2) Host State Area */ + addr_t cr0 ; + addr_t cr3 ; + addr_t cr4 ; + addr_t rsp ; + addr_t rip ; + + addr_t csSelector ; + addr_t ssSelector ; + addr_t dsSelector ; + addr_t esSelector ; + addr_t fsSelector ; + addr_t gsSelector ; + addr_t trSelector ; + + addr_t fsBaseAddr ; + addr_t gsBaseAddr ; + addr_t trBaseAddr ; + addr_t gdtrBaseAddr ; + addr_t idtrBaseAddr ; + + + /* MSRs */ + uint32_t sysenter_cs ; + addr_t sysenter_esp ; + addr_t sysenter_eip ; }; @@ -462,38 +420,36 @@ int CopyInVMCSHostStateArea(struct VMCSHostStateArea *p); struct VMCSExecCtrlFields { - uint_t pinCtrls ; // Table 20-5, Vol 3B. (pg. 20-10) - uint_t procCtrls ; // Table 20-6, Vol 3B. (pg. 20-11) - uint_t execBitmap ; - uint_t pageFaultErrorMask ; - uint_t pageFaultErrorMatch ; - uint_t ioBitmapA ; - uint_t ioBitmapB ; - ullong_t tscOffset ; - uint_t cr0GuestHostMask ; // Should be 64 bits? - uint_t cr0ReadShadow ; // Should be 64 bits? - uint_t cr4GuestHostMask ; // Should be 64 bits? - uint_t cr4ReadShadow ; // Should be 64 bits? - uint_t cr3TargetValue0 ; // should be 64 bits? - uint_t cr3TargetValue1 ; // should be 64 bits? - uint_t cr3TargetValue2 ; // should be 64 bits? - uint_t cr3TargetValue3 ; // should be 64 bits? - uint_t cr3TargetCount ; - - - - /* these fields enabled if "use TPR shadow"==1 */ - /* may not need them */ - ullong_t virtApicPageAddr ; - // uint_t virtApicPageAddrHigh - uint_t tprThreshold ; - /**/ - - ullong_t MSRBitmapsBaseAddr; - - - ullong_t vmcsExecPtr ; - + uint32_t pinCtrls ; // Table 20-5, Vol 3B. (pg. 20-10) + uint32_t procCtrls ; // Table 20-6, Vol 3B. (pg. 20-11) + uint32_t execBitmap ; + uint32_t pageFaultErrorMask ; + uint32_t pageFaultErrorMatch ; + uint32_t ioBitmapA ; + uint32_t ioBitmapB ; + uint64_t tscOffset ; + uint32_t cr0GuestHostMask ; // Should be 64 bits? + uint32_t cr0ReadShadow ; // Should be 64 bits? + uint32_t cr4GuestHostMask ; // Should be 64 bits? + uint32_t cr4ReadShadow ; // Should be 64 bits? + uint32_t cr3TargetValue0 ; // should be 64 bits? + uint32_t cr3TargetValue1 ; // should be 64 bits? + uint32_t cr3TargetValue2 ; // should be 64 bits? + uint32_t cr3TargetValue3 ; // should be 64 bits? + uint32_t cr3TargetCount ; + + + + /* these fields enabled if "use TPR shadow"==1 */ + /* may not need them */ + uint64_t virtApicPageAddr ; + // uint32_t virtApicPageAddrHigh + uint32_t tprThreshold ; + /**/ + + uint64_t MSRBitmapsBaseAddr; + + uint64_t vmcsExecPtr ; }; int CopyOutVMCSExecCtrlFields(struct VMCSExecCtrlFields *p); @@ -503,11 +459,11 @@ int CopyInVMCSExecCtrlFields(struct VMCSExecCtrlFields *p); struct VMCSExitCtrlFields { - uint_t exitCtrls ; // Table 20-7, Vol. 3B (pg. 20-16) - uint_t msrStoreCount ; - ullong_t msrStoreAddr ; - uint_t msrLoadCount ; - ullong_t msrLoadAddr ; + uint32_t exitCtrls ; // Table 20-7, Vol. 3B (pg. 20-16) + uint32_t msrStoreCount ; + uint64_t msrStoreAddr ; + uint32_t msrLoadCount ; + uint64_t msrLoadAddr ; }; int CopyOutVMCSExitCtrlFields(struct VMCSExitCtrlFields *p); @@ -516,12 +472,12 @@ int CopyInVMCSExitCtrlFields(struct VMCSExitCtrlFields *p); struct VMCSEntryCtrlFields { - uint_t entryCtrls ; // Table 20-9, Vol. 3B (pg. 20-18) - uint_t msrLoadCount ; - ullong_t msrLoadAddr ; - uint_t intInfo ; // Table 20-10, Vol. 3B (pg. 20-19) - uint_t exceptionErrorCode ; - uint_t instrLength ; + uint32_t entryCtrls ; // Table 20-9, Vol. 3B (pg. 20-18) + uint32_t msrLoadCount ; + uint64_t msrLoadAddr ; + uint32_t intInfo ; // Table 20-10, Vol. 3B (pg. 20-19) + uint32_t exceptionErrorCode ; + uint32_t instrLength ; }; @@ -530,20 +486,20 @@ int CopyInVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p); struct VMCSExitInfoFields { - uint_t reason; // Table 20-11, Vol. 3B (pg. 20-20) - uint_t qualification ; // Should be 64 bits? - uint_t intInfo ; - uint_t intErrorCode ; - uint_t idtVectorInfo ; - uint_t idtVectorErrorCode ; - uint_t instrLength ; - ullong_t guestLinearAddr ; // Should be 64 bits? - uint_t instrInfo ; - ullong_t ioRCX ; // Should be 64 bits? - ullong_t ioRSI ; // Should be 64 bits? - ullong_t ioRDI ; // Should be 64 bits? - ullong_t ioRIP ; // Should be 64 bits? - uint_t instrErrorField ; + uint32_t reason; // Table 20-11, Vol. 3B (pg. 20-20) + uint32_t qualification ; // Should be 64 bits? + uint32_t intInfo ; + uint32_t intErrorCode ; + uint32_t idtVectorInfo ; + uint32_t idtVectorErrorCode ; + uint32_t instrLength ; + uint64_t guestLinearAddr ; // Should be 64 bits? + uint32_t instrInfo ; + uint64_t ioRCX ; // Should be 64 bits? + uint64_t ioRSI ; // Should be 64 bits? + uint64_t ioRDI ; // Should be 64 bits? + uint64_t ioRIP ; // Should be 64 bits? + uint32_t instrErrorField ; }; @@ -553,15 +509,15 @@ int CopyOutVMCSExitInfoFields(struct VMCSExitInfoFields *p); struct VMCSData { - uint_t revision ; - uint_t abort ; - uint_t exitCtrlFlags; - struct VMCSGuestStateArea guestStateArea ; - struct VMCSHostStateArea hostStateArea ; - struct VMCSExecCtrlFields execCtrlFields ; - struct VMCSExitCtrlFields exitCtrlFields ; - struct VMCSEntryCtrlFields entryCtrlFields ; - struct VMCSExitInfoFields exitInfoFields ; + uint32_t revision ; + uint32_t abort ; + uint32_t exitCtrlFlags; + struct VMCSGuestStateArea guestStateArea ; + struct VMCSHostStateArea hostStateArea ; + struct VMCSExecCtrlFields execCtrlFields ; + struct VMCSExitCtrlFields exitCtrlFields ; + struct VMCSEntryCtrlFields entryCtrlFields ; + struct VMCSExitInfoFields exitInfoFields ; }; @@ -569,14 +525,14 @@ int CopyOutVMCSData(struct VMCSData *p); int CopyInVMCSData(struct VMCSData *p); struct VMXRegs { - uint_t edi; - uint_t esi; - uint_t ebp; - uint_t esp; - uint_t ebx; - uint_t edx; - uint_t ecx; - uint_t eax; + uint32_t edi; + uint32_t esi; + uint32_t ebp; + uint32_t esp; + uint32_t ebx; + uint32_t edx; + uint32_t ecx; + uint32_t eax; }; void PrintTrace_VMX_Regs(struct VMXRegs *regs); @@ -589,15 +545,10 @@ void PrintTrace_VMCSEntryCtrlFields(struct VMCSEntryCtrlFields * entryCtrls); void PrintTrace_VMCSExitInfoFields(struct VMCSExitInfoFields * exitInfo); void PrintTrace_VMCSSegment(char * segname, struct VMCSSegment * seg, int abbr); -VMCS * CreateVMCS(); -extern uint_t VMCS_WRITE(); -extern uint_t VMCS_READ(); //uint_t VMCSRead(uint_t tag, void * val); -#include - #endif // ! __V3VEE__ diff --git a/palacios/include/palacios/vmm_lowlevel.h b/palacios/include/palacios/vmm_lowlevel.h index 7863d19..6558884 100644 --- a/palacios/include/palacios/vmm_lowlevel.h +++ b/palacios/include/palacios/vmm_lowlevel.h @@ -20,6 +20,10 @@ #include +#define CPUID_FEATURE_IDS 0x80000001 +#define CPUID_EXT_FEATURE_IDS 0x80000001 + + #ifdef __V3_32BIT__ static void __inline__ v3_cpuid(uint_t target, addr_t * eax, addr_t * ebx, addr_t * ecx, addr_t * edx) { @@ -92,7 +96,7 @@ static addr_t __inline__ v3_irq_save() { __asm__ __volatile__ ("pushf \n\t" "popl %0 \n\t" "cli \n\t" - :"=g" (x) + :"=g" (state) : :"memory" ); diff --git a/palacios/include/palacios/vmx.h b/palacios/include/palacios/vmx.h index 278622f..d637d8f 100644 --- a/palacios/include/palacios/vmx.h +++ b/palacios/include/palacios/vmx.h @@ -29,68 +29,55 @@ #include #include -#define IA32_FEATURE_CONTROL_MSR ((unsigned int)0x3a) -#define IA32_VMX_BASIC_MSR ((unsigned int)0x480) -#define IA32_VMX_PINBASED_CTLS_MSR ((unsigned int)0x481) -#define IA32_VMX_PROCBASED_CTLS_MSR ((unsigned int)0x482) -#define IA32_VMX_EXIT_CTLS_MSR ((unsigned int)0x483) -#define IA32_VMX_ENTRY_CTLS_MSR ((unsigned int)0x484) -#define IA32_VMX_MISC_MSR ((unsigned int)0x485) -#define IA32_VMX_CR0_FIXED0_MSR ((unsigned int)0x486) -#define IA32_VMX_CR0_FIXED1_MSR ((unsigned int)0x487) -#define IA32_VMX_CR4_FIXED0_MSR ((unsigned int)0x488) -#define IA32_VMX_CR4_FIXED1_MSR ((unsigned int)0x489) -#define IA32_VMX_VMCS_ENUM_MSR ((unsigned ing)0x48A) - -#define VMX_SUCCESS 0 +// Intel VMX Specific MSRs +#define VMX_FEATURE_CONTROL_MSR 0x0000003a +#define VMX_BASIC_MSR 0x00000480 +#define VMX_PINBASED_CTLS_MSR 0x00000481 +#define VMX_PROCBASED_CTLS_MSR 0x00000482 +#define VMX_EXIT_CTLS_MSR 0x00000483 +#define VMX_ENTRY_CTLS_MSR 0x00000484 +#define VMX_MISC_MSR 0x00000485 +#define VMX_CR0_FIXED0_MSR 0x00000486 +#define VMX_CR0_FIXED1_MSR 0x00000487 +#define VMX_CR4_FIXED0_MSR 0x00000488 +#define VMX_CR4_FIXED1_MSR 0x00000489 +#define VMX_VMCS_ENUM_MSR 0x0000048A + +#define VMX_SUCCESS 0 #define VMX_FAIL_INVALID 1 #define VMX_FAIL_VALID 2 #define VMM_ERROR 3 -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_CONTROL_VMXON (1<<2) -#define FEATURE_CONTROL_VALID ( FEATURE_CONTROL_LOCK | FEATURE_CONTROL_VMXON) +#define FEATURE_CONTROL_LOCK 0x00000001 +#define FEATURE_CONTROL_VMXON 0x00000004 +#define FEATURE_CONTROL_VALID ( FEATURE_CONTROL_LOCK | FEATURE_CONTROL_VMXON ) -#define CPUID_1_ECX_VTXFLAG (1<<5) +#define CPUID_1_ECX_VTXFLAG 0x00000020 +struct vmx_basic_msr { + uint32_t revision; + uint_t regionSize : 13; + uint_t rsvd1 : 4; // Always 0 + uint_t physWidth : 1; + uint_t smm : 1; // Always 1 + uint_t memType : 4; + uint_t rsvd2 : 10; // Always 0 +} __attribute__((packed)); -typedef void VmxOnRegion; -struct MSR_REGS { - uint_t low; - uint_t high; -} __attribute__((packed)); +enum VMState { VM_VMXASSIST_STARTUP, VM_VMXASSIST_V8086_BIOS, VM_VMXASSIST_V8086, VM_NORMAL }; -struct VMX_BASIC { - uint_t revision; - uint_t regionSize : 13; - uint_t rsvd1 : 4; // Always 0 - uint_t physWidth : 1; - uint_t smm : 1; // Always 1 - uint_t memType : 4; - uint_t rsvd2 : 10; // Always 0 -} __attribute__((packed)); -union VMX_MSR { - struct MSR_REGS regs; - struct VMX_BASIC vmxBasic; -} __attribute__((packed)); -struct VMDescriptor { - uint_t entry_ip; - uint_t exit_eip; - uint_t guest_esp; -} __attribute__((packed)); -enum VMState { VM_VMXASSIST_STARTUP, VM_VMXASSIST_V8086_BIOS, VM_VMXASSIST_V8086, VM_NORMAL }; struct VM { enum VMState state; @@ -114,7 +101,6 @@ struct Instruction { }; -void DecodeCurrentInstruction(struct VM *vm, struct Instruction *out); int is_vmx_capable(); diff --git a/palacios/src/palacios/svm.c b/palacios/src/palacios/svm.c index ae275c1..5220c83 100644 --- a/palacios/src/palacios/svm.c +++ b/palacios/src/palacios/svm.c @@ -266,9 +266,6 @@ static int init_svm_guest(struct guest_info * info, struct v3_vm_config * config return 0; } - - -// can we start a kernel thread here... static int start_svm_guest(struct guest_info *info) { // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data)); // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data)); @@ -386,7 +383,7 @@ int v3_is_svm_capable() { v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx); - PrintDebug("CPUID_FEATURE_IDS_edx=%p\n", (void *)edx); + PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=%p\n", (void *)edx); if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) { PrintDebug("SVM BIOS Disabled, not unlockable\n"); @@ -399,10 +396,10 @@ int v3_is_svm_capable() { PrintDebug("SVM is available and enabled.\n"); v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx); - PrintDebug("CPUID_FEATURE_IDS_eax=%p\n", (void *)eax); - PrintDebug("CPUID_FEATURE_IDS_ebx=%p\n", (void *)ebx); - PrintDebug("CPUID_FEATURE_IDS_ecx=%p\n", (void *)ecx); - PrintDebug("CPUID_FEATURE_IDS_edx=%p\n", (void *)edx); + PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_eax=%p\n", (void *)eax); + PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ebx=%p\n", (void *)ebx); + PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ecx=%p\n", (void *)ecx); + PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=%p\n", (void *)edx); if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) { diff --git a/palacios/src/palacios/vmcs_gen.c b/palacios/src/palacios/vmcs_gen.c index 4fe1365..93d26a7 100644 --- a/palacios/src/palacios/vmcs_gen.c +++ b/palacios/src/palacios/vmcs_gen.c @@ -20,925 +20,320 @@ - -void Set_VMCS_GUEST_ES_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_ES_SELECTOR,val); } -uint_t Get_VMCS_GUEST_ES_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_ES_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_ES_SELECTOR() { PrintTrace("VMCS_GUEST_ES_SELECTOR = %x\n", Get_VMCS_GUEST_ES_SELECTOR()); } - - -void Set_VMCS_GUEST_CS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_CS_SELECTOR,val); } -uint_t Get_VMCS_GUEST_CS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_CS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_CS_SELECTOR() { PrintTrace("VMCS_GUEST_CS_SELECTOR = %x\n", Get_VMCS_GUEST_CS_SELECTOR()); } - - -void Set_VMCS_GUEST_SS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_SS_SELECTOR,val); } -uint_t Get_VMCS_GUEST_SS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_SS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_SS_SELECTOR() { PrintTrace("VMCS_GUEST_SS_SELECTOR = %x\n", Get_VMCS_GUEST_SS_SELECTOR()); } - - -void Set_VMCS_GUEST_DS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_DS_SELECTOR,val); } -uint_t Get_VMCS_GUEST_DS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_DS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_DS_SELECTOR() { PrintTrace("VMCS_GUEST_DS_SELECTOR = %x\n", Get_VMCS_GUEST_DS_SELECTOR()); } - - -void Set_VMCS_GUEST_FS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_FS_SELECTOR,val); } -uint_t Get_VMCS_GUEST_FS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_FS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_FS_SELECTOR() { PrintTrace("VMCS_GUEST_FS_SELECTOR = %x\n", Get_VMCS_GUEST_FS_SELECTOR()); } - - -void Set_VMCS_GUEST_GS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_GS_SELECTOR,val); } -uint_t Get_VMCS_GUEST_GS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_GS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_GS_SELECTOR() { PrintTrace("VMCS_GUEST_GS_SELECTOR = %x\n", Get_VMCS_GUEST_GS_SELECTOR()); } - - -void Set_VMCS_GUEST_LDTR_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_LDTR_SELECTOR,val); } -uint_t Get_VMCS_GUEST_LDTR_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_LDTR_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_LDTR_SELECTOR() { PrintTrace("VMCS_GUEST_LDTR_SELECTOR = %x\n", Get_VMCS_GUEST_LDTR_SELECTOR()); } - - -void Set_VMCS_GUEST_TR_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_GUEST_TR_SELECTOR,val); } -uint_t Get_VMCS_GUEST_TR_SELECTOR() { uint_t rc; VMCS_READ(VMCS_GUEST_TR_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_GUEST_TR_SELECTOR() { PrintTrace("VMCS_GUEST_TR_SELECTOR = %x\n", Get_VMCS_GUEST_TR_SELECTOR()); } - - -void Set_VMCS_HOST_ES_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_ES_SELECTOR,val); } -uint_t Get_VMCS_HOST_ES_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_ES_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_ES_SELECTOR() { PrintTrace("VMCS_HOST_ES_SELECTOR = %x\n", Get_VMCS_HOST_ES_SELECTOR()); } - - -void Set_VMCS_HOST_CS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_CS_SELECTOR,val); } -uint_t Get_VMCS_HOST_CS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_CS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_CS_SELECTOR() { PrintTrace("VMCS_HOST_CS_SELECTOR = %x\n", Get_VMCS_HOST_CS_SELECTOR()); } - - -void Set_VMCS_HOST_SS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_SS_SELECTOR,val); } -uint_t Get_VMCS_HOST_SS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_SS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_SS_SELECTOR() { PrintTrace("VMCS_HOST_SS_SELECTOR = %x\n", Get_VMCS_HOST_SS_SELECTOR()); } - - -void Set_VMCS_HOST_DS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_DS_SELECTOR,val); } -uint_t Get_VMCS_HOST_DS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_DS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_DS_SELECTOR() { PrintTrace("VMCS_HOST_DS_SELECTOR = %x\n", Get_VMCS_HOST_DS_SELECTOR()); } - - -void Set_VMCS_HOST_FS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_FS_SELECTOR,val); } -uint_t Get_VMCS_HOST_FS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_FS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_FS_SELECTOR() { PrintTrace("VMCS_HOST_FS_SELECTOR = %x\n", Get_VMCS_HOST_FS_SELECTOR()); } - - -void Set_VMCS_HOST_GS_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_GS_SELECTOR,val); } -uint_t Get_VMCS_HOST_GS_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_GS_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_GS_SELECTOR() { PrintTrace("VMCS_HOST_GS_SELECTOR = %x\n", Get_VMCS_HOST_GS_SELECTOR()); } - - -void Set_VMCS_HOST_TR_SELECTOR(uint_t val) { VMCS_WRITE(VMCS_HOST_TR_SELECTOR,val); } -uint_t Get_VMCS_HOST_TR_SELECTOR() { uint_t rc; VMCS_READ(VMCS_HOST_TR_SELECTOR,&rc); return rc; } - void PrintTrace_VMCS_HOST_TR_SELECTOR() { PrintTrace("VMCS_HOST_TR_SELECTOR = %x\n", Get_VMCS_HOST_TR_SELECTOR()); } - - -void Set_IO_BITMAP_A_ADDR(uint_t val) { VMCS_WRITE(IO_BITMAP_A_ADDR,val); } -uint_t Get_IO_BITMAP_A_ADDR() { uint_t rc; VMCS_READ(IO_BITMAP_A_ADDR,&rc); return rc; } - void PrintTrace_IO_BITMAP_A_ADDR() { PrintTrace("IO_BITMAP_A_ADDR = %x\n", Get_IO_BITMAP_A_ADDR()); } - - -void Set_IO_BITMAP_A_ADDR_HIGH(uint_t val) { VMCS_WRITE(IO_BITMAP_A_ADDR_HIGH,val); } -uint_t Get_IO_BITMAP_A_ADDR_HIGH() { uint_t rc; VMCS_READ(IO_BITMAP_A_ADDR_HIGH,&rc); return rc; } - void PrintTrace_IO_BITMAP_A_ADDR_HIGH() { PrintTrace("IO_BITMAP_A_ADDR_HIGH = %x\n", Get_IO_BITMAP_A_ADDR_HIGH()); } - - -void Set_IO_BITMAP_B_ADDR(uint_t val) { VMCS_WRITE(IO_BITMAP_B_ADDR,val); } -uint_t Get_IO_BITMAP_B_ADDR() { uint_t rc; VMCS_READ(IO_BITMAP_B_ADDR,&rc); return rc; } - void PrintTrace_IO_BITMAP_B_ADDR() { PrintTrace("IO_BITMAP_B_ADDR = %x\n", Get_IO_BITMAP_B_ADDR()); } - - -void Set_IO_BITMAP_B_ADDR_HIGH(uint_t val) { VMCS_WRITE(IO_BITMAP_B_ADDR_HIGH,val); } -uint_t Get_IO_BITMAP_B_ADDR_HIGH() { uint_t rc; VMCS_READ(IO_BITMAP_B_ADDR_HIGH,&rc); return rc; } - void PrintTrace_IO_BITMAP_B_ADDR_HIGH() { PrintTrace("IO_BITMAP_B_ADDR_HIGH = %x\n", Get_IO_BITMAP_B_ADDR_HIGH()); } - - -void Set_MSR_BITMAPS(uint_t val) { VMCS_WRITE(MSR_BITMAPS,val); } -uint_t Get_MSR_BITMAPS() { uint_t rc; VMCS_READ(MSR_BITMAPS,&rc); return rc; } - void PrintTrace_MSR_BITMAPS() { PrintTrace("MSR_BITMAPS = %x\n", Get_MSR_BITMAPS()); } - - -void Set_MSR_BITMAPS_HIGH(uint_t val) { VMCS_WRITE(MSR_BITMAPS_HIGH,val); } -uint_t Get_MSR_BITMAPS_HIGH() { uint_t rc; VMCS_READ(MSR_BITMAPS_HIGH,&rc); return rc; } - void PrintTrace_MSR_BITMAPS_HIGH() { PrintTrace("MSR_BITMAPS_HIGH = %x\n", Get_MSR_BITMAPS_HIGH()); } - - -void Set_VM_EXIT_MSR_STORE_ADDR(uint_t val) { VMCS_WRITE(VM_EXIT_MSR_STORE_ADDR,val); } -uint_t Get_VM_EXIT_MSR_STORE_ADDR() { uint_t rc; VMCS_READ(VM_EXIT_MSR_STORE_ADDR,&rc); return rc; } - void PrintTrace_VM_EXIT_MSR_STORE_ADDR() { PrintTrace("VM_EXIT_MSR_STORE_ADDR = %x\n", Get_VM_EXIT_MSR_STORE_ADDR()); } - - -void Set_VM_EXIT_MSR_STORE_ADDR_HIGH(uint_t val) { VMCS_WRITE(VM_EXIT_MSR_STORE_ADDR_HIGH,val); } -uint_t Get_VM_EXIT_MSR_STORE_ADDR_HIGH() { uint_t rc; VMCS_READ(VM_EXIT_MSR_STORE_ADDR_HIGH,&rc); return rc; } - void PrintTrace_VM_EXIT_MSR_STORE_ADDR_HIGH() { PrintTrace("VM_EXIT_MSR_STORE_ADDR_HIGH = %x\n", Get_VM_EXIT_MSR_STORE_ADDR_HIGH()); } - - -void Set_VM_EXIT_MSR_LOAD_ADDR(uint_t val) { VMCS_WRITE(VM_EXIT_MSR_LOAD_ADDR,val); } -uint_t Get_VM_EXIT_MSR_LOAD_ADDR() { uint_t rc; VMCS_READ(VM_EXIT_MSR_LOAD_ADDR,&rc); return rc; } - void PrintTrace_VM_EXIT_MSR_LOAD_ADDR() { PrintTrace("VM_EXIT_MSR_LOAD_ADDR = %x\n", Get_VM_EXIT_MSR_LOAD_ADDR()); } - - -void Set_VM_EXIT_MSR_LOAD_ADDR_HIGH(uint_t val) { VMCS_WRITE(VM_EXIT_MSR_LOAD_ADDR_HIGH,val); } -uint_t Get_VM_EXIT_MSR_LOAD_ADDR_HIGH() { uint_t rc; VMCS_READ(VM_EXIT_MSR_LOAD_ADDR_HIGH,&rc); return rc; } - void PrintTrace_VM_EXIT_MSR_LOAD_ADDR_HIGH() { PrintTrace("VM_EXIT_MSR_LOAD_ADDR_HIGH = %x\n", Get_VM_EXIT_MSR_LOAD_ADDR_HIGH()); } - - -void Set_VM_ENTRY_MSR_LOAD_ADDR(uint_t val) { VMCS_WRITE(VM_ENTRY_MSR_LOAD_ADDR,val); } -uint_t Get_VM_ENTRY_MSR_LOAD_ADDR() { uint_t rc; VMCS_READ(VM_ENTRY_MSR_LOAD_ADDR,&rc); return rc; } - void PrintTrace_VM_ENTRY_MSR_LOAD_ADDR() { PrintTrace("VM_ENTRY_MSR_LOAD_ADDR = %x\n", Get_VM_ENTRY_MSR_LOAD_ADDR()); } - - -void Set_VM_ENTRY_MSR_LOAD_ADDR_HIGH(uint_t val) { VMCS_WRITE(VM_ENTRY_MSR_LOAD_ADDR_HIGH,val); } -uint_t Get_VM_ENTRY_MSR_LOAD_ADDR_HIGH() { uint_t rc; VMCS_READ(VM_ENTRY_MSR_LOAD_ADDR_HIGH,&rc); return rc; } - void PrintTrace_VM_ENTRY_MSR_LOAD_ADDR_HIGH() { PrintTrace("VM_ENTRY_MSR_LOAD_ADDR_HIGH = %x\n", Get_VM_ENTRY_MSR_LOAD_ADDR_HIGH()); } - - -void Set_VMCS_EXEC_PTR(uint_t val) { VMCS_WRITE(VMCS_EXEC_PTR,val); } -uint_t Get_VMCS_EXEC_PTR() { uint_t rc; VMCS_READ(VMCS_EXEC_PTR,&rc); return rc; } - void PrintTrace_VMCS_EXEC_PTR() { PrintTrace("VMCS_EXEC_PTR = %x\n", Get_VMCS_EXEC_PTR()); } - - -void Set_VMCS_EXEC_PTR_HIGH(uint_t val) { VMCS_WRITE(VMCS_EXEC_PTR_HIGH,val); } -uint_t Get_VMCS_EXEC_PTR_HIGH() { uint_t rc; VMCS_READ(VMCS_EXEC_PTR_HIGH,&rc); return rc; } - void PrintTrace_VMCS_EXEC_PTR_HIGH() { PrintTrace("VMCS_EXEC_PTR_HIGH = %x\n", Get_VMCS_EXEC_PTR_HIGH()); } - - -void Set_TSC_OFFSET(uint_t val) { VMCS_WRITE(TSC_OFFSET,val); } -uint_t Get_TSC_OFFSET() { uint_t rc; VMCS_READ(TSC_OFFSET,&rc); return rc; } - void PrintTrace_TSC_OFFSET() { PrintTrace("TSC_OFFSET = %x\n", Get_TSC_OFFSET()); } - - -void Set_TSC_OFFSET_HIGH(uint_t val) { VMCS_WRITE(TSC_OFFSET_HIGH,val); } -uint_t Get_TSC_OFFSET_HIGH() { uint_t rc; VMCS_READ(TSC_OFFSET_HIGH,&rc); return rc; } - void PrintTrace_TSC_OFFSET_HIGH() { PrintTrace("TSC_OFFSET_HIGH = %x\n", Get_TSC_OFFSET_HIGH()); } - - -void Set_VIRT_APIC_PAGE_ADDR(uint_t val) { VMCS_WRITE(VIRT_APIC_PAGE_ADDR,val); } -uint_t Get_VIRT_APIC_PAGE_ADDR() { uint_t rc; VMCS_READ(VIRT_APIC_PAGE_ADDR,&rc); return rc; } - void PrintTrace_VIRT_APIC_PAGE_ADDR() { PrintTrace("VIRT_APIC_PAGE_ADDR = %x\n", Get_VIRT_APIC_PAGE_ADDR()); } - - -void Set_VIRT_APIC_PAGE_ADDR_HIGH(uint_t val) { VMCS_WRITE(VIRT_APIC_PAGE_ADDR_HIGH,val); } -uint_t Get_VIRT_APIC_PAGE_ADDR_HIGH() { uint_t rc; VMCS_READ(VIRT_APIC_PAGE_ADDR_HIGH,&rc); return rc; } - void PrintTrace_VIRT_APIC_PAGE_ADDR_HIGH() { PrintTrace("VIRT_APIC_PAGE_ADDR_HIGH = %x\n", Get_VIRT_APIC_PAGE_ADDR_HIGH()); } - - -void Set_VMCS_LINK_PTR(uint_t val) { VMCS_WRITE(VMCS_LINK_PTR,val); } -uint_t Get_VMCS_LINK_PTR() { uint_t rc; VMCS_READ(VMCS_LINK_PTR,&rc); return rc; } - void PrintTrace_VMCS_LINK_PTR() { PrintTrace("VMCS_LINK_PTR = %x\n", Get_VMCS_LINK_PTR()); } - - -void Set_VMCS_LINK_PTR_HIGH(uint_t val) { VMCS_WRITE(VMCS_LINK_PTR_HIGH,val); } -uint_t Get_VMCS_LINK_PTR_HIGH() { uint_t rc; VMCS_READ(VMCS_LINK_PTR_HIGH,&rc); return rc; } - void PrintTrace_VMCS_LINK_PTR_HIGH() { PrintTrace("VMCS_LINK_PTR_HIGH = %x\n", Get_VMCS_LINK_PTR_HIGH()); } - - -void Set_GUEST_IA32_DEBUGCTL(uint_t val) { VMCS_WRITE(GUEST_IA32_DEBUGCTL,val); } -uint_t Get_GUEST_IA32_DEBUGCTL() { uint_t rc; VMCS_READ(GUEST_IA32_DEBUGCTL,&rc); return rc; } - void PrintTrace_GUEST_IA32_DEBUGCTL() { PrintTrace("GUEST_IA32_DEBUGCTL = %x\n", Get_GUEST_IA32_DEBUGCTL()); } - - -void Set_GUEST_IA32_DEBUGCTL_HIGH(uint_t val) { VMCS_WRITE(GUEST_IA32_DEBUGCTL_HIGH,val); } -uint_t Get_GUEST_IA32_DEBUGCTL_HIGH() { uint_t rc; VMCS_READ(GUEST_IA32_DEBUGCTL_HIGH,&rc); return rc; } - void PrintTrace_GUEST_IA32_DEBUGCTL_HIGH() { PrintTrace("GUEST_IA32_DEBUGCTL_HIGH = %x\n", Get_GUEST_IA32_DEBUGCTL_HIGH()); } - - -void Set_PIN_VM_EXEC_CTRLS(uint_t val) { VMCS_WRITE(PIN_VM_EXEC_CTRLS,val); } -uint_t Get_PIN_VM_EXEC_CTRLS() { uint_t rc; VMCS_READ(PIN_VM_EXEC_CTRLS,&rc); return rc; } - void PrintTrace_PIN_VM_EXEC_CTRLS() { PrintTrace("PIN_VM_EXEC_CTRLS = %x\n", Get_PIN_VM_EXEC_CTRLS()); } - - -void Set_PROC_VM_EXEC_CTRLS(uint_t val) { VMCS_WRITE(PROC_VM_EXEC_CTRLS,val); } -uint_t Get_PROC_VM_EXEC_CTRLS() { uint_t rc; VMCS_READ(PROC_VM_EXEC_CTRLS,&rc); return rc; } - void PrintTrace_PROC_VM_EXEC_CTRLS() { PrintTrace("PROC_VM_EXEC_CTRLS = %x\n", Get_PROC_VM_EXEC_CTRLS()); } - - -void Set_EXCEPTION_BITMAP(uint_t val) { VMCS_WRITE(EXCEPTION_BITMAP,val); } -uint_t Get_EXCEPTION_BITMAP() { uint_t rc; VMCS_READ(EXCEPTION_BITMAP,&rc); return rc; } - void PrintTrace_EXCEPTION_BITMAP() { PrintTrace("EXCEPTION_BITMAP = %x\n", Get_EXCEPTION_BITMAP()); } - - -void Set_PAGE_FAULT_ERROR_MASK(uint_t val) { VMCS_WRITE(PAGE_FAULT_ERROR_MASK,val); } -uint_t Get_PAGE_FAULT_ERROR_MASK() { uint_t rc; VMCS_READ(PAGE_FAULT_ERROR_MASK,&rc); return rc; } - void PrintTrace_PAGE_FAULT_ERROR_MASK() { PrintTrace("PAGE_FAULT_ERROR_MASK = %x\n", Get_PAGE_FAULT_ERROR_MASK()); } - - -void Set_PAGE_FAULT_ERROR_MATCH(uint_t val) { VMCS_WRITE(PAGE_FAULT_ERROR_MATCH,val); } -uint_t Get_PAGE_FAULT_ERROR_MATCH() { uint_t rc; VMCS_READ(PAGE_FAULT_ERROR_MATCH,&rc); return rc; } - void PrintTrace_PAGE_FAULT_ERROR_MATCH() { PrintTrace("PAGE_FAULT_ERROR_MATCH = %x\n", Get_PAGE_FAULT_ERROR_MATCH()); } - - -void Set_CR3_TARGET_COUNT(uint_t val) { VMCS_WRITE(CR3_TARGET_COUNT,val); } -uint_t Get_CR3_TARGET_COUNT() { uint_t rc; VMCS_READ(CR3_TARGET_COUNT,&rc); return rc; } - void PrintTrace_CR3_TARGET_COUNT() { PrintTrace("CR3_TARGET_COUNT = %x\n", Get_CR3_TARGET_COUNT()); } - - -void Set_VM_EXIT_CTRLS(uint_t val) { VMCS_WRITE(VM_EXIT_CTRLS,val); } -uint_t Get_VM_EXIT_CTRLS() { uint_t rc; VMCS_READ(VM_EXIT_CTRLS,&rc); return rc; } - void PrintTrace_VM_EXIT_CTRLS() { PrintTrace("VM_EXIT_CTRLS = %x\n", Get_VM_EXIT_CTRLS()); } - - -void Set_VM_EXIT_MSR_STORE_COUNT(uint_t val) { VMCS_WRITE(VM_EXIT_MSR_STORE_COUNT,val); } -uint_t Get_VM_EXIT_MSR_STORE_COUNT() { uint_t rc; VMCS_READ(VM_EXIT_MSR_STORE_COUNT,&rc); return rc; } - void PrintTrace_VM_EXIT_MSR_STORE_COUNT() { PrintTrace("VM_EXIT_MSR_STORE_COUNT = %x\n", Get_VM_EXIT_MSR_STORE_COUNT()); } - - -void Set_VM_EXIT_MSR_LOAD_COUNT(uint_t val) { VMCS_WRITE(VM_EXIT_MSR_LOAD_COUNT,val); } -uint_t Get_VM_EXIT_MSR_LOAD_COUNT() { uint_t rc; VMCS_READ(VM_EXIT_MSR_LOAD_COUNT,&rc); return rc; } - void PrintTrace_VM_EXIT_MSR_LOAD_COUNT() { PrintTrace("VM_EXIT_MSR_LOAD_COUNT = %x\n", Get_VM_EXIT_MSR_LOAD_COUNT()); } - - -void Set_VM_ENTRY_CTRLS(uint_t val) { VMCS_WRITE(VM_ENTRY_CTRLS,val); } -uint_t Get_VM_ENTRY_CTRLS() { uint_t rc; VMCS_READ(VM_ENTRY_CTRLS,&rc); return rc; } - void PrintTrace_VM_ENTRY_CTRLS() { PrintTrace("VM_ENTRY_CTRLS = %x\n", Get_VM_ENTRY_CTRLS()); } - - -void Set_VM_ENTRY_MSR_LOAD_COUNT(uint_t val) { VMCS_WRITE(VM_ENTRY_MSR_LOAD_COUNT,val); } -uint_t Get_VM_ENTRY_MSR_LOAD_COUNT() { uint_t rc; VMCS_READ(VM_ENTRY_MSR_LOAD_COUNT,&rc); return rc; } - void PrintTrace_VM_ENTRY_MSR_LOAD_COUNT() { PrintTrace("VM_ENTRY_MSR_LOAD_COUNT = %x\n", Get_VM_ENTRY_MSR_LOAD_COUNT()); } - - -void Set_VM_ENTRY_INT_INFO_FIELD(uint_t val) { VMCS_WRITE(VM_ENTRY_INT_INFO_FIELD,val); } -uint_t Get_VM_ENTRY_INT_INFO_FIELD() { uint_t rc; VMCS_READ(VM_ENTRY_INT_INFO_FIELD,&rc); return rc; } - void PrintTrace_VM_ENTRY_INT_INFO_FIELD() { PrintTrace("VM_ENTRY_INT_INFO_FIELD = %x\n", Get_VM_ENTRY_INT_INFO_FIELD()); } - - -void Set_VM_ENTRY_EXCEPTION_ERROR(uint_t val) { VMCS_WRITE(VM_ENTRY_EXCEPTION_ERROR,val); } -uint_t Get_VM_ENTRY_EXCEPTION_ERROR() { uint_t rc; VMCS_READ(VM_ENTRY_EXCEPTION_ERROR,&rc); return rc; } - void PrintTrace_VM_ENTRY_EXCEPTION_ERROR() { PrintTrace("VM_ENTRY_EXCEPTION_ERROR = %x\n", Get_VM_ENTRY_EXCEPTION_ERROR()); } - - -void Set_VM_ENTRY_INSTR_LENGTH(uint_t val) { VMCS_WRITE(VM_ENTRY_INSTR_LENGTH,val); } -uint_t Get_VM_ENTRY_INSTR_LENGTH() { uint_t rc; VMCS_READ(VM_ENTRY_INSTR_LENGTH,&rc); return rc; } - void PrintTrace_VM_ENTRY_INSTR_LENGTH() { PrintTrace("VM_ENTRY_INSTR_LENGTH = %x\n", Get_VM_ENTRY_INSTR_LENGTH()); } - - -void Set_TPR_THRESHOLD(uint_t val) { VMCS_WRITE(TPR_THRESHOLD,val); } -uint_t Get_TPR_THRESHOLD() { uint_t rc; VMCS_READ(TPR_THRESHOLD,&rc); return rc; } - void PrintTrace_TPR_THRESHOLD() { PrintTrace("TPR_THRESHOLD = %x\n", Get_TPR_THRESHOLD()); } - - -void Set_VM_INSTR_ERROR(uint_t val) { VMCS_WRITE(VM_INSTR_ERROR,val); } -uint_t Get_VM_INSTR_ERROR() { uint_t rc; VMCS_READ(VM_INSTR_ERROR,&rc); return rc; } - void PrintTrace_VM_INSTR_ERROR() { PrintTrace("VM_INSTR_ERROR = %x\n", Get_VM_INSTR_ERROR()); } - - -void Set_EXIT_REASON(uint_t val) { VMCS_WRITE(EXIT_REASON,val); } -uint_t Get_EXIT_REASON() { uint_t rc; VMCS_READ(EXIT_REASON,&rc); return rc; } - void PrintTrace_EXIT_REASON() { PrintTrace("EXIT_REASON = %x\n", Get_EXIT_REASON()); } - - -void Set_VM_EXIT_INT_INFO(uint_t val) { VMCS_WRITE(VM_EXIT_INT_INFO,val); } -uint_t Get_VM_EXIT_INT_INFO() { uint_t rc; VMCS_READ(VM_EXIT_INT_INFO,&rc); return rc; } - void PrintTrace_VM_EXIT_INT_INFO() { PrintTrace("VM_EXIT_INT_INFO = %x\n", Get_VM_EXIT_INT_INFO()); } - - -void Set_VM_EXIT_INT_ERROR(uint_t val) { VMCS_WRITE(VM_EXIT_INT_ERROR,val); } -uint_t Get_VM_EXIT_INT_ERROR() { uint_t rc; VMCS_READ(VM_EXIT_INT_ERROR,&rc); return rc; } - void PrintTrace_VM_EXIT_INT_ERROR() { PrintTrace("VM_EXIT_INT_ERROR = %x\n", Get_VM_EXIT_INT_ERROR()); } - - -void Set_IDT_VECTOR_INFO(uint_t val) { VMCS_WRITE(IDT_VECTOR_INFO,val); } -uint_t Get_IDT_VECTOR_INFO() { uint_t rc; VMCS_READ(IDT_VECTOR_INFO,&rc); return rc; } - void PrintTrace_IDT_VECTOR_INFO() { PrintTrace("IDT_VECTOR_INFO = %x\n", Get_IDT_VECTOR_INFO()); } - - -void Set_IDT_VECTOR_ERROR(uint_t val) { VMCS_WRITE(IDT_VECTOR_ERROR,val); } -uint_t Get_IDT_VECTOR_ERROR() { uint_t rc; VMCS_READ(IDT_VECTOR_ERROR,&rc); return rc; } - void PrintTrace_IDT_VECTOR_ERROR() { PrintTrace("IDT_VECTOR_ERROR = %x\n", Get_IDT_VECTOR_ERROR()); } - - -void Set_VM_EXIT_INSTR_LENGTH(uint_t val) { VMCS_WRITE(VM_EXIT_INSTR_LENGTH,val); } -uint_t Get_VM_EXIT_INSTR_LENGTH() { uint_t rc; VMCS_READ(VM_EXIT_INSTR_LENGTH,&rc); return rc; } - void PrintTrace_VM_EXIT_INSTR_LENGTH() { PrintTrace("VM_EXIT_INSTR_LENGTH = %x\n", Get_VM_EXIT_INSTR_LENGTH()); } - - -void Set_VMX_INSTR_INFO(uint_t val) { VMCS_WRITE(VMX_INSTR_INFO,val); } -uint_t Get_VMX_INSTR_INFO() { uint_t rc; VMCS_READ(VMX_INSTR_INFO,&rc); return rc; } - void PrintTrace_VMX_INSTR_INFO() { PrintTrace("VMX_INSTR_INFO = %x\n", Get_VMX_INSTR_INFO()); } - - -void Set_GUEST_ES_LIMIT(uint_t val) { VMCS_WRITE(GUEST_ES_LIMIT,val); } -uint_t Get_GUEST_ES_LIMIT() { uint_t rc; VMCS_READ(GUEST_ES_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_ES_LIMIT() { PrintTrace("GUEST_ES_LIMIT = %x\n", Get_GUEST_ES_LIMIT()); } - - -void Set_GUEST_CS_LIMIT(uint_t val) { VMCS_WRITE(GUEST_CS_LIMIT,val); } -uint_t Get_GUEST_CS_LIMIT() { uint_t rc; VMCS_READ(GUEST_CS_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_CS_LIMIT() { PrintTrace("GUEST_CS_LIMIT = %x\n", Get_GUEST_CS_LIMIT()); } - - -void Set_GUEST_SS_LIMIT(uint_t val) { VMCS_WRITE(GUEST_SS_LIMIT,val); } -uint_t Get_GUEST_SS_LIMIT() { uint_t rc; VMCS_READ(GUEST_SS_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_SS_LIMIT() { PrintTrace("GUEST_SS_LIMIT = %x\n", Get_GUEST_SS_LIMIT()); } - - -void Set_GUEST_DS_LIMIT(uint_t val) { VMCS_WRITE(GUEST_DS_LIMIT,val); } -uint_t Get_GUEST_DS_LIMIT() { uint_t rc; VMCS_READ(GUEST_DS_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_DS_LIMIT() { PrintTrace("GUEST_DS_LIMIT = %x\n", Get_GUEST_DS_LIMIT()); } - - -void Set_GUEST_FS_LIMIT(uint_t val) { VMCS_WRITE(GUEST_FS_LIMIT,val); } -uint_t Get_GUEST_FS_LIMIT() { uint_t rc; VMCS_READ(GUEST_FS_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_FS_LIMIT() { PrintTrace("GUEST_FS_LIMIT = %x\n", Get_GUEST_FS_LIMIT()); } - - -void Set_GUEST_GS_LIMIT(uint_t val) { VMCS_WRITE(GUEST_GS_LIMIT,val); } -uint_t Get_GUEST_GS_LIMIT() { uint_t rc; VMCS_READ(GUEST_GS_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_GS_LIMIT() { PrintTrace("GUEST_GS_LIMIT = %x\n", Get_GUEST_GS_LIMIT()); } - - -void Set_GUEST_LDTR_LIMIT(uint_t val) { VMCS_WRITE(GUEST_LDTR_LIMIT,val); } -uint_t Get_GUEST_LDTR_LIMIT() { uint_t rc; VMCS_READ(GUEST_LDTR_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_LDTR_LIMIT() { PrintTrace("GUEST_LDTR_LIMIT = %x\n", Get_GUEST_LDTR_LIMIT()); } - - -void Set_GUEST_TR_LIMIT(uint_t val) { VMCS_WRITE(GUEST_TR_LIMIT,val); } -uint_t Get_GUEST_TR_LIMIT() { uint_t rc; VMCS_READ(GUEST_TR_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_TR_LIMIT() { PrintTrace("GUEST_TR_LIMIT = %x\n", Get_GUEST_TR_LIMIT()); } - - -void Set_GUEST_GDTR_LIMIT(uint_t val) { VMCS_WRITE(GUEST_GDTR_LIMIT,val); } -uint_t Get_GUEST_GDTR_LIMIT() { uint_t rc; VMCS_READ(GUEST_GDTR_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_GDTR_LIMIT() { PrintTrace("GUEST_GDTR_LIMIT = %x\n", Get_GUEST_GDTR_LIMIT()); } - - -void Set_GUEST_IDTR_LIMIT(uint_t val) { VMCS_WRITE(GUEST_IDTR_LIMIT,val); } -uint_t Get_GUEST_IDTR_LIMIT() { uint_t rc; VMCS_READ(GUEST_IDTR_LIMIT,&rc); return rc; } - void PrintTrace_GUEST_IDTR_LIMIT() { PrintTrace("GUEST_IDTR_LIMIT = %x\n", Get_GUEST_IDTR_LIMIT()); } - - -void Set_GUEST_ES_ACCESS(uint_t val) { VMCS_WRITE(GUEST_ES_ACCESS,val); } -uint_t Get_GUEST_ES_ACCESS() { uint_t rc; VMCS_READ(GUEST_ES_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_ES_ACCESS() { PrintTrace("GUEST_ES_ACCESS = %x\n", Get_GUEST_ES_ACCESS()); } - - -void Set_GUEST_CS_ACCESS(uint_t val) { VMCS_WRITE(GUEST_CS_ACCESS,val); } -uint_t Get_GUEST_CS_ACCESS() { uint_t rc; VMCS_READ(GUEST_CS_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_CS_ACCESS() { PrintTrace("GUEST_CS_ACCESS = %x\n", Get_GUEST_CS_ACCESS()); } - - -void Set_GUEST_SS_ACCESS(uint_t val) { VMCS_WRITE(GUEST_SS_ACCESS,val); } -uint_t Get_GUEST_SS_ACCESS() { uint_t rc; VMCS_READ(GUEST_SS_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_SS_ACCESS() { PrintTrace("GUEST_SS_ACCESS = %x\n", Get_GUEST_SS_ACCESS()); } - - -void Set_GUEST_DS_ACCESS(uint_t val) { VMCS_WRITE(GUEST_DS_ACCESS,val); } -uint_t Get_GUEST_DS_ACCESS() { uint_t rc; VMCS_READ(GUEST_DS_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_DS_ACCESS() { PrintTrace("GUEST_DS_ACCESS = %x\n", Get_GUEST_DS_ACCESS()); } - - -void Set_GUEST_FS_ACCESS(uint_t val) { VMCS_WRITE(GUEST_FS_ACCESS,val); } -uint_t Get_GUEST_FS_ACCESS() { uint_t rc; VMCS_READ(GUEST_FS_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_FS_ACCESS() { PrintTrace("GUEST_FS_ACCESS = %x\n", Get_GUEST_FS_ACCESS()); } - - -void Set_GUEST_GS_ACCESS(uint_t val) { VMCS_WRITE(GUEST_GS_ACCESS,val); } -uint_t Get_GUEST_GS_ACCESS() { uint_t rc; VMCS_READ(GUEST_GS_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_GS_ACCESS() { PrintTrace("GUEST_GS_ACCESS = %x\n", Get_GUEST_GS_ACCESS()); } - - -void Set_GUEST_LDTR_ACCESS(uint_t val) { VMCS_WRITE(GUEST_LDTR_ACCESS,val); } -uint_t Get_GUEST_LDTR_ACCESS() { uint_t rc; VMCS_READ(GUEST_LDTR_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_LDTR_ACCESS() { PrintTrace("GUEST_LDTR_ACCESS = %x\n", Get_GUEST_LDTR_ACCESS()); } - - -void Set_GUEST_TR_ACCESS(uint_t val) { VMCS_WRITE(GUEST_TR_ACCESS,val); } -uint_t Get_GUEST_TR_ACCESS() { uint_t rc; VMCS_READ(GUEST_TR_ACCESS,&rc); return rc; } - void PrintTrace_GUEST_TR_ACCESS() { PrintTrace("GUEST_TR_ACCESS = %x\n", Get_GUEST_TR_ACCESS()); } - - -void Set_GUEST_INT_STATE(uint_t val) { VMCS_WRITE(GUEST_INT_STATE,val); } -uint_t Get_GUEST_INT_STATE() { uint_t rc; VMCS_READ(GUEST_INT_STATE,&rc); return rc; } - void PrintTrace_GUEST_INT_STATE() { PrintTrace("GUEST_INT_STATE = %x\n", Get_GUEST_INT_STATE()); } - - -void Set_GUEST_ACTIVITY_STATE(uint_t val) { VMCS_WRITE(GUEST_ACTIVITY_STATE,val); } -uint_t Get_GUEST_ACTIVITY_STATE() { uint_t rc; VMCS_READ(GUEST_ACTIVITY_STATE,&rc); return rc; } - void PrintTrace_GUEST_ACTIVITY_STATE() { PrintTrace("GUEST_ACTIVITY_STATE = %x\n", Get_GUEST_ACTIVITY_STATE()); } - - -void Set_GUEST_SMBASE(uint_t val) { VMCS_WRITE(GUEST_SMBASE,val); } -uint_t Get_GUEST_SMBASE() { uint_t rc; VMCS_READ(GUEST_SMBASE,&rc); return rc; } - void PrintTrace_GUEST_SMBASE() { PrintTrace("GUEST_SMBASE = %x\n", Get_GUEST_SMBASE()); } - - -void Set_GUEST_IA32_SYSENTER_CS(uint_t val) { VMCS_WRITE(GUEST_IA32_SYSENTER_CS,val); } -uint_t Get_GUEST_IA32_SYSENTER_CS() { uint_t rc; VMCS_READ(GUEST_IA32_SYSENTER_CS,&rc); return rc; } - void PrintTrace_GUEST_IA32_SYSENTER_CS() { PrintTrace("GUEST_IA32_SYSENTER_CS = %x\n", Get_GUEST_IA32_SYSENTER_CS()); } - - -void Set_HOST_IA32_SYSENTER_CS(uint_t val) { VMCS_WRITE(HOST_IA32_SYSENTER_CS,val); } -uint_t Get_HOST_IA32_SYSENTER_CS() { uint_t rc; VMCS_READ(HOST_IA32_SYSENTER_CS,&rc); return rc; } - void PrintTrace_HOST_IA32_SYSENTER_CS() { PrintTrace("HOST_IA32_SYSENTER_CS = %x\n", Get_HOST_IA32_SYSENTER_CS()); } - - -void Set_CR0_GUEST_HOST_MASK(uint_t val) { VMCS_WRITE(CR0_GUEST_HOST_MASK,val); } -uint_t Get_CR0_GUEST_HOST_MASK() { uint_t rc; VMCS_READ(CR0_GUEST_HOST_MASK,&rc); return rc; } - void PrintTrace_CR0_GUEST_HOST_MASK() { PrintTrace("CR0_GUEST_HOST_MASK = %x\n", Get_CR0_GUEST_HOST_MASK()); } - - -void Set_CR4_GUEST_HOST_MASK(uint_t val) { VMCS_WRITE(CR4_GUEST_HOST_MASK,val); } -uint_t Get_CR4_GUEST_HOST_MASK() { uint_t rc; VMCS_READ(CR4_GUEST_HOST_MASK,&rc); return rc; } - void PrintTrace_CR4_GUEST_HOST_MASK() { PrintTrace("CR4_GUEST_HOST_MASK = %x\n", Get_CR4_GUEST_HOST_MASK()); } - - -void Set_CR0_READ_SHADOW(uint_t val) { VMCS_WRITE(CR0_READ_SHADOW,val); } -uint_t Get_CR0_READ_SHADOW() { uint_t rc; VMCS_READ(CR0_READ_SHADOW,&rc); return rc; } - void PrintTrace_CR0_READ_SHADOW() { PrintTrace("CR0_READ_SHADOW = %x\n", Get_CR0_READ_SHADOW()); } - - -void Set_CR4_READ_SHADOW(uint_t val) { VMCS_WRITE(CR4_READ_SHADOW,val); } -uint_t Get_CR4_READ_SHADOW() { uint_t rc; VMCS_READ(CR4_READ_SHADOW,&rc); return rc; } - void PrintTrace_CR4_READ_SHADOW() { PrintTrace("CR4_READ_SHADOW = %x\n", Get_CR4_READ_SHADOW()); } - - -void Set_CR3_TARGET_VALUE_0(uint_t val) { VMCS_WRITE(CR3_TARGET_VALUE_0,val); } -uint_t Get_CR3_TARGET_VALUE_0() { uint_t rc; VMCS_READ(CR3_TARGET_VALUE_0,&rc); return rc; } - void PrintTrace_CR3_TARGET_VALUE_0() { PrintTrace("CR3_TARGET_VALUE_0 = %x\n", Get_CR3_TARGET_VALUE_0()); } - - -void Set_CR3_TARGET_VALUE_1(uint_t val) { VMCS_WRITE(CR3_TARGET_VALUE_1,val); } -uint_t Get_CR3_TARGET_VALUE_1() { uint_t rc; VMCS_READ(CR3_TARGET_VALUE_1,&rc); return rc; } - void PrintTrace_CR3_TARGET_VALUE_1() { PrintTrace("CR3_TARGET_VALUE_1 = %x\n", Get_CR3_TARGET_VALUE_1()); } - - -void Set_CR3_TARGET_VALUE_2(uint_t val) { VMCS_WRITE(CR3_TARGET_VALUE_2,val); } -uint_t Get_CR3_TARGET_VALUE_2() { uint_t rc; VMCS_READ(CR3_TARGET_VALUE_2,&rc); return rc; } - void PrintTrace_CR3_TARGET_VALUE_2() { PrintTrace("CR3_TARGET_VALUE_2 = %x\n", Get_CR3_TARGET_VALUE_2()); } - - -void Set_CR3_TARGET_VALUE_3(uint_t val) { VMCS_WRITE(CR3_TARGET_VALUE_3,val); } -uint_t Get_CR3_TARGET_VALUE_3() { uint_t rc; VMCS_READ(CR3_TARGET_VALUE_3,&rc); return rc; } - void PrintTrace_CR3_TARGET_VALUE_3() { PrintTrace("CR3_TARGET_VALUE_3 = %x\n", Get_CR3_TARGET_VALUE_3()); } - - -void Set_EXIT_QUALIFICATION(uint_t val) { VMCS_WRITE(EXIT_QUALIFICATION,val); } -uint_t Get_EXIT_QUALIFICATION() { uint_t rc; VMCS_READ(EXIT_QUALIFICATION,&rc); return rc; } - void PrintTrace_EXIT_QUALIFICATION() { PrintTrace("EXIT_QUALIFICATION = %x\n", Get_EXIT_QUALIFICATION()); } - - -void Set_IO_RCX(uint_t val) { VMCS_WRITE(IO_RCX,val); } -uint_t Get_IO_RCX() { uint_t rc; VMCS_READ(IO_RCX,&rc); return rc; } - void PrintTrace_IO_RCX() { PrintTrace("IO_RCX = %x\n", Get_IO_RCX()); } - - -void Set_IO_RSI(uint_t val) { VMCS_WRITE(IO_RSI,val); } -uint_t Get_IO_RSI() { uint_t rc; VMCS_READ(IO_RSI,&rc); return rc; } - void PrintTrace_IO_RSI() { PrintTrace("IO_RSI = %x\n", Get_IO_RSI()); } - - -void Set_IO_RDI(uint_t val) { VMCS_WRITE(IO_RDI,val); } -uint_t Get_IO_RDI() { uint_t rc; VMCS_READ(IO_RDI,&rc); return rc; } - void PrintTrace_IO_RDI() { PrintTrace("IO_RDI = %x\n", Get_IO_RDI()); } - - -void Set_IO_RIP(uint_t val) { VMCS_WRITE(IO_RIP,val); } -uint_t Get_IO_RIP() { uint_t rc; VMCS_READ(IO_RIP,&rc); return rc; } - void PrintTrace_IO_RIP() { PrintTrace("IO_RIP = %x\n", Get_IO_RIP()); } - - -void Set_GUEST_LINEAR_ADDR(uint_t val) { VMCS_WRITE(GUEST_LINEAR_ADDR,val); } -uint_t Get_GUEST_LINEAR_ADDR() { uint_t rc; VMCS_READ(GUEST_LINEAR_ADDR,&rc); return rc; } - void PrintTrace_GUEST_LINEAR_ADDR() { PrintTrace("GUEST_LINEAR_ADDR = %x\n", Get_GUEST_LINEAR_ADDR()); } - - -void Set_GUEST_CR0(uint_t val) { VMCS_WRITE(GUEST_CR0,val); } -uint_t Get_GUEST_CR0() { uint_t rc; VMCS_READ(GUEST_CR0,&rc); return rc; } - void PrintTrace_GUEST_CR0() { PrintTrace("GUEST_CR0 = %x\n", Get_GUEST_CR0()); } - - -void Set_GUEST_CR3(uint_t val) { VMCS_WRITE(GUEST_CR3,val); } -uint_t Get_GUEST_CR3() { uint_t rc; VMCS_READ(GUEST_CR3,&rc); return rc; } - void PrintTrace_GUEST_CR3() { PrintTrace("GUEST_CR3 = %x\n", Get_GUEST_CR3()); } - - -void Set_GUEST_CR4(uint_t val) { VMCS_WRITE(GUEST_CR4,val); } -uint_t Get_GUEST_CR4() { uint_t rc; VMCS_READ(GUEST_CR4,&rc); return rc; } - void PrintTrace_GUEST_CR4() { PrintTrace("GUEST_CR4 = %x\n", Get_GUEST_CR4()); } - - -void Set_GUEST_ES_BASE(uint_t val) { VMCS_WRITE(GUEST_ES_BASE,val); } -uint_t Get_GUEST_ES_BASE() { uint_t rc; VMCS_READ(GUEST_ES_BASE,&rc); return rc; } - void PrintTrace_GUEST_ES_BASE() { PrintTrace("GUEST_ES_BASE = %x\n", Get_GUEST_ES_BASE()); } - - -void Set_GUEST_CS_BASE(uint_t val) { VMCS_WRITE(GUEST_CS_BASE,val); } -uint_t Get_GUEST_CS_BASE() { uint_t rc; VMCS_READ(GUEST_CS_BASE,&rc); return rc; } - void PrintTrace_GUEST_CS_BASE() { PrintTrace("GUEST_CS_BASE = %x\n", Get_GUEST_CS_BASE()); } - - -void Set_GUEST_SS_BASE(uint_t val) { VMCS_WRITE(GUEST_SS_BASE,val); } -uint_t Get_GUEST_SS_BASE() { uint_t rc; VMCS_READ(GUEST_SS_BASE,&rc); return rc; } - void PrintTrace_GUEST_SS_BASE() { PrintTrace("GUEST_SS_BASE = %x\n", Get_GUEST_SS_BASE()); } - - -void Set_GUEST_DS_BASE(uint_t val) { VMCS_WRITE(GUEST_DS_BASE,val); } -uint_t Get_GUEST_DS_BASE() { uint_t rc; VMCS_READ(GUEST_DS_BASE,&rc); return rc; } - void PrintTrace_GUEST_DS_BASE() { PrintTrace("GUEST_DS_BASE = %x\n", Get_GUEST_DS_BASE()); } - - -void Set_GUEST_FS_BASE(uint_t val) { VMCS_WRITE(GUEST_FS_BASE,val); } -uint_t Get_GUEST_FS_BASE() { uint_t rc; VMCS_READ(GUEST_FS_BASE,&rc); return rc; } - void PrintTrace_GUEST_FS_BASE() { PrintTrace("GUEST_FS_BASE = %x\n", Get_GUEST_FS_BASE()); } - - -void Set_GUEST_GS_BASE(uint_t val) { VMCS_WRITE(GUEST_GS_BASE,val); } -uint_t Get_GUEST_GS_BASE() { uint_t rc; VMCS_READ(GUEST_GS_BASE,&rc); return rc; } - void PrintTrace_GUEST_GS_BASE() { PrintTrace("GUEST_GS_BASE = %x\n", Get_GUEST_GS_BASE()); } - - -void Set_GUEST_LDTR_BASE(uint_t val) { VMCS_WRITE(GUEST_LDTR_BASE,val); } -uint_t Get_GUEST_LDTR_BASE() { uint_t rc; VMCS_READ(GUEST_LDTR_BASE,&rc); return rc; } - void PrintTrace_GUEST_LDTR_BASE() { PrintTrace("GUEST_LDTR_BASE = %x\n", Get_GUEST_LDTR_BASE()); } - - -void Set_GUEST_TR_BASE(uint_t val) { VMCS_WRITE(GUEST_TR_BASE,val); } -uint_t Get_GUEST_TR_BASE() { uint_t rc; VMCS_READ(GUEST_TR_BASE,&rc); return rc; } - void PrintTrace_GUEST_TR_BASE() { PrintTrace("GUEST_TR_BASE = %x\n", Get_GUEST_TR_BASE()); } - - -void Set_GUEST_GDTR_BASE(uint_t val) { VMCS_WRITE(GUEST_GDTR_BASE,val); } -uint_t Get_GUEST_GDTR_BASE() { uint_t rc; VMCS_READ(GUEST_GDTR_BASE,&rc); return rc; } - void PrintTrace_GUEST_GDTR_BASE() { PrintTrace("GUEST_GDTR_BASE = %x\n", Get_GUEST_GDTR_BASE()); } - - -void Set_GUEST_IDTR_BASE(uint_t val) { VMCS_WRITE(GUEST_IDTR_BASE,val); } -uint_t Get_GUEST_IDTR_BASE() { uint_t rc; VMCS_READ(GUEST_IDTR_BASE,&rc); return rc; } - void PrintTrace_GUEST_IDTR_BASE() { PrintTrace("GUEST_IDTR_BASE = %x\n", Get_GUEST_IDTR_BASE()); } - - -void Set_GUEST_DR7(uint_t val) { VMCS_WRITE(GUEST_DR7,val); } -uint_t Get_GUEST_DR7() { uint_t rc; VMCS_READ(GUEST_DR7,&rc); return rc; } - void PrintTrace_GUEST_DR7() { PrintTrace("GUEST_DR7 = %x\n", Get_GUEST_DR7()); } - - -void Set_GUEST_RSP(uint_t val) { VMCS_WRITE(GUEST_RSP,val); } -uint_t Get_GUEST_RSP() { uint_t rc; VMCS_READ(GUEST_RSP,&rc); return rc; } - void PrintTrace_GUEST_RSP() { PrintTrace("GUEST_RSP = %x\n", Get_GUEST_RSP()); } - - -void Set_GUEST_RIP(uint_t val) { VMCS_WRITE(GUEST_RIP,val); } -uint_t Get_GUEST_RIP() { uint_t rc; VMCS_READ(GUEST_RIP,&rc); return rc; } - void PrintTrace_GUEST_RIP() { PrintTrace("GUEST_RIP = %x\n", Get_GUEST_RIP()); } - - -void Set_GUEST_RFLAGS(uint_t val) { VMCS_WRITE(GUEST_RFLAGS,val); } -uint_t Get_GUEST_RFLAGS() { uint_t rc; VMCS_READ(GUEST_RFLAGS,&rc); return rc; } - void PrintTrace_GUEST_RFLAGS() { PrintTrace("GUEST_RFLAGS = %x\n", Get_GUEST_RFLAGS()); } - - -void Set_GUEST_PENDING_DEBUG_EXCS(uint_t val) { VMCS_WRITE(GUEST_PENDING_DEBUG_EXCS,val); } -uint_t Get_GUEST_PENDING_DEBUG_EXCS() { uint_t rc; VMCS_READ(GUEST_PENDING_DEBUG_EXCS,&rc); return rc; } - void PrintTrace_GUEST_PENDING_DEBUG_EXCS() { PrintTrace("GUEST_PENDING_DEBUG_EXCS = %x\n", Get_GUEST_PENDING_DEBUG_EXCS()); } - - -void Set_GUEST_IA32_SYSENTER_ESP(uint_t val) { VMCS_WRITE(GUEST_IA32_SYSENTER_ESP,val); } -uint_t Get_GUEST_IA32_SYSENTER_ESP() { uint_t rc; VMCS_READ(GUEST_IA32_SYSENTER_ESP,&rc); return rc; } - void PrintTrace_GUEST_IA32_SYSENTER_ESP() { PrintTrace("GUEST_IA32_SYSENTER_ESP = %x\n", Get_GUEST_IA32_SYSENTER_ESP()); } - - -void Set_GUEST_IA32_SYSENTER_EIP(uint_t val) { VMCS_WRITE(GUEST_IA32_SYSENTER_EIP,val); } -uint_t Get_GUEST_IA32_SYSENTER_EIP() { uint_t rc; VMCS_READ(GUEST_IA32_SYSENTER_EIP,&rc); return rc; } - void PrintTrace_GUEST_IA32_SYSENTER_EIP() { PrintTrace("GUEST_IA32_SYSENTER_EIP = %x\n", Get_GUEST_IA32_SYSENTER_EIP()); } - - -void Set_HOST_CR0(uint_t val) { VMCS_WRITE(HOST_CR0,val); } -uint_t Get_HOST_CR0() { uint_t rc; VMCS_READ(HOST_CR0,&rc); return rc; } - void PrintTrace_HOST_CR0() { PrintTrace("HOST_CR0 = %x\n", Get_HOST_CR0()); } - - -void Set_HOST_CR3(uint_t val) { VMCS_WRITE(HOST_CR3,val); } -uint_t Get_HOST_CR3() { uint_t rc; VMCS_READ(HOST_CR3,&rc); return rc; } - void PrintTrace_HOST_CR3() { PrintTrace("HOST_CR3 = %x\n", Get_HOST_CR3()); } - - -void Set_HOST_CR4(uint_t val) { VMCS_WRITE(HOST_CR4,val); } -uint_t Get_HOST_CR4() { uint_t rc; VMCS_READ(HOST_CR4,&rc); return rc; } - void PrintTrace_HOST_CR4() { PrintTrace("HOST_CR4 = %x\n", Get_HOST_CR4()); } - - -void Set_HOST_FS_BASE(uint_t val) { VMCS_WRITE(HOST_FS_BASE,val); } -uint_t Get_HOST_FS_BASE() { uint_t rc; VMCS_READ(HOST_FS_BASE,&rc); return rc; } - void PrintTrace_HOST_FS_BASE() { PrintTrace("HOST_FS_BASE = %x\n", Get_HOST_FS_BASE()); } - - -void Set_HOST_GS_BASE(uint_t val) { VMCS_WRITE(HOST_GS_BASE,val); } -uint_t Get_HOST_GS_BASE() { uint_t rc; VMCS_READ(HOST_GS_BASE,&rc); return rc; } - void PrintTrace_HOST_GS_BASE() { PrintTrace("HOST_GS_BASE = %x\n", Get_HOST_GS_BASE()); } - - -void Set_HOST_TR_BASE(uint_t val) { VMCS_WRITE(HOST_TR_BASE,val); } -uint_t Get_HOST_TR_BASE() { uint_t rc; VMCS_READ(HOST_TR_BASE,&rc); return rc; } - void PrintTrace_HOST_TR_BASE() { PrintTrace("HOST_TR_BASE = %x\n", Get_HOST_TR_BASE()); } - - -void Set_HOST_GDTR_BASE(uint_t val) { VMCS_WRITE(HOST_GDTR_BASE,val); } -uint_t Get_HOST_GDTR_BASE() { uint_t rc; VMCS_READ(HOST_GDTR_BASE,&rc); return rc; } - void PrintTrace_HOST_GDTR_BASE() { PrintTrace("HOST_GDTR_BASE = %x\n", Get_HOST_GDTR_BASE()); } +void PrintTrace_HOST_IDTR_BASE() { PrintTrace("HOST_IDTR_BASE = %x\n", Get_HOST_IDTR_BASE()); } +void PrintTrace_HOST_IA32_SYSENTER_ESP() { PrintTrace("HOST_IA32_SYSENTER_ESP = %x\n", Get_HOST_IA32_SYSENTER_ESP()); } +void PrintTrace_HOST_IA32_SYSENTER_EIP() { PrintTrace("HOST_IA32_SYSENTER_EIP = %x\n", Get_HOST_IA32_SYSENTER_EIP()); } +void PrintTrace_HOST_RSP() { PrintTrace("HOST_RSP = %x\n", Get_HOST_RSP()); } +void PrintTrace_HOST_RIP() { PrintTrace("HOST_RIP = %x\n", Get_HOST_RIP()); } -void Set_HOST_IDTR_BASE(uint_t val) { VMCS_WRITE(HOST_IDTR_BASE,val); } -uint_t Get_HOST_IDTR_BASE() { uint_t rc; VMCS_READ(HOST_IDTR_BASE,&rc); return rc; } - -void PrintTrace_HOST_IDTR_BASE() { PrintTrace("HOST_IDTR_BASE = %x\n", Get_HOST_IDTR_BASE()); } +static void print_guest_segments() { + struct vmcs_segment tmp_seg; + int i = 0; + + char names[] = {"CS", "SS", "DS", "ES", "FS", "GS", "LDTR", "TR"}; + + uint32_t sels[] = { VMCS_GUEST_CS_SELECTOR, + VMCS_GUEST_SS_SELECTOR, + VMCS_GUEST_DS_SELECTOR, + VMCS_GUEST_ES_SELECTOR, + VMCS_GUEST_FS_SELECTOR, + VMCS_GUEST_GS_SELECTOR, + VMCS_GUEST_LDTR_SELECTOR, + VMCS_GUEST_TR_SELECTOR }; + + uint32_t bases[] = { VMCS_GUEST_CS_BASE, + VMCS_GUEST_SS_BASE, + VMCS_GUEST_DS_BASE, + VMCS_GUEST_ES_BASE, + VMCS_GUEST_FS_BASE, + VMCS_GUEST_GS_BASE, + VMCS_GUEST_LDTR_BASE, + VMCS_GUEST_TR_BASE }; + + uint32_t limits[] = { VMCS_GUEST_CS_LIMIT, + VMCS_GUEST_SS_LIMIT, + VMCS_GUEST_DS_LIMIT, + VMCS_GUEST_ES_LIMIT, + VMCS_GUEST_FS_LIMIT, + VMCS_GUEST_GS_LIMIT, + VMCS_GUEST_LDTR_LIMIT, + VMCS_GUEST_TR_LIMIT }; + + uint32_t accesses[] = { VMCS_GUEST_CS_ACCESS, + VMCS_GUEST_SS_ACCESS, + VMCS_GUEST_DS_ACCESS, + VMCS_GUEST_ES_ACCESS, + VMCS_GUEST_FS_ACCESS, + VMCS_GUEST_GS_ACCESS, + VMCS_GUEST_LDTR_ACCESS, + VMCS_GUEST_TR_ACCESS }; + + + for (i = 0; i < 8; i++) { + vmcs_read(sels[i], &(tmp_seg.selector), 2); + vmcs_read(bases[i], &(tmp_seg.base), 4); + vmcs_read(limits[i], &(tmp_seg.limit), 4); + vmcs_read(accesses[i], &(tmp_seg.access.value), 4); + + } + + + VMCS_GUEST_GDTR_BASE; + VMCS_GUEST_GDTR_LIMIT; + + VMCS_GUEST_IDTR_BASE; + VMCS_GUEST_IDTR_LIMIT; -void Set_HOST_IA32_SYSENTER_ESP(uint_t val) { VMCS_WRITE(HOST_IA32_SYSENTER_ESP,val); } -uint_t Get_HOST_IA32_SYSENTER_ESP() { uint_t rc; VMCS_READ(HOST_IA32_SYSENTER_ESP,&rc); return rc; } -void PrintTrace_HOST_IA32_SYSENTER_ESP() { PrintTrace("HOST_IA32_SYSENTER_ESP = %x\n", Get_HOST_IA32_SYSENTER_ESP()); } +} -void Set_HOST_IA32_SYSENTER_EIP(uint_t val) { VMCS_WRITE(HOST_IA32_SYSENTER_EIP,val); } -uint_t Get_HOST_IA32_SYSENTER_EIP() { uint_t rc; VMCS_READ(HOST_IA32_SYSENTER_EIP,&rc); return rc; } +static void print_guest_reg_state() { + PrintDebug(" Guest Register State\n"); + PrintDebug("\tGuest Ctrl Regs\n"); -void PrintTrace_HOST_IA32_SYSENTER_EIP() { PrintTrace("HOST_IA32_SYSENTER_EIP = %x\n", Get_HOST_IA32_SYSENTER_EIP()); } + PrintDebug_GUEST_CR0(); + PrintDebug_GUEST_CR3(); + PrintDebug_GUEST_CR4(); + PrintDebug_GUEST_DR7(); -void Set_HOST_RSP(uint_t val) { VMCS_WRITE(HOST_RSP,val); } -uint_t Get_HOST_RSP() { uint_t rc; VMCS_READ(HOST_RSP,&rc); return rc; } + PrintDebug_GUEST_RSP(); + PrintDebug_GUEST_RIP(); + PrintDebug_GUEST_RFLAGS(); + PrintDebug_GUEST_IA32_DEBUGCTL(); + PrintDebug_GUEST_IA32_DEBUGCTL_HIGH(); + PrintDebug_GUEST_IA32_SYSENTER_CS(); + PrintDebug_GUEST_IA32_SYSENTER_ESP(); + PrintDebug_GUEST_IA32_SYSENTER_EIP(); + PrintDebug_GUEST_SMBASE(); -void PrintTrace_HOST_RSP() { PrintTrace("HOST_RSP = %x\n", Get_HOST_RSP()); } -void Set_HOST_RIP(uint_t val) { VMCS_WRITE(HOST_RIP,val); } -uint_t Get_HOST_RIP() { uint_t rc; VMCS_READ(HOST_RIP,&rc); return rc; } +} -void PrintTrace_HOST_RIP() { PrintTrace("HOST_RIP = %x\n", Get_HOST_RIP()); } -void PrintTrace_VMCS_ALL() { - - PrintTrace("==>Guest State Area\n"); - PrintTrace("==>==> Guest Register State\n"); - PrintTrace_GUEST_CR0(); - PrintTrace_GUEST_CR3(); - PrintTrace_GUEST_CR4(); - PrintTrace_GUEST_DR7(); - PrintTrace_GUEST_RSP(); - PrintTrace_GUEST_RIP(); - PrintTrace_GUEST_RFLAGS(); - PrintTrace_VMCS_GUEST_CS_SELECTOR(); - PrintTrace_VMCS_GUEST_SS_SELECTOR(); - PrintTrace_VMCS_GUEST_DS_SELECTOR(); - PrintTrace_VMCS_GUEST_ES_SELECTOR(); - PrintTrace_VMCS_GUEST_FS_SELECTOR(); - PrintTrace_VMCS_GUEST_GS_SELECTOR(); - PrintTrace_VMCS_GUEST_LDTR_SELECTOR(); - PrintTrace_VMCS_GUEST_TR_SELECTOR(); - PrintTrace_GUEST_CS_BASE(); - PrintTrace_GUEST_SS_BASE(); - PrintTrace_GUEST_DS_BASE(); - PrintTrace_GUEST_ES_BASE(); - PrintTrace_GUEST_FS_BASE(); - PrintTrace_GUEST_GS_BASE(); - PrintTrace_GUEST_LDTR_BASE(); - PrintTrace_GUEST_TR_BASE(); - PrintTrace_GUEST_CS_LIMIT(); - PrintTrace_GUEST_SS_LIMIT(); - PrintTrace_GUEST_DS_LIMIT(); - PrintTrace_GUEST_ES_LIMIT(); - PrintTrace_GUEST_FS_LIMIT(); - PrintTrace_GUEST_GS_LIMIT(); - PrintTrace_GUEST_LDTR_LIMIT(); - PrintTrace_GUEST_TR_LIMIT(); - PrintTrace_GUEST_ES_ACCESS(); - PrintTrace_GUEST_CS_ACCESS(); - PrintTrace_GUEST_SS_ACCESS(); - PrintTrace_GUEST_DS_ACCESS(); - PrintTrace_GUEST_FS_ACCESS(); - PrintTrace_GUEST_GS_ACCESS(); - PrintTrace_GUEST_LDTR_ACCESS(); - PrintTrace_GUEST_TR_ACCESS(); - PrintTrace_GUEST_GDTR_BASE(); - PrintTrace_GUEST_IDTR_BASE(); - PrintTrace_GUEST_GDTR_LIMIT(); - PrintTrace_GUEST_IDTR_LIMIT(); - PrintTrace_GUEST_IA32_DEBUGCTL(); - PrintTrace_GUEST_IA32_DEBUGCTL_HIGH(); - PrintTrace_GUEST_IA32_SYSENTER_CS(); - PrintTrace_GUEST_IA32_SYSENTER_ESP(); - PrintTrace_GUEST_IA32_SYSENTER_EIP(); - PrintTrace_GUEST_SMBASE(); - - PrintTrace("==>==> Guest Non-Register State\n"); - PrintTrace_GUEST_ACTIVITY_STATE(); - PrintTrace_GUEST_INT_STATE(); - PrintTrace_GUEST_PENDING_DEBUG_EXCS(); - PrintTrace_VMCS_LINK_PTR(); - PrintTrace_VMCS_LINK_PTR_HIGH(); - - PrintTrace("\n==> Host State Area\n"); - PrintTrace_HOST_CR0(); - PrintTrace_HOST_CR3(); - PrintTrace_HOST_CR4(); - PrintTrace_HOST_RSP(); - PrintTrace_HOST_RIP(); - PrintTrace_VMCS_HOST_CS_SELECTOR(); - PrintTrace_VMCS_HOST_SS_SELECTOR(); - PrintTrace_VMCS_HOST_DS_SELECTOR(); - PrintTrace_VMCS_HOST_ES_SELECTOR(); - PrintTrace_VMCS_HOST_FS_SELECTOR(); - PrintTrace_VMCS_HOST_GS_SELECTOR(); - PrintTrace_VMCS_HOST_TR_SELECTOR(); - PrintTrace_HOST_FS_BASE(); - PrintTrace_HOST_GS_BASE(); - PrintTrace_HOST_TR_BASE(); - PrintTrace_HOST_GDTR_BASE(); - PrintTrace_HOST_IDTR_BASE(); - PrintTrace_HOST_IA32_SYSENTER_CS(); - PrintTrace_HOST_IA32_SYSENTER_ESP(); - PrintTrace_HOST_IA32_SYSENTER_EIP(); - - - PrintTrace("\n==> VM-Execution Controls:\n"); - PrintTrace_PIN_VM_EXEC_CTRLS(); - PrintTrace_PROC_VM_EXEC_CTRLS(); - PrintTrace_EXCEPTION_BITMAP(); - PrintTrace_PAGE_FAULT_ERROR_MASK(); - PrintTrace_PAGE_FAULT_ERROR_MATCH(); - PrintTrace_IO_BITMAP_A_ADDR(); - PrintTrace_IO_BITMAP_A_ADDR_HIGH(); - PrintTrace_IO_BITMAP_B_ADDR(); - PrintTrace_IO_BITMAP_B_ADDR_HIGH(); - PrintTrace_TSC_OFFSET(); - PrintTrace_TSC_OFFSET_HIGH(); - PrintTrace_CR0_GUEST_HOST_MASK(); - PrintTrace_CR0_READ_SHADOW(); - PrintTrace_CR4_GUEST_HOST_MASK(); - PrintTrace_CR4_READ_SHADOW(); - PrintTrace_CR3_TARGET_COUNT(); - PrintTrace_CR3_TARGET_VALUE_0(); - PrintTrace_CR3_TARGET_VALUE_1(); - PrintTrace_CR3_TARGET_VALUE_2(); - PrintTrace_CR3_TARGET_VALUE_3(); - PrintTrace_VIRT_APIC_PAGE_ADDR(); - PrintTrace_VIRT_APIC_PAGE_ADDR_HIGH(); - PrintTrace_TPR_THRESHOLD(); - PrintTrace_MSR_BITMAPS(); - PrintTrace_MSR_BITMAPS_HIGH(); - PrintTrace_VMCS_EXEC_PTR(); - PrintTrace_VMCS_EXEC_PTR_HIGH(); - - PrintTrace("\n==> VM Exit Controls\n"); - PrintTrace_VM_EXIT_CTRLS(); - PrintTrace_VM_EXIT_MSR_STORE_COUNT(); - PrintTrace_VM_EXIT_MSR_STORE_ADDR(); - PrintTrace_VM_EXIT_MSR_STORE_ADDR_HIGH(); - PrintTrace_VM_EXIT_MSR_LOAD_COUNT(); - PrintTrace_VM_EXIT_MSR_LOAD_ADDR(); - PrintTrace_VM_EXIT_MSR_LOAD_ADDR_HIGH(); - - PrintTrace("\n==> VM Entry Controls\n"); - PrintTrace_VM_ENTRY_CTRLS(); - PrintTrace_VM_ENTRY_MSR_LOAD_COUNT(); - PrintTrace_VM_ENTRY_MSR_LOAD_ADDR(); - PrintTrace_VM_ENTRY_MSR_LOAD_ADDR_HIGH(); - PrintTrace_VM_ENTRY_INT_INFO_FIELD(); - PrintTrace_VM_ENTRY_EXCEPTION_ERROR(); - PrintTrace_VM_ENTRY_INSTR_LENGTH(); - - PrintTrace("\n==> VM Exit Info\n"); - PrintTrace_EXIT_REASON(); - PrintTrace_EXIT_QUALIFICATION(); - PrintTrace_VM_EXIT_INT_INFO(); - PrintTrace_VM_EXIT_INT_ERROR(); - PrintTrace_IDT_VECTOR_INFO(); - PrintTrace_IDT_VECTOR_ERROR(); - PrintTrace_VM_EXIT_INSTR_LENGTH(); - PrintTrace_GUEST_LINEAR_ADDR(); - PrintTrace_VMX_INSTR_INFO(); - PrintTrace_IO_RCX(); - PrintTrace_IO_RSI(); - PrintTrace_IO_RDI(); - PrintTrace_IO_RIP(); - PrintTrace_VM_INSTR_ERROR(); - PrintTrace("\n"); +void PrintVMCS() { + + PrintDebug("==>Guest State Area\n"); + + PrintDebug("==>==> Guest Non-Register State\n"); + PrintDebug_GUEST_ACTIVITY_STATE(); + PrintDebug_GUEST_INT_STATE(); + PrintDebug_GUEST_PENDING_DEBUG_EXCS(); + PrintDebug_VMCS_LINK_PTR(); + PrintDebug_VMCS_LINK_PTR_HIGH(); + + PrintDebug("\n==> Host State Area\n"); + PrintDebug_HOST_CR0(); + PrintDebug_HOST_CR3(); + PrintDebug_HOST_CR4(); + PrintDebug_HOST_RSP(); + PrintDebug_HOST_RIP(); + PrintDebug_VMCS_HOST_CS_SELECTOR(); + PrintDebug_VMCS_HOST_SS_SELECTOR(); + PrintDebug_VMCS_HOST_DS_SELECTOR(); + PrintDebug_VMCS_HOST_ES_SELECTOR(); + PrintDebug_VMCS_HOST_FS_SELECTOR(); + PrintDebug_VMCS_HOST_GS_SELECTOR(); + PrintDebug_VMCS_HOST_TR_SELECTOR(); + PrintDebug_HOST_FS_BASE(); + PrintDebug_HOST_GS_BASE(); + PrintDebug_HOST_TR_BASE(); + PrintDebug_HOST_GDTR_BASE(); + PrintDebug_HOST_IDTR_BASE(); + PrintDebug_HOST_IA32_SYSENTER_CS(); + PrintDebug_HOST_IA32_SYSENTER_ESP(); + PrintDebug_HOST_IA32_SYSENTER_EIP(); + + + PrintDebug("\n==> VM-Execution Controls:\n"); + PrintDebug_PIN_VM_EXEC_CTRLS(); + PrintDebug_PROC_VM_EXEC_CTRLS(); + PrintDebug_EXCEPTION_BITMAP(); + PrintDebug_PAGE_FAULT_ERROR_MASK(); + PrintDebug_PAGE_FAULT_ERROR_MATCH(); + PrintDebug_IO_BITMAP_A_ADDR(); + PrintDebug_IO_BITMAP_A_ADDR_HIGH(); + PrintDebug_IO_BITMAP_B_ADDR(); + PrintDebug_IO_BITMAP_B_ADDR_HIGH(); + PrintDebug_TSC_OFFSET(); + PrintDebug_TSC_OFFSET_HIGH(); + PrintDebug_CR0_GUEST_HOST_MASK(); + PrintDebug_CR0_READ_SHADOW(); + PrintDebug_CR4_GUEST_HOST_MASK(); + PrintDebug_CR4_READ_SHADOW(); + PrintDebug_CR3_TARGET_COUNT(); + PrintDebug_CR3_TARGET_VALUE_0(); + PrintDebug_CR3_TARGET_VALUE_1(); + PrintDebug_CR3_TARGET_VALUE_2(); + PrintDebug_CR3_TARGET_VALUE_3(); + PrintDebug_VIRT_APIC_PAGE_ADDR(); + PrintDebug_VIRT_APIC_PAGE_ADDR_HIGH(); + PrintDebug_TPR_THRESHOLD(); + PrintDebug_MSR_BITMAPS(); + PrintDebug_MSR_BITMAPS_HIGH(); + PrintDebug_VMCS_EXEC_PTR(); + PrintDebug_VMCS_EXEC_PTR_HIGH(); + + PrintDebug("\n==> VM Exit Controls\n"); + PrintDebug_VM_EXIT_CTRLS(); + PrintDebug_VM_EXIT_MSR_STORE_COUNT(); + PrintDebug_VM_EXIT_MSR_STORE_ADDR(); + PrintDebug_VM_EXIT_MSR_STORE_ADDR_HIGH(); + PrintDebug_VM_EXIT_MSR_LOAD_COUNT(); + PrintDebug_VM_EXIT_MSR_LOAD_ADDR(); + PrintDebug_VM_EXIT_MSR_LOAD_ADDR_HIGH(); + + PrintDebug("\n==> VM Entry Controls\n"); + PrintDebug_VM_ENTRY_CTRLS(); + PrintDebug_VM_ENTRY_MSR_LOAD_COUNT(); + PrintDebug_VM_ENTRY_MSR_LOAD_ADDR(); + PrintDebug_VM_ENTRY_MSR_LOAD_ADDR_HIGH(); + PrintDebug_VM_ENTRY_INT_INFO_FIELD(); + PrintDebug_VM_ENTRY_EXCEPTION_ERROR(); + PrintDebug_VM_ENTRY_INSTR_LENGTH(); + + PrintDebug("\n==> VM Exit Info\n"); + PrintDebug_EXIT_REASON(); + PrintDebug_EXIT_QUALIFICATION(); + PrintDebug_VM_EXIT_INT_INFO(); + PrintDebug_VM_EXIT_INT_ERROR(); + PrintDebug_IDT_VECTOR_INFO(); + PrintDebug_IDT_VECTOR_ERROR(); + PrintDebug_VM_EXIT_INSTR_LENGTH(); + PrintDebug_GUEST_LINEAR_ADDR(); + PrintDebug_VMX_INSTR_INFO(); + PrintDebug_IO_RCX(); + PrintDebug_IO_RSI(); + PrintDebug_IO_RDI(); + PrintDebug_IO_RIP(); + PrintDebug_VM_INSTR_ERROR(); + PrintDebug("\n"); } diff --git a/palacios/src/palacios/vmm.c b/palacios/src/palacios/vmm.c index e860391..4a71a11 100644 --- a/palacios/src/palacios/vmm.c +++ b/palacios/src/palacios/vmm.c @@ -19,7 +19,7 @@ #include #include -#include +//#include #include #include #include diff --git a/palacios/src/palacios/vmx.c b/palacios/src/palacios/vmx.c index 19f8312..0395b6e 100644 --- a/palacios/src/palacios/vmx.c +++ b/palacios/src/palacios/vmx.c @@ -20,24 +20,24 @@ */ -/* Eventually we want to get rid of these */ - -#include -#include -#include -/* ** */ - #include #include #include + + +// +// +// CRUFT +// +// + + + #include #include -extern void Get_MSR(unsigned int msr, uint_t * high, uint_t * low); -extern void Set_MSR(unsigned int msr, uint_t high, uint_t low); -extern int Enable_VMX(ullong_t regionPtr); -extern int cpuid_ecx(unsigned int op); + extern int Launch_VM(ullong_t vmcsPtr, uint_t eip); #define NUMPORTS 65536 @@ -52,9 +52,8 @@ extern int Launch_VM(ullong_t vmcsPtr, uint_t eip); static struct VM theVM; -static uint_t GetLinearIP(struct VM *vm) -{ - if (vm->state==VM_VMXASSIST_V8086_BIOS || vm->state==VM_VMXASSIST_V8086) { +static uint_t GetLinearIP(struct VM * vm) { + if (vm->state == VM_VMXASSIST_V8086_BIOS || vm->state == VM_VMXASSIST_V8086) { return vm->vmcs.guestStateArea.cs.baseAddr + vm->vmcs.guestStateArea.rip; } else { return vm->vmcs.guestStateArea.rip; @@ -62,10 +61,6 @@ static uint_t GetLinearIP(struct VM *vm) } -static void VMXPanic() -{ - while (1) {} -} #define MAX_CODE 512 @@ -77,120 +72,10 @@ static void VMXPanic() uint_t oldesp=0; uint_t myregs=0; -// simply execute the instruction that is faulting and return -static int ExecFaultingInstructionInVMM(struct VM *vm) -{ - uint_t address = GetLinearIP(vm); - myregs = (uint_t)&(vm->registers); - - PrintTrace("About the execute faulting instruction!\n"); - PrintTrace("Instruction is:\n"); - PrintTraceMemDump((void*)(address),vm->vmcs.exitInfoFields.instrLength); - - PrintTrace("The template code is:\n"); - PrintTraceMemDump(&&template_code,TEMPLATE_CODE_LEN); - // clone the template code - //memcpy(&&template_code,code,MAX_CODE); - - // clean up the nop field - memset(&&template_code+INSTR_OFFSET_START,*((uchar_t *)(&&template_code+0)),NOP_SEQ_LEN); - // overwrite the nops with the faulting instruction - memcpy(&&template_code+INSTR_OFFSET_START, (void*)(address),vm->vmcs.exitInfoFields.instrLength); - - PrintTrace("Finished modifying the template code, which now is:\n"); - PrintTraceMemDump(&&template_code,TEMPLATE_CODE_LEN); - - PrintTrace("Now entering modified template code\n"); - - - template_code: - // Template code stores current registers, - // restores registers, has a landing pad of noops - // that will be modified, restores current regs, and then returns - // - // Note that this currently ignores cr0, cr3, cr4, dr7, rsp, rip, and rflags - // it also blythly assumes it can exec the instruction in protected mode - // - __asm__ __volatile__ ("nop\n" // for cloning purposes (1 byte) - "pusha\n" // push our current regs onto the current stack (1 byte) - "movl %0, %%eax\n" // Get oldesp location (5 bytes) - "movl %%esp, (%%eax)\n" // store the current stack pointer in oldesp (2 bytes) - "movl %1, %%eax\n" // Get regs location (5 bytes) - "movl (%%eax), %%esp\n" // point esp at regs (2 bytes) - "popa\n" // now we have the VM registers restored (1 byte) - "nop\n" // now we execute the actual instruction (1 byte x 10) - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - // need to copy back to the VM registers! - "movl %0, %%eax\n" // recapture oldesp location (5 bytes) - "movl (%%eax), %%esp\n" // now we'll get our esp back from oldesp (2 bytes) - "popa\n" // and restore our GP regs and we're done (1 byte) - : "=m"(oldesp) - : "m"(myregs) - ); - - PrintTrace("Survived executing the faulting instruction and returning.\n"); - - vm->vmcs.guestStateArea.rip += vm->vmcs.exitInfoFields.instrLength; - return 0; - -} - - -int is_vmx_capable() { - uint_t ret; - union VMX_MSR featureMSR; - - ret = cpuid_ecx(1); - if (ret & CPUID_1_ECX_VTXFLAG) { - Get_MSR(IA32_FEATURE_CONTROL_MSR, &featureMSR.regs.high, &featureMSR.regs.low); - - PrintTrace("MSRREGlow: 0x%.8x\n", featureMSR.regs.low); - - if ((featureMSR.regs.low & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) { - PrintDebug("VMX is locked -- enable in the BIOS\n"); - return 0; - } - } else { - PrintDebug("VMX not supported on this cpu\n"); - return 0; - } - - return 1; - -} - - -VmxOnRegion * Init_VMX() { - uint_t ret; - VmxOnRegion * region = NULL; - - - region = CreateVmxOnRegion(); - - - ret = Enable_VMX((ullong_t)((uint_t)region)); - if (ret == 0) { - PrintDebug("VMX Enabled\n"); - } else { - PrintDebug("VMX failure (ret = %d)\n", ret); - } - - theVM.vmxonregion = region; - - return region; -} extern uint_t VMCS_CLEAR(); extern uint_t VMCS_LOAD(); @@ -200,206 +85,13 @@ extern uint_t VMCS_RESUME(); extern uint_t Init_VMCS_HostState(); extern uint_t Init_VMCS_GuestState(); -void SetCtrlBitsCorrectly(int msrno, int vmcsno) -{ - uint_t reserved =0; - union VMX_MSR msr; - - PrintTrace("SetCtrlBitsCorrectly(%x,%x)\n", msrno, vmcsno); - Get_MSR(msrno, &msr.regs.high, &msr.regs.low); - PrintTrace("MSR %x = %x : %x \n", msrno, msr.regs.high, msr.regs.low); - reserved = msr.regs.low; - reserved &= msr.regs.high; - VMCS_WRITE(vmcsno, &reserved); -} - -void SetCRBitsCorrectly(int msr0no, int msr1no, int vmcsno) -{ - uint_t reserved =0; - union VMX_MSR msr0, msr1; - - PrintTrace("SetCRBitsCorrectly(%x,%x,%x)\n",msr0no,msr1no,vmcsno); - Get_MSR(msr0no, &msr0.regs.high, &msr0.regs.low); - Get_MSR(msr1no, &msr1.regs.high, &msr1.regs.low); - PrintTrace("MSR %x = %x, %x = %x \n", msr0no, msr0.regs.low, msr1no, msr1.regs.low); - reserved = msr0.regs.low; - reserved &= msr1.regs.low; - VMCS_WRITE(vmcsno, &reserved); -} extern int Get_CR2(); extern int vmRunning; -static int PanicUnhandledVMExit(struct VM *vm) -{ - PrintInfo("Panicking due to VMExit with reason %u\n", vm->vmcs.exitInfoFields.reason); - PrintTrace("Panicking due to VMExit with reason %u\n", vm->vmcs.exitInfoFields.reason); - PrintTrace_VMCS_ALL(); - PrintTrace_VMX_Regs(&(vm->registers)); - VMXPanic(); - return 0; -} - - -static int HandleVMPrintsAndPanics(struct VM *vm, uint_t port, uint_t data) -{ - if (port==VMXASSIST_INFO_PORT && - (vm->state == VM_VMXASSIST_STARTUP || - vm->state == VM_VMXASSIST_V8086_BIOS || - vm->state == VM_VMXASSIST_V8086)) { - // Communication channel from VMXAssist - PrintTrace("VMXASSIST Output Port\n"); - PrintDebug("%c",data&0xff); - return 1; - } - - if ((port==ROMBIOS_PANIC_PORT || - port==ROMBIOS_PANIC_PORT2 || - port==ROMBIOS_DEBUG_PORT || - port==ROMBIOS_INFO_PORT) && - (vm->state==VM_VMXASSIST_V8086_BIOS)) { - // rombios is communicating - PrintTrace("ROMBIOS Output Port\n"); - // PrintDebug("%c",data&0xff); - return 1; - } - - if (port==BOOT_STATE_CARD_PORT && vm->state==VM_VMXASSIST_V8086_BIOS) { - // rombios is sending something to the display card - PrintTrace("Hex Display: 0x%x\n",data&0xff); - return 1; - } - return 0; -} - -static int HandleInOutExit(struct VM *vm) -{ - uint_t address; - - struct VMCSExitInfoFields *exitinfo = &(vm->vmcs.exitInfoFields); - struct VMExitIOQual * qual = (struct VMExitIOQual *)&(vm->vmcs.exitInfoFields.qualification); - struct VMXRegs *regs = &(vm->registers); - - address=GetLinearIP(vm); - - PrintTrace("Handling Input/Output Instruction Exit\n"); - - PrintTrace_VMX_Regs(regs); - - PrintTrace("Qualifications=0x%x\n", exitinfo->qualification); - PrintTrace("Reason=0x%x\n", exitinfo->reason); - PrintTrace("IO Port: 0x%x (%d)\n", qual->port, qual->port); - PrintTrace("Instruction Info=%x\n", exitinfo->instrInfo); - PrintTrace("%x : %s %s %s instruction of length %d for %d bytes from/to port 0x%x\n", - address, - qual->dir == 0 ? "output" : "input", - qual->string ==0 ? "nonstring" : "STRING", - qual->REP == 0 ? "with no rep" : "WITH REP", - exitinfo->instrLength, - qual->accessSize==0 ? 1 : qual->accessSize==1 ? 2 : 4, - qual->port); - - if ((qual->port == PIC_MASTER_CMD_ISR_PORT) || - (qual->port == PIC_MASTER_IMR_PORT) || - (qual->port == PIC_SLAVE_CMD_ISR_PORT) || - (qual->port == PIC_SLAVE_IMR_PORT)) { - PrintTrace( "PIC Access\n"); - } - - - if ((qual->dir == 1) && (qual->REP == 0) && (qual->string == 0)) { - char byte = In_Byte(qual->port); - - vm->vmcs.guestStateArea.rip += exitinfo->instrLength; - regs->eax = (regs->eax & 0xffffff00) | byte; - PrintTrace("Returning 0x%x in eax\n", (regs->eax)); - } - - if (qual->dir==0 && qual->REP==0 && qual->string==0) { - // See if we need to handle the outb as a signal or - // print from the VM - if (HandleVMPrintsAndPanics(vm,qual->port,regs->eax)) { - } else { - // If not, just go ahead and do the outb - Out_Byte(qual->port,regs->eax); - PrintTrace("Wrote 0x%x to port\n",(regs->eax)); - } - vm->vmcs.guestStateArea.rip += exitinfo->instrLength; - } - - return 0; -} - - -static int HandleExternalIRQExit(struct VM *vm) -{ - struct VMCSExitInfoFields * exitinfo = &(vm->vmcs.exitInfoFields); - struct VMExitIntInfo * intInfo = (struct VMExitIntInfo *)&(vm->vmcs.exitInfoFields.intInfo); - - PrintTrace("External Interrupt captured\n"); - PrintTrace("IntInfo: %x\n", exitinfo->intInfo); - - - if (!intInfo->valid) { - // interrupts are off, but this interrupt is not acknoledged (still pending) - // so we turn on interrupts to deliver appropriately in the - // host - PrintTrace("External Interrupt is invald. Turning Interrupts back on\n"); - asm("sti"); - return 0; - } - - // At this point, interrupts are off and the interrupt has been - // acknowledged. We will now handle the interrupt ourselves - // and turn interrupts back on in the host - - PrintTrace("type: %d\n", intInfo->type); - PrintTrace("number: %d\n", intInfo->nr); - - PrintTrace("Interrupt %d occuring now and handled by HandleExternalIRQExit\n",intInfo->nr); - - switch (intInfo->type) { - case 0: { // ext. IRQ - // In the following, we construct an "int x" instruction - // where x is the specific interrupt number that is raised - // then we execute that instruciton - // because we are in host context, that means it is delivered as normal - // through the host IDT - - ((char*)(&&ext_int_seq_start))[1] = intInfo->nr; - - PrintTrace("Interrupt instruction setup done %x\n", *((ushort_t *)(&&ext_int_seq_start))); - -ext_int_seq_start: - asm("int $0"); - } - - break; - case 2: // NMI - PrintTrace("Type: NMI\n"); - break; - case 3: // hw exception - PrintTrace("Type: HW Exception\n"); - break; - case 4: // sw exception - PrintTrace("Type: SW Exception\n"); - break; - default: - PrintTrace("Invalid Interrupt Type\n"); - return -1; - } - - if (intInfo->valid && intInfo->errorCode) { - PrintTrace("IntError: %x\n", exitinfo->intErrorCode); - } - - - return 0; - -} @@ -433,12 +125,12 @@ void DecodeCurrentInstruction(struct VM *vm, struct Instruction *inst) static void V8086ModeSegmentRegisterFixup(struct VM *vm) { - vm->vmcs.guestStateArea.cs.baseAddr=vm->vmcs.guestStateArea.cs.selector<<4; - vm->vmcs.guestStateArea.es.baseAddr=vm->vmcs.guestStateArea.es.selector<<4; - vm->vmcs.guestStateArea.ss.baseAddr=vm->vmcs.guestStateArea.ss.selector<<4; - vm->vmcs.guestStateArea.ds.baseAddr=vm->vmcs.guestStateArea.ds.selector<<4; - vm->vmcs.guestStateArea.fs.baseAddr=vm->vmcs.guestStateArea.fs.selector<<4; - vm->vmcs.guestStateArea.gs.baseAddr=vm->vmcs.guestStateArea.gs.selector<<4; + vm->vmcs.guestStateArea.cs.baseAddr = vm->vmcs.guestStateArea.cs.selector << 4; + vm->vmcs.guestStateArea.es.baseAddr = vm->vmcs.guestStateArea.es.selector << 4; + vm->vmcs.guestStateArea.ss.baseAddr = vm->vmcs.guestStateArea.ss.selector << 4; + vm->vmcs.guestStateArea.ds.baseAddr = vm->vmcs.guestStateArea.ds.selector << 4; + vm->vmcs.guestStateArea.fs.baseAddr = vm->vmcs.guestStateArea.fs.selector << 4; + vm->vmcs.guestStateArea.gs.baseAddr = vm->vmcs.guestStateArea.gs.selector << 4; } static void SetupV8086ModeForBoot(struct VM *vm) @@ -454,27 +146,27 @@ static void SetupV8086ModeForBoot(struct VM *vm) // reset vm->vmcs.guestStateArea.rip = 0xfff0; // note, 16 bit rip vm->vmcs.guestStateArea.cs.selector = 0xf000; - vm->vmcs.guestStateArea.cs.limit=0xffff; + vm->vmcs.guestStateArea.cs.limit = 0xffff; vm->vmcs.guestStateArea.cs.access.as_dword = 0xf3; vm->vmcs.guestStateArea.ss.selector = 0x0000; - vm->vmcs.guestStateArea.ss.limit=0xffff; + vm->vmcs.guestStateArea.ss.limit = 0xffff; vm->vmcs.guestStateArea.ss.access.as_dword = 0xf3; vm->vmcs.guestStateArea.ds.selector = 0x0000; - vm->vmcs.guestStateArea.ds.limit=0xffff; + vm->vmcs.guestStateArea.ds.limit = 0xffff; vm->vmcs.guestStateArea.ds.access.as_dword = 0xf3; vm->vmcs.guestStateArea.es.selector = 0x0000; - vm->vmcs.guestStateArea.es.limit=0xffff; + vm->vmcs.guestStateArea.es.limit = 0xffff; vm->vmcs.guestStateArea.es.access.as_dword = 0xf3; vm->vmcs.guestStateArea.fs.selector = 0x0000; - vm->vmcs.guestStateArea.fs.limit=0xffff; + vm->vmcs.guestStateArea.fs.limit = 0xffff; vm->vmcs.guestStateArea.fs.access.as_dword = 0xf3; vm->vmcs.guestStateArea.gs.selector = 0x0000; - vm->vmcs.guestStateArea.gs.limit=0xffff; + vm->vmcs.guestStateArea.gs.limit = 0xffff; vm->vmcs.guestStateArea.gs.access.as_dword = 0xf3; V8086ModeSegmentRegisterFixup(vm); @@ -485,265 +177,6 @@ static void SetupV8086ModeForBoot(struct VM *vm) -static int HandleExceptionOrNMI(struct VM *vm) -{ - struct Instruction inst; - uint_t num; - uint_t type; - uint_t errorvalid; - uint_t error; - uint_t ext=0; - uint_t idt=0; - uint_t ti=0; - uint_t selectorindex=0; - - PrintTrace("Exception or NMI occurred\n"); - - num=vm->vmcs.exitInfoFields.intInfo & 0xff; - type=(vm->vmcs.exitInfoFields.intInfo & 0x700)>>8; - errorvalid=(vm->vmcs.exitInfoFields.intInfo & 0x800)>>11; - if (errorvalid) { - error=vm->vmcs.exitInfoFields.intErrorCode; - ext=error&0x1; - idt=(error&0x2)>>1; - ti=(error&0x4)>>2; - selectorindex=(error>>3)&0xffff; - } - - PrintTrace("Exception %d now - handled by HandleExceptionOrNMI\n",num); - - PrintTrace("Exception Number %u : %s\n", num, exception_names[num]); - PrintTrace("Exception Type %u : %s\n", type, exception_type_names[type]); - if (errorvalid) { - if (ext) { - PrintTrace("External\n"); - } else { - PrintTrace("%s - Selector Index is %u\n", idt ? "IDT" : ti ? "LDT" : "GDT", selectorindex); - } - } - - DecodeCurrentInstruction(vm,&inst); - - if (inst.type==VM_MOV_TO_CR0) { - PrintTrace("MOV TO CR0, oldvalue=0x%x, newvalue=0x%x\n",inst.input2, inst.input1); - if ((inst.input2 & CR0_PE) && !(inst.input1 & CR0_PE) && vm->state==VM_VMXASSIST_STARTUP) { - // This is VMXAssist signalling for us to turn on V8086 mode and - // jump into the bios - PrintTrace("VMXAssist is signaling us for switch to V8086 mode and jump to 0xf000:fff0\n"); - SetupV8086ModeForBoot(vm); - goto leave; - } else { - PrintTrace("Instruction is a write to CR0, but we don't understand it so we'll just exec it\n"); - } - } - - - PrintTrace("Trying to execute the faulting instruction in VMM context now\n"); - ExecFaultingInstructionInVMM(vm); - - leave: - // - //PanicUnhandledVMExit(vmcs,regs); - //VMXPanic(); - return 0; -} - - -static struct VM *FindVM() -{ - return &theVM; -} - - -int Do_VMM(struct VMXRegs regs) -{ - - ullong_t vmcs_ptr = 0; - uint_t vmcs_ptr_low = 0; - int ret = 0; - uint_t vmx_abort = 0; - - - - PrintTrace("Vm Exit\n"); - ret = VMCS_STORE(&vmcs_ptr); - vmcs_ptr &= 0xffffffff; - vmcs_ptr_low += vmcs_ptr; - - - - - PrintTrace("ret=%d\n", ret); - PrintTrace("Revision: %x\n", *(uint_t *)(vmcs_ptr_low)); - vmx_abort = *(uint_t*)(((char *)vmcs_ptr_low)+4); - - struct VM *vm = FindVM(); - - if (vmx_abort != 0) { - PrintTrace("VM ABORTED w/ code: %x\n", vmx_abort); - return -1; - } - - vm->registers = regs; - - if (CopyOutVMCSData(&(vm->vmcs)) != 0) { - PrintTrace("Could not copy out VMCS\n"); - return -1; - } - - - PrintTrace("Guest esp: 0x%x (%u)\n", vm->vmcs.guestStateArea.rsp, vm->vmcs.guestStateArea.rsp); - - PrintTrace("VM Exit for reason: %d (%x)\n", - vm->vmcs.exitInfoFields.reason & 0x00000fff, - vm->vmcs.exitInfoFields.reason); - - if (vm->vmcs.exitInfoFields.reason & (0x1<<29) ) { - PrintTrace("VM Exit is from VMX root operation. Panicking\n"); - VMXPanic(); - } - - if (vm->vmcs.exitInfoFields.reason & (0x1<<31) ) { - PrintTrace("VM Exit is due to a VM entry failure. Shouldn't happen here. Panicking\n"); - PrintTrace_VMCSData(&(vm->vmcs)); - VMXPanic(); - } - - switch (vm->vmcs.exitInfoFields.reason) { - case VM_EXIT_REASON_INFO_EXCEPTION_OR_NMI: - ret = HandleExceptionOrNMI(vm); - break; - case VM_EXIT_REASON_EXTERNAL_INTR: - ret = HandleExternalIRQExit(vm); - break; - case VM_EXIT_REASON_TRIPLE_FAULT: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INIT_SIGNAL: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_STARTUP_IPI: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_IO_SMI: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_OTHER_SMI: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INTR_WINDOW: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_NMI_WINDOW: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_TASK_SWITCH: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_CPUID: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INVD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INVLPG: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_RDPMC: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_RDTSC: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_RSM: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMCALL: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMCLEAR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMLAUNCH: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMPTRLD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMPTRST: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMREAD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMRESUME: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMWRITE: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMXOFF: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMXON: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_CR_REG_ACCESSES: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_MOV_DR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_IO_INSTR: - ret = HandleInOutExit(vm); - break; - case VM_EXIT_REASON_RDMSR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_WRMSR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_ENTRY_FAIL_INVALID_GUEST_STATE: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_ENTRY_FAIL_MSR_LOAD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_MWAIT: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_MONITOR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_PAUSE: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_TPR_BELOW_THRESHOLD: - ret = PanicUnhandledVMExit(vm); - break; - default: - ret = PanicUnhandledVMExit(vm); - break; - } - - - regs = vm->registers; - CopyInVMCSData(&(vm->vmcs)); - - /* - { - VMCS_CLEAR(vmcs_ptr); - } - */ - - PrintTrace("Returning from Do_VMM: %d\n", ret); - - return ret; -} - static void ConfigureExits(struct VM *vm) { @@ -753,17 +186,17 @@ static void ConfigureExits(struct VM *vm) // EXTERNAL_INTERRUPT_EXITING | NMI_EXITING; vm->vmcs.execCtrlFields.procCtrls |= 0 - // INTERRUPT_WINDOWS_EXIT - | USE_TSC_OFFSETTING - | HLT_EXITING - |INVLPG_EXITING - |MWAIT_EXITING - |RDPMC_EXITING - |RDTSC_EXITING - |MOVDR_EXITING - |UNCONDITION_IO_EXITING - |MONITOR_EXITING - |PAUSE_EXITING ; + // INTERRUPT_WINDOWS_EXIT + | USE_TSC_OFFSETTING + | HLT_EXITING + | INVLPG_EXITING + | MWAIT_EXITING + | RDPMC_EXITING + | RDTSC_EXITING + | MOVDR_EXITING + | UNCONDITION_IO_EXITING + | MONITOR_EXITING + | PAUSE_EXITING ; CopyInVMCSExecCtrlFields(&(vm->vmcs.execCtrlFields)); @@ -888,43 +321,212 @@ int VMLaunch(struct VMDescriptor *vm) int rc; ullong_t vmcs_ptr = (ullong_t)((uint_t)vmcs); - uint_t top = (vmcs_ptr>>32)&0xffffffff; - uint_t bottom = (vmcs_ptr)&0xffffffff; + uint_t top = (vmcs_ptr >> 32) & 0xffffffff; + uint_t bottom = (vmcs_ptr) & 0xffffffff; theVM.vmcsregion = vmcs; theVM.descriptor = *vm; PrintTrace("vmcs_ptr_top=%x vmcs_ptr_bottom=%x, eip=%x\n", top, bottom, vm->entry_ip); - rc=MyLaunch(&theVM); // vmcs_ptr, vm->entry_ip, vm->exit_eip, vm->guest_esp); + rc = MyLaunch(&theVM); // vmcs_ptr, vm->entry_ip, vm->exit_eip, vm->guest_esp); PrintTrace("Returned from MyLaunch();\n"); return rc; } -VmxOnRegion * CreateVmxOnRegion() { - union VMX_MSR basicMSR; - VmxOnRegion * region = (VmxOnRegion *)(os_hooks)->allocate_pages(1); - Get_MSR(IA32_VMX_BASIC_MSR, &basicMSR.regs.high, &basicMSR.regs.low); - // memcpy(region, &basicMSR.vmxBasic.revision, sizeof(uint_t)); - *(ulong_t*)region = basicMSR.vmxBasic.revision; +// +// +// END CRUFT +// +// + + +// For the 32 bit reserved bit fields +// MB1s are in the low 32 bits, MBZs are in the high 32 bits of the MSR +static uint32_t sanitize_bits1(uint32_t msr_num, uint32_t val) { + v3_msr_t mask_msr; + + PrintDebug("sanitize_bits1 (MSR:%x)\n", msr_num); + + v3_get_msr(msr_num, &mask_msr.hi, &mask_msr.lo); + + PrintDebug("MSR %x = %x : %x \n", msr_num, msr.hi, msr.lo); + + val &= mask_msr.lo; + val &= mask_msr.hi; + + return val; +} + + +static addr_t sanitize_bits2(uint32_t msr_num0, uint32_t msr_num1, addr_t val) { + v3_msr_t msr0, msr1; + addr_t msr0_val, msr1_val; + + PrintDebug("sanitize_bits2 (MSR0=%x, MSR1=%x)\n", msr_num0, msr_num1); + + v3_get_msr(msr_num0, &msr0.hi, &msr0.lo); + v3_get_msr(msr_num1, &msr1.hi, &msr1.lo); + + // This generates a mask that is the natural bit width of the CPU + msr0_val = msr0.value; + msr1_val = msr1.value; + + PrintDebug("MSR %x = %p, %x = %p \n", msr_num0, msr0_val, msr_num1, msr1_val); + + val &= msr0_val; + val &= msr1_val; + + return val; +} + + + +static vmcs_t * allocate_vmcs() { + reg_ex_t msr; + vmcs_t * vmcs_page = (vmcs_t *)V3_VAddr(V3_AllocPages(1)); + + memset(vmcb_page, 0, 4096); + + v3_get_msr(VMX_BASIC_MSR, &(msr.e_reg.high), &(msr.e_reg.low)); + + *(uint32_t *)vmcs_page = ((struct vmx_basic_msr *)msr.val)->revision; + + return vmcs_page; +} + + + +static void init_vmcs_bios(vmcs_t * vmcs, struct guest_info * vm_info) { + +} + + + +static int init_vmx_guest(struct guest_info * info, struct v3_vm_config * config_ptr) { + v3_pre_config_guest(info, config_ptr); + + PrintDebug("Allocating VMCS\n"); + info->vmm_data = (void *)allocate_vmcs(); + + PrintDebug("Initializing VMCS (addr=%p)\n", (void *)info->vmm_data); + init_vmcs_bios((vmcs_t *)(info->vmm_data), info); + + v3_post_config_guest(info, config_ptr); + + return 0; +} + + + + +static int start_svm_guest(struct guest_info *info) { + return -1; +} + + + + + + +int v3_is_vmx_capable() { + uint_t ret; + v3_msr_t feature_msr; + addr_t eax = 0, ebx = 0, ecx = 0, edx = 0; + + v3_cpuid(CPUID_FEATURE_IDS, &eax, &ebx, &ecx, &edx); + + if (ecx & CPUID_1_ECX_VTXFLAG) { + v3_get_msr(IA32_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo)); + + PrintTrace("MSRREGlow: 0x%.8x\n", feature_msr.lo); + + if ((feature_msr.lo & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) { + PrintDebug("VMX is locked -- enable in the BIOS\n"); + return 0; + } + + } else { + PrintDebug("VMX not supported on this cpu\n"); + return 0; + } + + return 1; + +} + +static int has_vmx_nested_paging() { + return 0; +} + + + +// We set up the global host state that is unlikely to change across processes here +// Segment Descriptors mainly + +struct seg_descriptor { + +}; + + +static int setup_base_host_state() { + uint8_t gdt[10]; + + + + vmwrite(HOST_IDTR_BASE, - PrintInfo("VMX revision: 0x%lu\n", *(ulong_t *)region); - return region; } -VMCS * CreateVMCS() { - union VMX_MSR basicMSR; - VMCS * vmcs = (VMCS *)(os_hooks)->allocate_pages(1); - Get_MSR(IA32_VMX_BASIC_MSR, &basicMSR.regs.high, &basicMSR.regs.low); - *(ulong_t *)vmcs = basicMSR.vmxBasic.revision; - *(ulong_t *)((char*)vmcs + 4) = 0; - PrintTrace("VMCS Region size: %u\n", basicMSR.vmxBasic.regionSize); - PrintTrace("VMCS Abort: %x\n",*(uint_t *)(((char*)vmcs)+4)); +void v3_init_vmx(struct v3_ctrl_ops * vm_ops) { + v3_msr_t basic_msr; + + // Setup the host state save area + void * host_state = V3_AllocPages(1); + + v3_get_msr(VMX_BASIC_MSR, &(basic_msr.hi), &(basic_msr.lo)); + + *(uint32_t *)host_state = ((struct vmx_basic_msr *)basic_msr.value)->revision; + + PrintDebug("VMX revision: 0x%p\n", host_state); + + __asm__ __volatile__ ( + "movl %%cr4, %%ebx; " + "orl %%ebx, 0x00002000; " + "movl %%ebx, %%cr4" + ); + + + + // Should check and return Error here.... + __asm__ __volatile__ ( + "movl %%cr0, %%ebx; " + "orl %%ebx, 0x00000020; " + "movl %%ebx, %%cr0" + ); + + + if (v3_enable_vmx(host_state) == 0) { + PrintDebug("VMX Enabled\n"); + } else { + PrintDebug("VMX initialization failure\n"); + } + + + if (has_vmx_nested_paging() == 1) { + v3_cpu_type = V3_VMX_EPT_CPU; + } else { + v3_cpu_type = V3_VMX_CPU; + } + + // Setup the VMX specific vmm operations + vmm_ops->init_guest = &init_vmx_guest; + vmm_ops->start_guest = &start_vmx_guest; + vmm_ops->has_nested_paging = &has_vmx_nested_paging; - return vmcs; }