X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?p=palacios.git;a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fide.c;h=197d90370a53958142c5afe03ae5c83cecbcfaf7;hp=87e10c3723de4f082f8de19ce5f8fec2a154cb18;hb=6661dd1d2aa547ae248e816dcd4201bcbcb7fee0;hpb=6fe0528310bec884ed00c8d97b45d18120a32e3f diff --git a/palacios/src/devices/ide.c b/palacios/src/devices/ide.c index 87e10c3..197d903 100644 --- a/palacios/src/devices/ide.c +++ b/palacios/src/devices/ide.c @@ -18,9 +18,14 @@ */ #include +#include #include +#include #include "ide-types.h" +#include "atapi-types.h" +#define PRI_DEFAULT_IRQ 14 +#define SEC_DEFAULT_IRQ 15 #define PRI_DATA_PORT 0x1f0 @@ -46,8 +51,46 @@ #define SEC_ADDR_REG_PORT 0x377 +#define PRI_DEFAULT_DMA_PORT 0xc000 +#define SEC_DEFAULT_DMA_PORT 0xc008 -static const char * ide_dev_type_strs[] = {"HARDDISK", "CDROM", "NONE"}; + +#define DATA_BUFFER_SIZE 2048 + +static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM", + "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD", + "PRI_CTRL", "PRI_ADDR_REG"}; + + +static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM", + "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD", + "SEC_CTRL", "SEC_ADDR_REG"}; + +static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL, + "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"}; + + + +static inline const char * io_port_to_str(uint16_t port) { + if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) { + return ide_pri_port_strs[port - PRI_DATA_PORT]; + } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) { + return ide_sec_port_strs[port - SEC_DATA_PORT]; + } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) { + return ide_pri_port_strs[port - PRI_CTRL_PORT + 8]; + } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) { + return ide_sec_port_strs[port - SEC_CTRL_PORT + 8]; + } + return NULL; +} + + +static inline const char * dma_port_to_str(uint16_t port) { + return ide_dma_port_strs[port & 0x7]; +} + + +static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" }; static inline const char * device_type_to_str(v3_ide_dev_type_t type) { @@ -60,7 +103,16 @@ static inline const char * device_type_to_str(v3_ide_dev_type_t type) { +struct ide_cd_state { + struct atapi_sense_data sense; + + uint8_t atapi_cmd; + struct atapi_error_recovery err_recovery; +}; +struct ide_hd_state { + int accessed; +}; struct ide_drive { // Command Registers @@ -73,20 +125,57 @@ struct ide_drive { }; + union { + struct ide_cd_state cd_state; + struct ide_hd_state hd_state; + }; + char model[41]; + + // Where we are in the data transfer + uint_t transfer_index; + + // the length of a transfer + // calculated for easy access + uint_t transfer_length; + + uint64_t current_lba; + + // We have a local data buffer that we use for IO port accesses + uint8_t data_buf[DATA_BUFFER_SIZE]; + + void * private_data; + + union { + uint8_t sector_count; // 0x1f2,0x172 + struct atapi_irq_flags irq_flags; + } __attribute__((packed)); + + union { + uint8_t sector_num; // 0x1f3,0x173 + uint8_t lba0; + } __attribute__((packed)); - uint8_t sector_count; // 0x1f2,0x172 - uint8_t sector_num; // 0x1f3,0x173 union { uint16_t cylinder; + uint16_t lba12; + struct { uint8_t cylinder_low; // 0x1f4,0x174 uint8_t cylinder_high; // 0x1f5,0x175 } __attribute__((packed)); + + struct { + uint8_t lba1; + uint8_t lba2; + } __attribute__((packed)); + + + // The transfer length requested by the CPU + uint16_t req_len; } __attribute__((packed)); - }; @@ -102,27 +191,63 @@ struct ide_channel { struct ide_drive_head_reg drive_head; // 0x1f6,0x176 struct ide_status_reg status; // [read] 0x1f7,0x177 - uint8_t command_reg; // [write] 0x1f7,0x177 + uint8_t cmd_reg; // [write] 0x1f7,0x177 + + int irq; // this is temporary until we add PCI support + + struct pci_device * pci_dev; // Control Registers struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376 + + struct ide_dma_cmd_reg dma_cmd; + struct ide_dma_status_reg dma_status; + uint32_t dma_prd_addr; + uint_t dma_tbl_index; }; struct ide_internal { struct ide_channel channels[2]; + struct vm_device * pci; + struct pci_device * busmaster_pci; }; + +/* Utility functions */ + +static inline uint16_t be_to_le_16(const uint16_t val) { + uint8_t * buf = (uint8_t *)&val; + return (buf[0] << 8) | (buf[1]) ; +} + +static inline uint16_t le_to_be_16(const uint16_t val) { + return be_to_le_16(val); +} + + +static inline uint32_t be_to_le_32(const uint32_t val) { + uint8_t * buf = (uint8_t *)&val; + return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; +} + +static inline uint32_t le_to_be_32(const uint32_t val) { + return be_to_le_32(val); +} + + static inline int get_channel_index(ushort_t port) { if (((port & 0xfff8) == 0x1f0) || - ((port & 0xfffe) == 0x3f6)) { + ((port & 0xfffe) == 0x3f6) || + ((port & 0xfff8) == 0xc000)) { return 0; } else if (((port & 0xfff8) == 0x170) || - ((port & 0xfffe) == 0x376)) { + ((port & 0xfffe) == 0x376) || + ((port & 0xfff8) == 0xc008)) { return 1; } @@ -144,16 +269,33 @@ static inline int is_lba_enabled(struct ide_channel * channel) { } +/* Drive Commands */ +static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) { + if (channel->ctrl_reg.irq_disable == 0) { + PrintDebug("Raising IDE Interrupt %d\n", channel->irq); + channel->dma_status.int_gen = 1; + v3_raise_irq(dev->vm, channel->irq); + } +} + + static void drive_reset(struct ide_drive * drive) { drive->sector_count = 0x01; drive->sector_num = 0x01; + + PrintDebug("Resetting drive %s\n", drive->model); if (drive->drive_type == IDE_CDROM) { drive->cylinder = 0xeb14; } else { drive->cylinder = 0x0000; + //drive->hd_state.accessed = 0; } + + memset(drive->data_buf, 0, sizeof(drive->data_buf)); + drive->transfer_index = 0; + // Send the reset signal to the connected device callbacks // channel->drives[0].reset(); // channel->drives[1].reset(); @@ -168,7 +310,7 @@ static void channel_reset(struct ide_channel * channel) { channel->error_reg.val = 0x01; // clear commands - channel->command_reg = 0x00; + channel->cmd_reg = 0x00; channel->ctrl_reg.irq_disable = 0; } @@ -184,22 +326,555 @@ static void channel_reset_complete(struct ide_channel * channel) { } +static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) { + channel->status.val = 0x41; // Error + ready + channel->error_reg.val = 0x04; // No idea... -static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - PrintDebug("IDE: Writing Command Port %x (val=%x)\n", port, *(uint8_t *)src); + ide_raise_irq(dev, channel); +} + + + + + + +/* ATAPI functions */ +#include "atapi.h" + +/* ATA functions */ +#include "ata.h" + + + +/* IO Operations */ +static int dma_read(struct vm_device * dev, struct ide_channel * channel) { + struct ide_drive * drive = get_selected_drive(channel); + struct ide_dma_prd prd_entry; + uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index); + int ret; + + + PrintDebug("PRD table address = %x\n", channel->dma_prd_addr); + + ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry); + + if (ret != sizeof(struct ide_dma_prd)) { + PrintError("Could not read PRD\n"); + return -1; + } + + PrintDebug("PRD Addr: %x, PDR Len: %d, EOT: %d\n", prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table); + + ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr, prd_entry.size, drive->data_buf); + + if (ret != prd_entry.size) { + PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret); + return -1; + } + + channel->status.busy = 0; + channel->status.ready = 1; + channel->status.data_req = 0; + channel->status.error = 0; + channel->status.seek_complete = 1; + + /* + drive->irq_flags.io_dir = 1; + drive->irq_flags.c_d = 1; + drive->irq_flags.rel = 0; + */ + + + // set DMA status + channel->dma_status.active = 0; + channel->dma_status.err = 1; + channel->dma_status.int_gen = 1; + + ide_raise_irq(dev, channel); + + return 0; +} + + +static int dma_write(struct vm_device * dev, struct ide_channel * channel) { + // unsupported + PrintError("DMA writes currently not supported\n"); return -1; } +/* + * This is an ugly ugly ugly way to differentiate between the first and second DMA channels + */ + +static int write_dma_port(ushort_t port_offset, void * src, uint_t length, struct vm_device * dev, struct ide_channel * channel); +static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel); + + +static int write_pri_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + PrintDebug("IDE: Writing PRI DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src); + return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[0])); +} + +static int write_sec_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + PrintDebug("IDE: Writing SEC DMA Port %x (%s) (val=%x)\n", port, dma_port_to_str(port & 0x7), *(uint32_t *)src); + return write_dma_port(port & 0x7, src, length, dev, &(ide->channels[1])); +} + + +static int read_pri_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + PrintDebug("IDE: Reading PRI DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7)); + return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[0])); +} + +static int read_sec_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + PrintDebug("IDE: Reading SEC DMA Port %x (%s)\n", port, dma_port_to_str(port & 0x7)); + return read_dma_port(port & 0x7, dst, length, dev, &(ide->channels[1])); +} + + +#define DMA_CMD_PORT 0x00 +#define DMA_STATUS_PORT 0x02 +#define DMA_PRD_PORT0 0x04 +#define DMA_PRD_PORT1 0x05 +#define DMA_PRD_PORT2 0x06 +#define DMA_PRD_PORT3 0x07 + + +static int write_dma_port(ushort_t port_offset, void * src, uint_t length, + struct vm_device * dev, struct ide_channel * channel) { + + switch (port_offset) { + case DMA_CMD_PORT: + channel->dma_cmd.val = *(uint8_t *)src; + + if (channel->dma_cmd.start == 0) { + channel->dma_tbl_index = 0; + } else { + channel->dma_status.active = 1; + + if (channel->dma_cmd.read == 1) { + // DMA Read + if (dma_read(dev, channel) == -1) { + PrintError("Failed DMA Read\n"); + return -1; + } + } else { + // DMA write + if (dma_write(dev, channel) == -1) { + PrintError("Failed DMA Write\n"); + return -1; + } + } + } + + break; + + case DMA_STATUS_PORT: + if (length != 1) { + PrintError("Invalid read length for DMA status port\n"); + return -1; + } + + channel->dma_status.val = *(uint8_t *)src; + break; + + case DMA_PRD_PORT0: + case DMA_PRD_PORT1: + case DMA_PRD_PORT2: + case DMA_PRD_PORT3: { + uint_t addr_index = port_offset & 0x3; + uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr); + int i = 0; + + if (addr_index + length > 4) { + PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length); + return -1; + } + + for (i = 0; i < length; i++) { + addr_buf[addr_index + i] = *((uint8_t *)src + i); + } + + PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr); + + break; + } + default: + PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset)); + return -1; + } + + return length; +} + + +static int read_dma_port(ushort_t port_offset, void * dst, uint_t length, + struct vm_device * dev, struct ide_channel * channel) { + + switch (port_offset) { + case DMA_CMD_PORT: + *(uint8_t *)dst = channel->dma_cmd.val; + break; + + case DMA_STATUS_PORT: + if (length != 1) { + PrintError("Invalid read length for DMA status port\n"); + return -1; + } + + *(uint8_t *)dst = channel->dma_status.val; + break; + + case DMA_PRD_PORT0: + case DMA_PRD_PORT1: + case DMA_PRD_PORT2: + case DMA_PRD_PORT3: { + uint_t addr_index = port_offset & 0x3; + uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr); + int i = 0; + + if (addr_index + length > 4) { + PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length); + return -1; + } + + for (i = 0; i < length; i++) { + *((uint8_t *)dst + i) = addr_buf[addr_index + i]; + } + + break; + } + default: + PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset)); + return -1; + } + + PrintDebug("\tval=%x\n", *(uint32_t *)dst); + + return length; +} + + + +static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + struct ide_channel * channel = get_selected_channel(ide, port); + struct ide_drive * drive = get_selected_drive(channel); + + if (length != 1) { + PrintError("Invalid Write Length on IDE command Port %x\n", port); + return -1; + } + + PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src); + + channel->cmd_reg = *(uint8_t *)src; + + switch (channel->cmd_reg) { + + case 0xa1: // ATAPI Identify Device Packet + if (drive->drive_type != IDE_CDROM) { + drive_reset(drive); + + // JRL: Should we abort here? + ide_abort_command(dev, channel); + } else { + + atapi_identify_device(drive); + + channel->error_reg.val = 0; + channel->status.val = 0x58; // ready, data_req, seek_complete + + ide_raise_irq(dev, channel); + } + break; + case 0xec: // Identify Device + if (drive->drive_type != IDE_DISK) { + drive_reset(drive); + + // JRL: Should we abort here? + ide_abort_command(dev, channel); + } else { + ata_identify_device(drive); + + channel->error_reg.val = 0; + channel->status.val = 0x58; + + ide_raise_irq(dev, channel); + } + break; + + case 0xa0: // ATAPI Command Packet + if (drive->drive_type != IDE_CDROM) { + ide_abort_command(dev, channel); + } + + drive->sector_count = 1; + + channel->status.busy = 0; + channel->status.write_fault = 0; + channel->status.data_req = 1; + channel->status.error = 0; + + // reset the data buffer... + drive->transfer_length = ATAPI_PACKET_SIZE; + drive->transfer_index = 0; + + break; + + case 0x20: // Read Sectors with Retry + case 0x21: // Read Sectors without Retry + if (ata_read_sectors(dev, channel) == -1) { + PrintError("Error reading sectors\n"); + return -1; + } + break; + + case 0x24: // Read Sectors Extended + if (ata_read_sectors_ext(dev, channel) == -1) { + PrintError("Error reading extended sectors\n"); + return -1; + } + break; + case 0xef: // Set Features + // Prior to this the features register has been written to. + // This command tells the drive to check if the new value is supported (the value is drive specific) + // Common is that bit0=DMA enable + // If valid the drive raises an interrupt, if not it aborts. + + // Do some checking here... + + channel->status.busy = 0; + channel->status.write_fault = 0; + channel->status.error = 0; + channel->status.ready = 1; + channel->status.seek_complete = 1; + + ide_raise_irq(dev, channel); + break; + + default: + PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg); + return -1; + } + + return length; +} + + static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - PrintDebug("IDE: Writing Data Port %x (val=%x)\n", port, *(uint8_t *)src); - return -1; + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + struct ide_channel * channel = get_selected_channel(ide, port); + struct ide_drive * drive = get_selected_drive(channel); + + // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n", + // port, *(uint32_t *)src, length); + + memcpy(drive->data_buf + drive->transfer_index, src, length); + drive->transfer_index += length; + + // Transfer is complete, dispatch the command + if (drive->transfer_index >= drive->transfer_length) { + switch (channel->cmd_reg) { + case 0x30: // Write Sectors + PrintError("Writing Data not yet implemented\n"); + return -1; + + case 0xa0: // ATAPI packet command + if (atapi_handle_packet(dev, channel) == -1) { + PrintError("Error handling ATAPI packet\n"); + return -1; + } + break; + default: + PrintError("Unhandld IDE Command %x\n", channel->cmd_reg); + return -1; + } + } + + return length; } -static int read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { - PrintDebug("IDE: Reading Data Port %x\n", port); - return -1; +static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) { + struct ide_drive * drive = get_selected_drive(channel); + int data_offset = drive->transfer_index % IDE_SECTOR_SIZE; + + + + if (drive->transfer_index >= drive->transfer_length) { + PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n", + drive->transfer_length, drive->transfer_index, + drive->transfer_index + length); + return -1; + } + + + if ((data_offset == 0) && (drive->transfer_index > 0)) { + drive->current_lba++; + + if (ata_read(dev, channel) == -1) { + PrintError("Could not read next disk sector\n"); + return -1; + } + } + + /* + PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n", + *(uint32_t *)(drive->data_buf + data_offset), + length, data_offset); + */ + memcpy(dst, drive->data_buf + data_offset, length); + + drive->transfer_index += length; + + if ((drive->transfer_index % IDE_SECTOR_SIZE) == 0) { + if (drive->transfer_index < drive->transfer_length) { + // An increment is complete, but there is still more data to be transferred... + PrintDebug("Integral Complete, still transferring more sectors\n"); + channel->status.data_req = 1; + + drive->irq_flags.c_d = 0; + } else { + PrintDebug("Final Sector Transferred\n"); + // This was the final read of the request + channel->status.data_req = 0; + + + drive->irq_flags.c_d = 1; + drive->irq_flags.rel = 0; + } + + channel->status.ready = 1; + drive->irq_flags.io_dir = 1; + channel->status.busy = 0; + + ide_raise_irq(dev, channel); + } + + + return length; +} + + + +static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) { + struct ide_drive * drive = get_selected_drive(channel); + int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE; + int req_offset = drive->transfer_index % drive->req_len; + + if (drive->cd_state.atapi_cmd != 0x28) { + PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len); + } + + if (drive->transfer_index >= drive->transfer_length) { + PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n", + drive->transfer_length, drive->transfer_index, + drive->transfer_index + length); + return -1; + } + + + + if ((data_offset == 0) && (drive->transfer_index > 0)) { + if (atapi_update_data_buf(dev, channel) == -1) { + PrintError("Could not update CDROM data buffer\n"); + return -1; + } + } + + memcpy(dst, drive->data_buf + data_offset, length); + + drive->transfer_index += length; + + + // Should the req_offset be recalculated here????? + if ((req_offset == 0) && (drive->transfer_index > 0)) { + if (drive->transfer_index < drive->transfer_length) { + // An increment is complete, but there is still more data to be transferred... + + channel->status.data_req = 1; + + drive->irq_flags.c_d = 0; + + // Update the request length in the cylinder regs + if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) { + PrintError("Could not update request length after completed increment\n"); + return -1; + } + } else { + // This was the final read of the request + channel->status.data_req = 0; + channel->status.ready = 1; + + drive->irq_flags.c_d = 1; + drive->irq_flags.rel = 0; + } + + drive->irq_flags.io_dir = 1; + channel->status.busy = 0; + + ide_raise_irq(dev, channel); + } + + return length; +} + + +static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) { + struct ide_drive * drive = get_selected_drive(channel); + + channel->status.busy = 0; + channel->status.ready = 1; + channel->status.write_fault = 0; + channel->status.seek_complete = 1; + channel->status.corrected = 0; + channel->status.error = 0; + + + memcpy(dst, drive->data_buf + drive->transfer_index, length); + drive->transfer_index += length; + + if (drive->transfer_index >= drive->transfer_length) { + channel->status.data_req = 0; + } + + return length; +} + + +static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + struct ide_channel * channel = get_selected_channel(ide, port); + struct ide_drive * drive = get_selected_drive(channel); + + // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length); + + if ((channel->cmd_reg == 0xec) || + (channel->cmd_reg == 0xa1)) { + return read_drive_id((uint8_t *)dst, length, dev, channel); + } + + if (drive->drive_type == IDE_CDROM) { + if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) { + PrintError("IDE: Could not read CD Data\n"); + return -1; + } + } else if (drive->drive_type == IDE_DISK) { + if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) { + PrintError("IDE: Could not read HD Data\n"); + return -1; + } + } else { + memset((uint8_t *)dst, 0, length); + } + + return length; } static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) { @@ -212,8 +887,7 @@ static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_de return -1; } - PrintDebug("IDE: Writing Standard Port %x (val=%x)\n", port, *(uint8_t *)src); - + PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src); switch (port) { // reset and interrupt enable @@ -238,21 +912,25 @@ static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_de case PRI_SECT_CNT_PORT: case SEC_SECT_CNT_PORT: - drive->sector_count = *(uint8_t *)src; + channel->drives[0].sector_count = *(uint8_t *)src; + channel->drives[1].sector_count = *(uint8_t *)src; break; case PRI_SECT_NUM_PORT: case SEC_SECT_NUM_PORT: - drive->sector_num = *(uint8_t *)src; - + channel->drives[0].sector_num = *(uint8_t *)src; + channel->drives[1].sector_num = *(uint8_t *)src; + break; case PRI_CYL_LOW_PORT: case SEC_CYL_LOW_PORT: - drive->cylinder_low = *(uint8_t *)src; + channel->drives[0].cylinder_low = *(uint8_t *)src; + channel->drives[1].cylinder_low = *(uint8_t *)src; break; case PRI_CYL_HIGH_PORT: case SEC_CYL_HIGH_PORT: - drive->cylinder_high = *(uint8_t *)src; + channel->drives[0].cylinder_high = *(uint8_t *)src; + channel->drives[1].cylinder_high = *(uint8_t *)src; break; case PRI_DRV_SEL_PORT: @@ -291,9 +969,8 @@ static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_dev PrintError("Invalid Read length on IDE port %x\n", port); return -1; } - - PrintDebug("IDE: Reading Standard Port %x\n", port); - + + PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port)); if ((port == PRI_ADDR_REG_PORT) || (port == SEC_ADDR_REG_PORT)) { @@ -362,6 +1039,8 @@ static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_dev return -1; } + PrintDebug("\tVal=%x\n", *(uint8_t *)dst); + return length; } @@ -377,6 +1056,12 @@ static void init_drive(struct ide_drive * drive) { memset(drive->model, 0, sizeof(drive->model)); + drive->transfer_index = 0; + drive->transfer_length = 0; + memset(drive->data_buf, 0, sizeof(drive->data_buf)); + + + drive->private_data = NULL; drive->cd_ops = NULL; } @@ -386,38 +1071,115 @@ static void init_channel(struct ide_channel * channel) { channel->error_reg.val = 0x01; channel->drive_head.val = 0x00; channel->status.val = 0x00; - channel->command_reg = 0x00; + channel->cmd_reg = 0x00; channel->ctrl_reg.val = 0x08; + + channel->dma_cmd.val = 0; + channel->dma_status.val = 0; + channel->dma_prd_addr = 0; + channel->dma_tbl_index = 0; + for (i = 0; i < 2; i++) { init_drive(&(channel->drives[i])); } } -static void init_ide_state(struct ide_internal * ide) { - int i; + +static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) { + PrintDebug("Interupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line); + + return 0; +} + +static int init_ide_state(struct vm_device * dev) { + struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + struct v3_pci_bar bars[6]; + struct pci_device * pci_dev = NULL; + int i, j; for (i = 0; i < 2; i++) { init_channel(&(ide->channels[i])); + + // JRL: this is a terrible hack... + ide->channels[i].irq = PRI_DEFAULT_IRQ + i; + + for (j = 0; j < 6; j++) { + bars[j].type = PCI_BAR_NONE; + } + + + bars[4].type = PCI_BAR_IO; + bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8); + bars[4].num_ports = 8; + + if (i == 0) { + bars[4].io_read = read_pri_dma_port; + bars[4].io_write = write_pri_dma_port; + } else { + bars[4].io_read = read_sec_dma_port; + bars[4].io_write = write_sec_dma_port; + } + + pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars, + pci_config_update, NULL, NULL, dev); + + if (pci_dev == NULL) { + PrintError("Failed to register IDE BUS %d with PCI\n", i); + return -1; + } + + ide->channels[i].pci_dev = pci_dev; + + pci_dev->config_header.vendor_id = 0x1095; + pci_dev->config_header.device_id = 0x0646; + pci_dev->config_header.revision = 0x8f07; + pci_dev->config_header.subclass = 0x01; + pci_dev->config_header.class = 0x01; + + pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i; + pci_dev->config_header.intr_pin = 1; } + + + + /* Register PIIX3 Busmaster PCI device */ + for (j = 0; j < 6; j++) { + bars[j].type = PCI_BAR_NONE; + } + + pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars, + NULL, NULL, NULL, dev); + + + ide->busmaster_pci = pci_dev; + + pci_dev->config_header.vendor_id = 0x8086; + pci_dev->config_header.device_id = 0x7010; + pci_dev->config_header.revision = 0x80; + pci_dev->config_header.subclass = 0x01; + pci_dev->config_header.class = 0x01; + + + return 0; } static int init_ide(struct vm_device * dev) { - struct ide_internal * ide = (struct ide_internal *)(dev->private_data); + //struct ide_internal * ide = (struct ide_internal *)(dev->private_data); PrintDebug("IDE: Initializing IDE\n"); - init_ide_state(ide); - + if (init_ide_state(dev) == -1) { + PrintError("Failed to initialize IDE state\n"); + return -1; + } - v3_dev_hook_io(dev, PRI_CTRL_PORT, - &read_port_std, &write_port_std); v3_dev_hook_io(dev, PRI_DATA_PORT, - &read_data_port, &write_data_port); + &ide_read_data_port, &write_data_port); v3_dev_hook_io(dev, PRI_FEATURES_PORT, &read_port_std, &write_port_std); v3_dev_hook_io(dev, PRI_SECT_CNT_PORT, @@ -433,12 +1195,8 @@ static int init_ide(struct vm_device * dev) { v3_dev_hook_io(dev, PRI_CMD_PORT, &read_port_std, &write_cmd_port); - - v3_dev_hook_io(dev, SEC_CTRL_PORT, - &read_port_std, &write_port_std); - v3_dev_hook_io(dev, SEC_DATA_PORT, - &read_data_port, &write_data_port); + &ide_read_data_port, &write_data_port); v3_dev_hook_io(dev, SEC_FEATURES_PORT, &read_port_std, &write_port_std); v3_dev_hook_io(dev, SEC_SECT_CNT_PORT, @@ -454,6 +1212,12 @@ static int init_ide(struct vm_device * dev) { v3_dev_hook_io(dev, SEC_CMD_PORT, &read_port_std, &write_cmd_port); + + v3_dev_hook_io(dev, PRI_CTRL_PORT, + &read_port_std, &write_port_std); + + v3_dev_hook_io(dev, SEC_CTRL_PORT, + &read_port_std, &write_port_std); v3_dev_hook_io(dev, SEC_ADDR_REG_PORT, @@ -482,11 +1246,11 @@ static struct vm_device_ops dev_ops = { }; -struct vm_device * v3_create_ide() { +struct vm_device * v3_create_ide(struct vm_device * pci) { struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal)); struct vm_device * device = v3_create_device("IDE", &dev_ops, ide); - // ide->pci = pci; + ide->pci = pci; PrintDebug("IDE: Creating IDE bus x 2\n"); @@ -521,6 +1285,11 @@ int v3_ide_register_cdrom(struct vm_device * ide_dev, strncpy(drive->model, dev_name, sizeof(drive->model) - 1); + while (strlen((char *)(drive->model)) < 40) { + strcat((char*)(drive->model), " "); + } + + drive->drive_type = IDE_CDROM; drive->cd_ops = ops; @@ -557,9 +1326,14 @@ int v3_ide_register_harddisk(struct vm_device * ide_dev, drive->drive_type = IDE_DISK; + drive->hd_state.accessed = 0; + drive->hd_ops = ops; drive->private_data = private_data; return 0; } + + +