X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?p=palacios.git;a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8259a.c;h=8019f82382c5ff3aea5895df2dec2d5230b77b49;hp=5e3397eaf7611c85069b5c43e9c43243772cca60;hb=cbe9bc8587261deb3aaee94a100594d88bc9765f;hpb=debb8d55e42ecf02a0967cbbed9247e707e99c7b

diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c
index 5e3397e..8019f82 100644
--- a/palacios/src/devices/8259a.c
+++ b/palacios/src/devices/8259a.c
@@ -18,12 +18,13 @@
  */
 
 
-#include <devices/8259a.h>
+
 #include <palacios/vmm_intr.h>
 #include <palacios/vmm_types.h>
 #include <palacios/vmm.h>
+#include <palacios/vmm_dev_mgr.h>
 
-#ifndef DEBUG_PIC
+#ifndef CONFIG_DEBUG_PIC
 #undef PrintDebug
 #define PrintDebug(fmt, args...)
 #endif
@@ -36,6 +37,10 @@ static const uint_t MASTER_PORT2 = 0x21;
 static const uint_t SLAVE_PORT1 = 0xA0;
 static const uint_t SLAVE_PORT2 = 0xA1;
 
+static const uint_t ELCR1_PORT = 0x4d0;
+static const uint_t ELCR2_PORT = 0x4d1;
+
+
 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
@@ -124,6 +129,11 @@ struct pic_internal {
     uchar_t master_isr;
     uchar_t slave_isr;
 
+    uchar_t master_elcr;
+    uchar_t slave_elcr;
+    uchar_t master_elcr_mask;
+    uchar_t slave_elcr_mask;
+
     uchar_t master_icw1;
     uchar_t master_icw2;
     uchar_t master_icw3;
@@ -252,7 +262,7 @@ static int pic_get_intr_number(void * private_data) {
 		// reset the irr
 		//state->master_irr &= ~(0x1 << i);
 		PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
-		irq= i + state->master_icw2;
+		irq = i + state->master_icw2;
 		break;
 	    }
 	} else {
@@ -260,7 +270,7 @@ static int pic_get_intr_number(void * private_data) {
 		//state->slave_isr |= (0x1 << (i - 8));
 		//state->slave_irr &= ~(0x1 << (i - 8));
 		PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
-		irq= (i - 8) + state->slave_icw2;
+		irq=  (i - 8) + state->slave_icw2;
 		break;
 	    }
 	}
@@ -296,11 +306,17 @@ static int pic_begin_irq(void * private_data, int irq) {
     if (irq <= 7) {
 	if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
 	    state->master_isr |= (0x1 << irq);
-	    state->master_irr &= ~(0x1 << irq);
+
+	    if (!(state->master_elcr & (0x1 << irq))) {
+		state->master_irr &= ~(0x1 << irq);
+	    }
 	}
     } else {
 	state->slave_isr |= (0x1 << (irq - 8));
-	state->slave_irr &= ~(0x1 << (irq - 8));
+
+	if (!(state->slave_elcr & (0x1 << irq))) {
+	    state->slave_irr &= ~(0x1 << (irq - 8));
+	}
     }
 
     return 0;
@@ -400,56 +416,56 @@ static int write_master_port1(ushort_t port, void * src, uint_t length, struct v
     PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
 
     if (length != 1) {
-	PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
-	return -1;
+        PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
+        return -1;
     }
-  
+
     if (IS_ICW1(cw)) {
 
-	PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
-    
-	state->master_icw1 = cw;
-	state->master_state = ICW2;
+        PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
 
-    } else if (state->master_state == READY) {
-	if (IS_OCW2(cw)) {
-	    // handle the EOI here
-	    struct ocw2 * cw2 =  (struct ocw2*)&cw;
+        state->master_icw1 = cw;
+        state->master_state = ICW2;
 
-	    PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
-      
-	    if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
-		// specific EOI;
-		state->master_isr &= ~(0x01 << cw2->level);
-	    } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
-		int i;
-		// Non-specific EOI
-		PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
-		for (i = 0; i < 8; i++) {
-		    if (state->master_isr & (0x01 << i)) {
-			state->master_isr &= ~(0x01 << i);
-			break;
-		    }
-		}	
-		PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
-	    } else {
-		PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
-		return -1;
-	    }
-
-	    state->master_ocw2 = cw;
-	} else if (IS_OCW3(cw)) {
-	    PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
-	    state->master_ocw3 = cw;
-	} else {
-	    PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
-	    PrintError("8259 PIC: CW=%x\n", cw);
-	    return -1;
-	}
+    } else if (state->master_state == READY) {
+        if (IS_OCW2(cw)) {
+            // handle the EOI here
+            struct ocw2 * cw2 =  (struct ocw2*)&cw;
+
+            PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
+
+            if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
+                // specific EOI;
+                state->master_isr &= ~(0x01 << cw2->level);
+            } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
+                int i;
+                // Non-specific EOI
+                PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
+                for (i = 0; i < 8; i++) {
+                    if (state->master_isr & (0x01 << i)) {
+                        state->master_isr &= ~(0x01 << i);
+                        break;
+                    }
+                }	
+                PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
+            } else {
+                PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
+                return -1;
+            }
+
+            state->master_ocw2 = cw;
+        } else if (IS_OCW3(cw)) {
+            PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
+            state->master_ocw3 = cw;
+        } else {
+            PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
+            PrintError("8259 PIC: CW=%x\n", cw);
+            return -1;
+        }
     } else {
-	PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
-	PrintError("8259 PIC: CW=%x\n", cw);
-	return -1;
+        PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
+        PrintError("8259 PIC: CW=%x\n", cw);
+        return -1;
     }
 
     return 1;
@@ -460,50 +476,51 @@ static int write_master_port2(ushort_t port, void * src, uint_t length, struct v
     uchar_t cw = *(uchar_t *)src;    
 
     PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
-  
+
     if (length != 1) {
-	PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
-	return -1;
+        PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
+        return -1;
     }
-    
+
     if (state->master_state == ICW2) {
-	struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+        struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
 
-	PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
-	state->master_icw2 = cw;
+        PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
+        state->master_icw2 = cw;
 
-	if (cw1->sngl == 0) {
-	    state->master_state = ICW3;
-	} else if (cw1->ic4 == 1) {
-	    state->master_state = ICW4;
-	} else {
-	    state->master_state = READY;
-	}
+        if (cw1->sngl == 0) {
+            state->master_state = ICW3;
+        } else if (cw1->ic4 == 1) {
+            state->master_state = ICW4;
+        } else {
+            state->master_state = READY;
+        }
 
     } else if (state->master_state == ICW3) {
-	struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+        struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
 
-	PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
+        PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
 
-	state->master_icw3 = cw;
+        state->master_icw3 = cw;
 
-	if (cw1->ic4 == 1) {
-	    state->master_state = ICW4;
-	} else {
-	    state->master_state = READY;
-	}
+        if (cw1->ic4 == 1) {
+            state->master_state = ICW4;
+        } else {
+            state->master_state = READY;
+        }
 
     } else if (state->master_state == ICW4) {
-	PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
-	state->master_icw4 = cw;
-	state->master_state = READY;
-    } else if (state->master_state == READY) {
-	PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
-	state->master_imr = cw;
+        PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
+        state->master_icw4 = cw;
+        state->master_state = READY;
+    } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
+        PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
+        state->master_imr = cw;
     } else {
-	// error
-	PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
-	return -1;
+        // error
+        PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n", 
+                state->master_state);
+        return -1;
     }
 
     return 1;
@@ -531,7 +548,7 @@ static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm
 	    struct ocw2 * cw2 =  (struct ocw2 *)&cw;
 
 	    PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
-      
+
 	    if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
 		// specific EOI;
 		state->slave_isr &= ~(0x01 << cw2->level);
@@ -544,7 +561,7 @@ static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm
 			state->slave_isr &= ~(0x01 << i);
 			break;
 		    }
-		}	
+		}
 		PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
 	    } else {
 		PrintError("8259 PIC: Command not handled or invalid  (wr_Slave1)\n");
@@ -575,48 +592,48 @@ static int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm
     PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
 
     if (length != 1) {
-	PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
-	return -1;
+        PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
+        return -1;
     }
 
     if (state->slave_state == ICW2) {
-	struct icw1 * cw1 =  (struct icw1 *)&(state->master_icw1);
+        struct icw1 * cw1 =  (struct icw1 *)&(state->master_icw1);
 
-	PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
+        PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
 
-	state->slave_icw2 = cw;
+        state->slave_icw2 = cw;
 
-	if (cw1->sngl == 0) {
-	    state->slave_state = ICW3;
-	} else if (cw1->ic4 == 1) {
-	    state->slave_state = ICW4;
-	} else {
-	    state->slave_state = READY;
-	}
+        if (cw1->sngl == 0) {
+            state->slave_state = ICW3;
+        } else if (cw1->ic4 == 1) {
+            state->slave_state = ICW4;
+        } else {
+            state->slave_state = READY;
+        }
 
     } else if (state->slave_state == ICW3) {
-	struct icw1 * cw1 =  (struct icw1 *)&(state->master_icw1);
+        struct icw1 * cw1 =  (struct icw1 *)&(state->master_icw1);
 
-	PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
+        PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
 
-	state->slave_icw3 = cw;
+        state->slave_icw3 = cw;
 
-	if (cw1->ic4 == 1) {
-	    state->slave_state = ICW4;
-	} else {
-	    state->slave_state = READY;
-	}
+        if (cw1->ic4 == 1) {
+            state->slave_state = ICW4;
+        } else {
+            state->slave_state = READY;
+        }
 
     } else if (state->slave_state == ICW4) {
-	PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
-	state->slave_icw4 = cw;
-	state->slave_state = READY;
-    } else if (state->slave_state == READY) {
-	PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
-	state->slave_imr = cw;
+        PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
+        state->slave_icw4 = cw;
+        state->slave_state = READY;
+    } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
+        PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
+        state->slave_imr = cw;
     } else {
-	PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
-	return -1;
+        PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
+        return -1;
     }
 
     return 1;
@@ -625,17 +642,97 @@ static int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm
 
 
 
+static int read_elcr_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
+    struct pic_internal * state = (struct pic_internal*)dev->private_data;
+    
+    if (length != 1) {
+	PrintError("ELCR read of invalid length %d\n", length);
+	return -1;
+    }
 
+    if (port == ELCR1_PORT) {
+	// master
+	*(uint8_t *)dst = state->master_elcr;
+    } else if (port == ELCR2_PORT) {
+	*(uint8_t *)dst = state->slave_elcr;
+    } else {
+	PrintError("Invalid port %x\n", port);
+	return -1;
+    }
 
+    return length;
+}
 
 
-static int pic_init(struct vm_device * dev) {
+static int write_elcr_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
     struct pic_internal * state = (struct pic_internal*)dev->private_data;
+    
+    if (length != 1) {
+	PrintError("ELCR read of invalid length %d\n", length);
+	return -1;
+    }
+
+    if (port == ELCR1_PORT) {
+	// master
+	state->master_elcr  = (*(uint8_t *)src) & state->master_elcr_mask;
+    } else if (port == ELCR2_PORT) {
+	state->slave_elcr  = (*(uint8_t *)src) & state->slave_elcr_mask;
+    } else {
+	PrintError("Invalid port %x\n", port);
+	return -1;
+    }
+
+    return length;
+}
+
+
 
-    v3_register_intr_controller(dev->vm, &intr_ops, state);
+
+
+
+static int pic_free(struct vm_device * dev) {
+    v3_dev_unhook_io(dev, MASTER_PORT1);
+    v3_dev_unhook_io(dev, MASTER_PORT2);
+    v3_dev_unhook_io(dev, SLAVE_PORT1);
+    v3_dev_unhook_io(dev, SLAVE_PORT2);
+
+    return 0;
+}
+
+
+
+
+
+
+
+static struct v3_device_ops dev_ops = {
+    .free = pic_free,
+    .reset = NULL,
+    .start = NULL,
+    .stop = NULL,
+};
+
+
+
+static int pic_init(struct guest_info * vm, void * cfg_data) {
+    struct pic_internal * state = NULL;
+    state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
+    V3_ASSERT(state != NULL);
+
+    struct vm_device * dev = v3_allocate_device("8259A", &dev_ops, state);
+
+    if (v3_attach_device(vm, dev) == -1) {
+	PrintError("Could not attach device %s\n", "8259A");
+	return -1;
+    }
+
+
+    v3_register_intr_controller(vm, &intr_ops, state);
 
     state->master_irr = 0;
     state->master_isr = 0;
+    state->master_elcr = 0;
+    state->master_elcr_mask = 0xf8;
     state->master_icw1 = 0;
     state->master_icw2 = 0;
     state->master_icw3 = 0;
@@ -648,6 +745,8 @@ static int pic_init(struct vm_device * dev) {
 
     state->slave_irr = 0;
     state->slave_isr = 0;
+    state->slave_elcr = 0;
+    state->slave_elcr_mask = 0xde;
     state->slave_icw1 = 0;
     state->slave_icw2 = 0;
     state->slave_icw3 = 0;
@@ -663,40 +762,13 @@ static int pic_init(struct vm_device * dev) {
     v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
     v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
 
-    return 0;
-}
-
 
-static int pic_deinit(struct vm_device * dev) {
-    v3_dev_unhook_io(dev, MASTER_PORT1);
-    v3_dev_unhook_io(dev, MASTER_PORT2);
-    v3_dev_unhook_io(dev, SLAVE_PORT1);
-    v3_dev_unhook_io(dev, SLAVE_PORT2);
+    v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
+    v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
 
     return 0;
 }
 
 
 
-
-
-
-
-static struct vm_device_ops dev_ops = {
-    .init = pic_init,
-    .deinit = pic_deinit,
-    .reset = NULL,
-    .start = NULL,
-    .stop = NULL,
-};
-
-
-struct vm_device * v3_create_pic() {
-    struct pic_internal * state = NULL;
-    state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
-    V3_ASSERT(state != NULL);
-
-    struct vm_device *device = v3_create_device("8259A", &dev_ops, state);
-
-    return device;
-}
+device_register("8259A", pic_init);