--- /dev/null
+/*
+ * This file is part of the Palacios Virtual Machine Monitor developed
+ * by the V3VEE Project with funding from the United States National
+ * Science Foundation and the Department of Energy.
+ *
+ * The V3VEE Project is a joint project between Northwestern University
+ * and the University of New Mexico. You can find out more at
+ * http://www.v3vee.org
+ *
+ * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
+ * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
+ * All rights reserved.
+ *
+ * Author: Jack Lange <jarusl@cs.northwestern.edu>
+ *
+ * This is free software. You are permitted to use,
+ * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
+ */
+
+#include <palacios/vmm_types.h>
+
+
+#ifdef __V3_32BIT__
+
+void __inline__ v3_cpuid(uint_t target, uint_t * eax, uint_t * ebx, uint_t * ecx, uint_t * edx) {
+ __asm__ __volatile__ (
+ "pushl %%ebx\n\t"
+ "cpuid\n\t"
+ "movl %%ebx, %%esi\n\t"
+ "popl %%ebx\n\t"
+ : "=a" (*eax), "=S" (*ebx), "=c" (*ecx), "=d" (*edx)
+ : "a" (target)
+ );
+ return;
+}
+
+
+
+
+void __inline__ v3_set_msr(uint_t msr, uint_t high_byte, uint_t low_byte) {
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (msr), "d" (high_byte), "a" (low_byte)
+ );
+
+
+}
+
+
+
+void __inline__ v3_get_msr(uint_t msr, uint_t * high_byte, uint_t * low_byte) {
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=d" (*high_byte), "=a" (*low_byte)
+ : "c" (msr)
+ );
+}
+
+
+
+void __inline__ v3_enable_ints() {
+ __asm__ __volatile__ ("sti");
+}
+
+void __inline__ v3_disable_ints() {
+ __asm__ __volatile__ ("cli");
+}
+
+#endif
#include <palacios/vmm_decoder.h>
#include <palacios/vmm_string.h>
+#include <palacios/vmm_lowlevel.h>
-extern uint_t cpuid_ecx(uint_t op);
-extern uint_t cpuid_edx(uint_t op);
-extern void Get_MSR(uint_t MSR, uint_t * high_byte, uint_t * low_byte);
-extern void Set_MSR(uint_t MSR, uint_t high_byte, uint_t low_byte);
extern uint_t launch_svm(vmcb_t * vmcb_addr);
extern void safe_svm_launch(vmcb_t * vmcb_addr, struct v3_gprs * gprs);
extern uint_t Get_CR3();
-extern void DisableInts();
-extern void EnableInts();
ullong_t tmp_tsc;
- EnableInts();
+ v3_enable_ints();
CLGI();
// PrintDebug("SVM Entry to rip=%x...\n", info->rip);
#if 1
// Dinda
-
- uint_t ret;
uint_t vm_cr_low = 0, vm_cr_high = 0;
+ uint_t eax = 0, ebx = 0, ecx = 0, edx = 0;
-
- ret = cpuid_ecx(CPUID_FEATURE_IDS);
+ v3_cpuid(CPUID_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
- PrintDebug("CPUID_FEATURE_IDS_ecx=0x%x\n",ret);
+ PrintDebug("CPUID_FEATURE_IDS_ecx=0x%x\n", ecx);
- if ((ret & CPUID_FEATURE_IDS_ecx_svm_avail) == 0) {
+ if ((ecx & CPUID_FEATURE_IDS_ecx_svm_avail) == 0) {
PrintDebug("SVM Not Available\n");
return 0;
} else {
- Get_MSR(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
+ v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
- PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n",vm_cr_high,vm_cr_low);
+ PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
PrintDebug("SVM is available but is disabled.\n");
- ret = cpuid_edx(CPUID_SVM_REV_AND_FEATURE_IDS);
+ v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
- PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n",ret);
+ PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n", edx);
- if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
+ if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
PrintDebug("SVM BIOS Disabled, not unlockable\n");
} else {
PrintDebug("SVM is locked with a key\n");
} else {
PrintDebug("SVM is available and enabled.\n");
- ret = cpuid_edx(CPUID_SVM_REV_AND_FEATURE_IDS);
+ v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
- PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n",ret);
+ PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n", edx);
- if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
+ if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
PrintDebug("SVM Nested Paging not supported\n");
} else {
PrintDebug("SVM Nested Paging supported\n");
}
#else
-
- uint_t ret = cpuid_ecx(CPUID_FEATURE_IDS);
+ uint_t eax = 0, ebx = 0, ecx = 0, edx = 0;
uint_t vm_cr_low = 0, vm_cr_high = 0;
+ v3_cpuid(CPUID_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
- if ((ret & CPUID_FEATURE_IDS_ecx_svm_avail) == 0) {
+ if ((ecx & CPUID_FEATURE_IDS_ecx_svm_avail) == 0) {
PrintDebug("SVM Not Available\n");
return 0;
}
- Get_MSR(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
+ v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
- PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n",vm_cr_high,vm_cr_low);
+ PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
// this part is clearly wrong, since the np bit is in
// edx, not ecx
- if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 1) {
+ if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 1) {
PrintDebug("Nested Paging not supported\n");
} else {
PrintDebug("Nested Paging supported\n");
return 1;
}
- ret = cpuid_edx(CPUID_SVM_REV_AND_FEATURE_IDS);
+ v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
- if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
+ if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
PrintDebug("SVM BIOS Disabled, not unlockable\n");
} else {
PrintDebug("SVM is locked with a key\n");
}
static int has_svm_nested_paging() {
- uint32_t ret;
+ uint_t eax = 0, ebx = 0, ecx = 0, edx = 0;
- ret = cpuid_edx(CPUID_SVM_REV_AND_FEATURE_IDS);
+ v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
- //PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n",ret);
+ //PrintDebug("CPUID_FEATURE_IDS_edx=0x%x\n", edx);
- if ((ret & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
+ if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
PrintDebug("SVM Nested Paging not supported\n");
return 0;
} else {
// Enable SVM on the CPU
- Get_MSR(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
+ v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
msr.e_reg.low |= EFER_MSR_svm_enable;
- Set_MSR(EFER_MSR, 0, msr.e_reg.low);
+ v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
PrintDebug("SVM Enabled\n");
msr.r_reg = (addr_t)host_state;
PrintDebug("Host State being saved at %x\n", (addr_t)host_state);
- Set_MSR(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
+ v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);