updated assembly to build in 64 bit mode

IMPORTANT 64 bit v3_svm_launch is not implemented

diff --git a/palacios/include/palacios/vmm_lowlevel.h b/palacios/include/palacios/vmm_lowlevel.h
index 4719cce..ea32b23 100644 (file)
--- a/palacios/include/palacios/vmm_lowlevel.h
+++ b/palacios/include/palacios/vmm_lowlevel.h
@@ -22,7 +22,7 @@
 
 #ifdef __V3_32BIT__
 
-void __inline__ v3_cpuid(uint_t target, uint_t * eax, uint_t * ebx, uint_t * ecx, uint_t * edx) {
+void __inline__ v3_cpuid(uint_t target, addr_t * eax, addr_t * ebx, addr_t * ecx, addr_t * edx) {
   __asm__ __volatile__ (
                        "pushl %%ebx\n\t"
                        "cpuid\n\t"
@@ -34,7 +34,21 @@ void __inline__ v3_cpuid(uint_t target, uint_t * eax, uint_t * ebx, uint_t * ecx
   return;
 }
 
+#elif __V3_64BIT__
 
+void __inline__ v3_cpuid(uint_t target, addr_t * eax, addr_t * ebx, addr_t * ecx, addr_t * edx) {
+  __asm__ __volatile__ (
+                       "pushq %%rbx\n\t"
+                       "cpuid\n\t"
+                       "movq %%rbx, %%rsi\n\t"
+                       "popq %%rbx\n\t"
+                       : "=a" (*eax), "=S" (*ebx), "=c" (*ecx), "=d" (*edx)
+                       : "a" (target)
+                       );
+  return;
+}
+
+#endif
 
 
 void __inline__ v3_set_msr(uint_t msr, uint_t high_byte, uint_t low_byte) {
@@ -67,4 +81,3 @@ void __inline__ v3_disable_ints() {
   __asm__ __volatile__ ("cli");
 }
 
-#endif

diff --git a/palacios/src/palacios/svm.c b/palacios/src/palacios/svm.c
index 1aca55b..bb0e217 100644 (file)
--- a/palacios/src/palacios/svm.c
+++ b/palacios/src/palacios/svm.c
@@ -372,7 +372,7 @@ int v3_is_svm_capable() {
 #if 1
   // Dinda
   uint_t vm_cr_low = 0, vm_cr_high = 0;
-  uint_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+  addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 
   v3_cpuid(CPUID_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
   
@@ -420,7 +420,7 @@ int v3_is_svm_capable() {
 
 #else
   uint_t eax = 0, ebx = 0, ecx = 0, edx = 0;
-  uint_t vm_cr_low = 0, vm_cr_high = 0;
+  addr_t vm_cr_low = 0, vm_cr_high = 0;
 
   v3_cpuid(CPUID_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
 
@@ -462,7 +462,7 @@ int v3_is_svm_capable() {
 }
 
 static int has_svm_nested_paging() {
-  uint_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+  addr_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 
   v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
       

diff --git a/palacios/src/palacios/svm_lowlevel.S b/palacios/src/palacios/svm_lowlevel.S
index 9b201b1..3a17df4 100644 (file)
--- a/palacios/src/palacios/svm_lowlevel.S
+++ b/palacios/src/palacios/svm_lowlevel.S
@@ -49,21 +49,6 @@
        popl    %eax;
 
 
-
-#elif __V3_64BIT__
-
-#endif
-
-
-v3_stgi:
-       stgi;
-       ret;
-
-v3_clgi:
-       clgi;
-       ret;
-       
-       
 v3_svm_launch:
        push    %ebp;
        movl    %esp, %ebp;
@@ -92,3 +77,55 @@ v3_svm_launch:
        popf;
        pop     %ebp;
        ret
+
+
+
+#elif __V3_64BIT__
+
+#define Save_SVM_Registers(location)   \
+       pushl   %eax;                   \
+       movl    location, %eax;         \
+       movl    %edi, (%eax);           \
+       movl    %esi, 8(%eax);          \
+       movl    %ebp, 16(%eax);         \
+       movl    $0, 24(%eax);           \
+       movl    %ebx, 32(%eax);         \
+       movl    %edx, 40(%eax);         \
+       movl    %ecx, 48(%eax);         \
+       pushl   %ebx;                   \
+       movl    4(%esp), %ebx;          \
+       movl    %ebx, 56(%eax);         \
+       popl    %ebx;                   \
+       popl    %eax;                   
+       
+
+#define Restore_SVM_Registers(location) \
+       pushl   %eax;                   \
+       movl    location, %eax;         \
+       movl    (%eax), %edi;           \
+       movl    8(%eax), %esi;          \
+       movl    16(%eax), %ebp;         \
+       movl    32(%eax), %ebx;         \
+       movl    40(%eax), %edx;         \
+       movl    48(%eax), %ecx;         \
+       popl    %eax;
+
+
+
+v3_svm_launch:
+
+       ret
+
+
+#endif
+
+
+v3_stgi:
+       stgi;
+       ret;
+
+v3_clgi:
+       clgi;
+       ret;
+       
+