X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fpalacios%2Fvmx.c;h=f0823b4cfe5c6d099fd8950fe8351985aefc4487;hb=60ad6a41c6d0ee08ed689e8505eb0c3df0c2a289;hp=ba5734b385e67914174eadd38ec96347755798a8;hpb=e70e95962c26832628d586e07f9cd1a2e1852d72;p=palacios.git diff --git a/palacios/src/palacios/vmx.c b/palacios/src/palacios/vmx.c index ba5734b..f0823b4 100644 --- a/palacios/src/palacios/vmx.c +++ b/palacios/src/palacios/vmx.c @@ -7,927 +7,1435 @@ * and the University of New Mexico. You can find out more at * http://www.v3vee.org * - * Copyright (c) 2008, Peter Dinda - * Copyright (c) 2008, Jack Lange - * Copyright (c) 2008, The V3VEE Project + * Copyright (c) 2011, Jack Lange + * Copyright (c) 2011, The V3VEE Project * All rights reserved. * - * Author: Peter Dinda - * Jack Lange + * Author: Jack Lange * * This is free software. You are permitted to use, * redistribute, and modify it as specified in the file "V3VEE_LICENSE". */ -/* Eventually we want to get rid of these */ - -#include -#include -#include -/* ** */ - #include -#include #include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef V3_CONFIG_CHECKPOINT +#include +#endif -extern void Get_MSR(unsigned int msr, uint_t * high, uint_t * low); -extern void Set_MSR(unsigned int msr, uint_t high, uint_t low); -extern int Enable_VMX(ullong_t regionPtr); -extern int cpuid_ecx(unsigned int op); -extern int Launch_VM(ullong_t vmcsPtr, uint_t eip); +#include +#include +#include -#define NUMPORTS 65536 +#ifdef V3_CONFIG_MEM_TRACK +#include +#endif +#ifndef V3_CONFIG_DEBUG_VMX +#undef PrintDebug +#define PrintDebug(fmt, args...) +#endif -#define VMXASSIST_INFO_PORT 0x0e9 -#define ROMBIOS_PANIC_PORT 0x400 -#define ROMBIOS_PANIC_PORT2 0x401 -#define ROMBIOS_INFO_PORT 0x402 -#define ROMBIOS_DEBUG_PORT 0x403 +/* These fields contain the hardware feature sets supported by the local CPU */ +static struct vmx_hw_info hw_info; -extern struct vmm_os_hooks * os_hooks; +extern v3_cpu_arch_t v3_mach_type; +static addr_t host_vmcs_ptrs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0}; -static struct VM theVM; +extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs); +extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs); -static uint_t GetLinearIP(struct VM *vm) -{ - if (vm->state==VM_VMXASSIST_V8086_BIOS || vm->state==VM_VMXASSIST_V8086) { - return vm->vmcs.guestStateArea.cs.baseAddr + vm->vmcs.guestStateArea.rip; - } else { - return vm->vmcs.guestStateArea.rip; - } -} +static int inline check_vmcs_write(vmcs_field_t field, addr_t val) { + int ret = 0; + ret = vmcs_write(field, val); + + if (ret != VMX_SUCCESS) { + PrintError(VM_NONE, VCORE_NONE, "VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret); + return 1; + } + + + -static void VMXPanic() -{ - while (1) {} + return 0; } +static int inline check_vmcs_read(vmcs_field_t field, void * val) { + int ret = 0; -#define MAX_CODE 512 -#define INSTR_OFFSET_START 17 -#define NOP_SEQ_LEN 10 -#define INSTR_OFFSET_END (INSTR_OFFSET_START+NOP_SEQ_LEN-1) -#define TEMPLATE_CODE_LEN 35 + ret = vmcs_read(field, val); -uint_t oldesp=0; -uint_t myregs=0; + if (ret != VMX_SUCCESS) { + PrintError(VM_NONE, VCORE_NONE, "VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret); + } -// simply execute the instruction that is faulting and return -static int ExecFaultingInstructionInVMM(struct VM *vm) -{ - uint_t address = GetLinearIP(vm); - myregs = (uint_t)&(vm->registers); - + return ret; +} - PrintTrace("About the execute faulting instruction!\n"); - PrintTrace("Instruction is:\n"); - PrintTraceMemDump((void*)(address),vm->vmcs.exitInfoFields.instrLength); - - PrintTrace("The template code is:\n"); - PrintTraceMemDump(&&template_code,TEMPLATE_CODE_LEN); - // clone the template code - //memcpy(&&template_code,code,MAX_CODE); - - // clean up the nop field - memset(&&template_code+INSTR_OFFSET_START,*((uchar_t *)(&&template_code+0)),NOP_SEQ_LEN); - // overwrite the nops with the faulting instruction - memcpy(&&template_code+INSTR_OFFSET_START, (void*)(address),vm->vmcs.exitInfoFields.instrLength); - - PrintTrace("Finished modifying the template code, which now is:\n"); - PrintTraceMemDump(&&template_code,TEMPLATE_CODE_LEN); - - PrintTrace("Now entering modified template code\n"); - - - template_code: - // Template code stores current registers, - // restores registers, has a landing pad of noops - // that will be modified, restores current regs, and then returns - // - // Note that this currently ignores cr0, cr3, cr4, dr7, rsp, rip, and rflags - // it also blythly assumes it can exec the instruction in protected mode - // - __asm__ __volatile__ ("nop\n" // for cloning purposes (1 byte) - "pusha\n" // push our current regs onto the current stack (1 byte) - "movl %0, %%eax\n" // Get oldesp location (5 bytes) - "movl %%esp, (%%eax)\n" // store the current stack pointer in oldesp (2 bytes) - "movl %1, %%eax\n" // Get regs location (5 bytes) - "movl (%%eax), %%esp\n" // point esp at regs (2 bytes) - "popa\n" // now we have the VM registers restored (1 byte) - "nop\n" // now we execute the actual instruction (1 byte x 10) - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - "nop\n" // now we execute the actual instruction - // need to copy back to the VM registers! - "movl %0, %%eax\n" // recapture oldesp location (5 bytes) - "movl (%%eax), %%esp\n" // now we'll get our esp back from oldesp (2 bytes) - "popa\n" // and restore our GP regs and we're done (1 byte) - : "=m"(oldesp) - : "m"(myregs) - ); - - PrintTrace("Survived executing the faulting instruction and returning.\n"); - vm->vmcs.guestStateArea.rip += vm->vmcs.exitInfoFields.instrLength; +static addr_t allocate_vmcs() { + void *temp; + struct vmcs_data * vmcs_page = NULL; - return 0; + PrintDebug(VM_NONE, VCORE_NONE, "Allocating page\n"); + temp = V3_AllocPages(1); // need not be shadow-safe, not exposed to guest + if (!temp) { + PrintError(VM_NONE, VCORE_NONE, "Cannot allocate VMCS\n"); + return -1; + } + vmcs_page = (struct vmcs_data *)V3_VAddr(temp); + memset(vmcs_page, 0, 4096); + + vmcs_page->revision = hw_info.basic_info.revision; + PrintDebug(VM_NONE, VCORE_NONE, "VMX Revision: 0x%x\n", vmcs_page->revision); + + return (addr_t)V3_PAddr((void *)vmcs_page); } -int is_vmx_capable() { - uint_t ret; - union VMX_MSR featureMSR; - - ret = cpuid_ecx(1); - if (ret & CPUID_1_ECX_VTXFLAG) { - Get_MSR(IA32_FEATURE_CONTROL_MSR, &featureMSR.regs.high, &featureMSR.regs.low); +#if 0 +static int debug_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * src, void * priv_data) { + struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer); + V3_Print(core->vm_info, core, "\n\nEFER READ (val = %p)\n", (void *)efer->value); + + v3_print_guest_state(core); + v3_print_vmcs(); - PrintTrace("MSRREGlow: 0x%.8x\n", featureMSR.regs.low); - if ((featureMSR.regs.low & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) { - PrintDebug("VMX is locked -- enable in the BIOS\n"); - return 0; - } - } else { - PrintDebug("VMX not supported on this cpu\n"); + src->value = efer->value; return 0; - } +} + +static int debug_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) { + struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer); + V3_Print(core->vm_info, core, "\n\nEFER WRITE (old_val = %p) (new_val = %p)\n", (void *)efer->value, (void *)src.value); + + v3_print_guest_state(core); + v3_print_vmcs(); - return 1; + efer->value = src.value; + return 0; } +#endif -VmxOnRegion * Init_VMX() { - uint_t ret; - VmxOnRegion * region = NULL; +static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) { + int vmx_ret = 0; + /* Get Available features */ + struct vmx_pin_ctrls avail_pin_ctrls; + avail_pin_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.pin_ctrls)); + /* ** */ - region = CreateVmxOnRegion(); + // disable global interrupts for vm state initialization + v3_disable_ints(); - ret = Enable_VMX((ullong_t)((uint_t)region)); - if (ret == 0) { - PrintDebug("VMX Enabled\n"); - } else { - PrintDebug("VMX failure (ret = %d)\n", ret); - } + PrintDebug(core->vm_info, core, "Loading VMCS\n"); + vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys); + vmx_state->state = VMX_UNLAUNCHED; - theVM.vmxonregion = region; + if (vmx_ret != VMX_SUCCESS) { + PrintError(core->vm_info, core, "VMPTRLD failed\n"); + return -1; + } - return region; -} -extern uint_t VMCS_CLEAR(); -extern uint_t VMCS_LOAD(); -extern uint_t VMCS_STORE(); -extern uint_t VMCS_LAUNCH(); -extern uint_t VMCS_RESUME(); -extern uint_t Init_VMCS_HostState(); -extern uint_t Init_VMCS_GuestState(); - -void SetCtrlBitsCorrectly(int msrno, int vmcsno) -{ - uint_t reserved =0; - union VMX_MSR msr; - - PrintTrace("SetCtrlBitsCorrectly(%x,%x)\n", msrno, vmcsno); - Get_MSR(msrno, &msr.regs.high, &msr.regs.low); - PrintTrace("MSR %x = %x : %x \n", msrno, msr.regs.high, msr.regs.low); - reserved = msr.regs.low; - reserved &= msr.regs.high; - VMCS_WRITE(vmcsno, &reserved); -} + /*** Setup default state from HW ***/ + vmx_state->pin_ctrls.value = hw_info.pin_ctrls.def_val; + vmx_state->pri_proc_ctrls.value = hw_info.proc_ctrls.def_val; + vmx_state->exit_ctrls.value = hw_info.exit_ctrls.def_val; + vmx_state->entry_ctrls.value = hw_info.entry_ctrls.def_val; + vmx_state->sec_proc_ctrls.value = hw_info.sec_proc_ctrls.def_val; -void SetCRBitsCorrectly(int msr0no, int msr1no, int vmcsno) -{ - uint_t reserved =0; - union VMX_MSR msr0, msr1; + /* Print Control MSRs */ + V3_Print(core->vm_info, core, "CR0 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr0.req_val, (void *)(addr_t)hw_info.cr0.req_mask); + V3_Print(core->vm_info, core, "CR4 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr4.req_val, (void *)(addr_t)hw_info.cr4.req_mask); - PrintTrace("SetCRBitsCorrectly(%x,%x,%x)\n",msr0no,msr1no,vmcsno); - Get_MSR(msr0no, &msr0.regs.high, &msr0.regs.low); - Get_MSR(msr1no, &msr1.regs.high, &msr1.regs.low); - PrintTrace("MSR %x = %x, %x = %x \n", msr0no, msr0.regs.low, msr1no, msr1.regs.low); - reserved = msr0.regs.low; - reserved &= msr1.regs.low; - VMCS_WRITE(vmcsno, &reserved); -} -extern int Get_CR2(); -extern int vmRunning; + /******* Setup Host State **********/ + /* Cache GDTR, IDTR, and TR in host struct */ -static int PanicUnhandledVMExit(struct VM *vm) -{ - PrintInfo("Panicking due to VMExit with reason %u\n", vm->vmcs.exitInfoFields.reason); - PrintTrace("Panicking due to VMExit with reason %u\n", vm->vmcs.exitInfoFields.reason); - PrintTrace_VMCS_ALL(); - PrintTrace_VMX_Regs(&(vm->registers)); - VMXPanic(); - return 0; -} + /********** Setup VMX Control Fields ***********/ -static int HandleVMPrintsAndPanics(struct VM *vm, uint_t port, uint_t data) -{ - if (port==VMXASSIST_INFO_PORT && - (vm->state == VM_VMXASSIST_STARTUP || - vm->state == VM_VMXASSIST_V8086_BIOS || - vm->state == VM_VMXASSIST_V8086)) { - // Communication channel from VMXAssist - PrintTrace("VMXASSIST Output Port\n"); - PrintDebug("%c",data&0xff); - return 1; - } - - if ((port==ROMBIOS_PANIC_PORT || - port==ROMBIOS_PANIC_PORT2 || - port==ROMBIOS_DEBUG_PORT || - port==ROMBIOS_INFO_PORT) && - (vm->state==VM_VMXASSIST_V8086_BIOS)) { - // rombios is communicating - PrintTrace("ROMBIOS Output Port\n"); - // PrintDebug("%c",data&0xff); - return 1; - } + /* Add external interrupts, NMI exiting, and virtual NMI */ + vmx_state->pin_ctrls.nmi_exit = 1; + vmx_state->pin_ctrls.virt_nmi = 1; + vmx_state->pin_ctrls.ext_int_exit = 1; - if (port==BOOT_STATE_CARD_PORT && vm->state==VM_VMXASSIST_V8086_BIOS) { - // rombios is sending something to the display card - PrintTrace("Hex Display: 0x%x\n",data&0xff); - return 1; - } - return 0; -} -static int HandleInOutExit(struct VM *vm) -{ - uint_t address; - - struct VMCSExitInfoFields *exitinfo = &(vm->vmcs.exitInfoFields); - struct VMExitIOQual * qual = (struct VMExitIOQual *)&(vm->vmcs.exitInfoFields.qualification); - struct VMXRegs *regs = &(vm->registers); - - address=GetLinearIP(vm); - - PrintTrace("Handling Input/Output Instruction Exit\n"); - - PrintTrace_VMX_Regs(regs); - - PrintTrace("Qualifications=0x%x\n", exitinfo->qualification); - PrintTrace("Reason=0x%x\n", exitinfo->reason); - PrintTrace("IO Port: 0x%x (%d)\n", qual->port, qual->port); - PrintTrace("Instruction Info=%x\n", exitinfo->instrInfo); - PrintTrace("%x : %s %s %s instruction of length %d for %d bytes from/to port 0x%x\n", - address, - qual->dir == 0 ? "output" : "input", - qual->string ==0 ? "nonstring" : "STRING", - qual->REP == 0 ? "with no rep" : "WITH REP", - exitinfo->instrLength, - qual->accessSize==0 ? 1 : qual->accessSize==1 ? 2 : 4, - qual->port); - - if ((qual->port == PIC_MASTER_CMD_ISR_PORT) || - (qual->port == PIC_MASTER_IMR_PORT) || - (qual->port == PIC_SLAVE_CMD_ISR_PORT) || - (qual->port == PIC_SLAVE_IMR_PORT)) { - PrintTrace( "PIC Access\n"); - } - - if ((qual->dir == 1) && (qual->REP == 0) && (qual->string == 0)) { - char byte = In_Byte(qual->port); + /* We enable the preemption timer by default to measure accurate guest time */ + if (avail_pin_ctrls.active_preempt_timer) { + V3_Print(core->vm_info, core, "VMX Preemption Timer is available\n"); + vmx_state->pin_ctrls.active_preempt_timer = 1; + vmx_state->exit_ctrls.save_preempt_timer = 1; + } - vm->vmcs.guestStateArea.rip += exitinfo->instrLength; - regs->eax = (regs->eax & 0xffffff00) | byte; - PrintTrace("Returning 0x%x in eax\n", (regs->eax)); - } + // we want it to use this when halting + vmx_state->pri_proc_ctrls.hlt_exit = 1; + + // cpuid tells it that it does not have these instructions + vmx_state->pri_proc_ctrls.monitor_exit = 1; + vmx_state->pri_proc_ctrls.mwait_exit = 1; + + // we don't need to handle a pause, although this is where + // we could pull out of a spin lock acquire or schedule to find its partner + vmx_state->pri_proc_ctrls.pause_exit = 0; + + vmx_state->pri_proc_ctrls.tsc_offset = 1; +#ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC + vmx_state->pri_proc_ctrls.rdtsc_exit = 1; +#endif + + /* Setup IO map */ + vmx_state->pri_proc_ctrls.use_io_bitmap = 1; + vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(core->vm_info->io_map.arch_data)); + vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR, + (addr_t)V3_PAddr(core->vm_info->io_map.arch_data) + PAGE_SIZE_4KB); + + + vmx_state->pri_proc_ctrls.use_msr_bitmap = 1; + vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data)); + + + +#ifdef __V3_64BIT__ + // Ensure host runs in 64-bit mode at each VM EXIT + vmx_state->exit_ctrls.host_64_on = 1; +#endif + + + + // Restore host's EFER register on each VM EXIT + vmx_state->exit_ctrls.ld_efer = 1; + + // Save/restore guest's EFER register to/from VMCS on VM EXIT/ENTRY + vmx_state->exit_ctrls.save_efer = 1; + vmx_state->entry_ctrls.ld_efer = 1; + + vmx_state->exit_ctrls.save_pat = 1; + vmx_state->exit_ctrls.ld_pat = 1; + vmx_state->entry_ctrls.ld_pat = 1; + + /* Temporary GPF trap */ + // vmx_state->excp_bmap.gp = 1; + + // Setup Guests initial PAT field + vmx_ret |= check_vmcs_write(VMCS_GUEST_PAT, 0x0007040600070406LL); + + // Capture CR8 mods so that we can keep the apic_tpr correct + vmx_state->pri_proc_ctrls.cr8_ld_exit = 1; + vmx_state->pri_proc_ctrls.cr8_str_exit = 1; + + + /* Setup paging */ + if (core->shdw_pg_mode == SHADOW_PAGING) { + PrintDebug(core->vm_info, core, "Creating initial shadow page table\n"); + + if (v3_init_passthrough_pts(core) == -1) { + PrintError(core->vm_info, core, "Could not initialize passthrough page tables\n"); + return -1; + } + +#define CR0_PE 0x00000001 +#define CR0_PG 0x80000000 +#define CR0_WP 0x00010000 // To ensure mem hooks work +#define CR0_NE 0x00000020 + vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE)); + + + // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written + vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE ); + + v3_activate_passthrough_pt(core); + + // vmx_state->pinbased_ctrls |= NMI_EXIT; + + /* Add CR exits */ + vmx_state->pri_proc_ctrls.cr3_ld_exit = 1; + vmx_state->pri_proc_ctrls.cr3_str_exit = 1; + + // Note that we intercept cr4.pae writes + // and we have cr4 read-shadowed to the shadow pager's cr4 + + vmx_state->pri_proc_ctrls.invlpg_exit = 1; + + /* Add page fault exits */ + vmx_state->excp_bmap.pf = 1; + + // Setup VMX Assist + v3_vmxassist_init(core, vmx_state); + + // Hook all accesses to EFER register + v3_hook_msr(core->vm_info, EFER_MSR, + &v3_handle_efer_read, + &v3_handle_efer_write, + core); + + } else if ((core->shdw_pg_mode == NESTED_PAGING) && + (v3_mach_type == V3_VMX_EPT_CPU)) { + +#define CR0_PE 0x00000001 +#define CR0_PG 0x80000000 +#define CR0_WP 0x00010000 // To ensure mem hooks work +#define CR0_NE 0x00000020 + vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE)); + + // vmx_state->pinbased_ctrls |= NMI_EXIT; + + // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written + vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE); + + /* Disable CR exits */ + vmx_state->pri_proc_ctrls.cr3_ld_exit = 0; + vmx_state->pri_proc_ctrls.cr3_str_exit = 0; + + vmx_state->pri_proc_ctrls.invlpg_exit = 0; + + /* Add page fault exits */ + // vmx_state->excp_bmap.pf = 1; // This should never happen..., enabled to catch bugs + + // Setup VMX Assist + v3_vmxassist_init(core, vmx_state); + + /* Enable EPT */ + vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls + vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging - if (qual->dir==0 && qual->REP==0 && qual->string==0) { - // See if we need to handle the outb as a signal or - // print from the VM - if (HandleVMPrintsAndPanics(vm,qual->port,regs->eax)) { + + + if (v3_init_nested_paging_core(core, &hw_info) == -1) { + PrintError(core->vm_info, core, "Error initializing EPT\n"); + return -1; + } + + // Hook all accesses to EFER register + v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL); + + } else if ((core->shdw_pg_mode == NESTED_PAGING) && + (v3_mach_type == V3_VMX_EPT_UG_CPU)) { + int i = 0; + // For now we will assume that unrestricted guest mode is assured w/ EPT + + + core->vm_regs.rsp = 0x00; + core->rip = 0xfff0; + core->vm_regs.rdx = 0x00000f00; + core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1 + core->ctrl_regs.cr0 = 0x60010030; + core->ctrl_regs.cr4 = 0x00002010; // Enable VMX and PSE flag + + + core->segments.cs.selector = 0xf000; + core->segments.cs.limit = 0xffff; + core->segments.cs.base = 0x0000000f0000LL; + + // (raw attributes = 0xf3) + core->segments.cs.type = 0xb; + core->segments.cs.system = 0x1; + core->segments.cs.dpl = 0x0; + core->segments.cs.present = 1; + + + + struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds), + &(core->segments.es), &(core->segments.fs), + &(core->segments.gs), NULL}; + + for ( i = 0; segregs[i] != NULL; i++) { + struct v3_segment * seg = segregs[i]; + + seg->selector = 0x0000; + // seg->base = seg->selector << 4; + seg->base = 0x00000000; + seg->limit = 0xffff; + + + seg->type = 0x3; + seg->system = 0x1; + seg->dpl = 0x0; + seg->present = 1; + // seg->granularity = 1; + + } + + + core->segments.gdtr.limit = 0x0000ffff; + core->segments.gdtr.base = 0x0000000000000000LL; + + core->segments.idtr.limit = 0x0000ffff; + core->segments.idtr.base = 0x0000000000000000LL; + + core->segments.ldtr.selector = 0x0000; + core->segments.ldtr.limit = 0x0000ffff; + core->segments.ldtr.base = 0x0000000000000000LL; + core->segments.ldtr.type = 0x2; + core->segments.ldtr.present = 1; + + core->segments.tr.selector = 0x0000; + core->segments.tr.limit = 0x0000ffff; + core->segments.tr.base = 0x0000000000000000LL; + core->segments.tr.type = 0xb; + core->segments.tr.present = 1; + + // core->dbg_regs.dr6 = 0x00000000ffff0ff0LL; + core->dbg_regs.dr7 = 0x0000000000000400LL; + + /* Enable EPT */ + vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls + vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging + vmx_state->sec_proc_ctrls.unrstrct_guest = 1; // enable unrestricted guest operation + + + /* Disable shadow paging stuff */ + vmx_state->pri_proc_ctrls.cr3_ld_exit = 0; + vmx_state->pri_proc_ctrls.cr3_str_exit = 0; + + vmx_state->pri_proc_ctrls.invlpg_exit = 0; + + + // Cause VM_EXIT whenever the CR4.VMXE bit is set + vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE); +#define CR0_NE 0x00000020 +#define CR0_CD 0x40000000 + vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, CR0_NE | CR0_CD); + ((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->ne = 1; + ((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->cd = 0; + + if (v3_init_nested_paging_core(core, &hw_info) == -1) { + PrintError(core->vm_info, core, "Error initializing EPT\n"); + return -1; + } + + // Hook all accesses to EFER register + // v3_hook_msr(core->vm_info, EFER_MSR, &debug_efer_read, &debug_efer_write, core); + v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL); } else { - // If not, just go ahead and do the outb - Out_Byte(qual->port,regs->eax); - PrintTrace("Wrote 0x%x to port\n",(regs->eax)); + PrintError(core->vm_info, core, "Invalid Virtual paging mode (pg_mode=%d) (mach_type=%d)\n", core->shdw_pg_mode, v3_mach_type); + return -1; } - vm->vmcs.guestStateArea.rip += exitinfo->instrLength; - } - return 0; -} + // hook vmx msrs -static int HandleExternalIRQExit(struct VM *vm) -{ - struct VMCSExitInfoFields * exitinfo = &(vm->vmcs.exitInfoFields); - struct VMExitIntInfo * intInfo = (struct VMExitIntInfo *)&(vm->vmcs.exitInfoFields.intInfo); + // Setup SYSCALL/SYSENTER MSRs in load/store area + + // save STAR, LSTAR, FMASK, KERNEL_GS_BASE MSRs in MSR load/store area + { - PrintTrace("External Interrupt captured\n"); - PrintTrace("IntInfo: %x\n", exitinfo->intInfo); + struct vmcs_msr_save_area * msr_entries = NULL; + int max_msrs = (hw_info.misc_info.max_msr_cache_size + 1) * 4; + int msr_ret = 0; + V3_Print(core->vm_info, core, "Setting up MSR load/store areas (max_msr_count=%d)\n", max_msrs); - if (!intInfo->valid) { - // interrupts are off, but this interrupt is not acknoledged (still pending) - // so we turn on interrupts to deliver appropriately in the - // host - PrintTrace("External Interrupt is invald. Turning Interrupts back on\n"); - asm("sti"); - return 0; - } - - // At this point, interrupts are off and the interrupt has been - // acknowledged. We will now handle the interrupt ourselves - // and turn interrupts back on in the host - - PrintTrace("type: %d\n", intInfo->type); - PrintTrace("number: %d\n", intInfo->nr); - - PrintTrace("Interrupt %d occuring now and handled by HandleExternalIRQExit\n",intInfo->nr); - - switch (intInfo->type) { - case 0: { // ext. IRQ - // In the following, we construct an "int x" instruction - // where x is the specific interrupt number that is raised - // then we execute that instruciton - // because we are in host context, that means it is delivered as normal - // through the host IDT - - ((char*)(&&ext_int_seq_start))[1] = intInfo->nr; - - PrintTrace("Interrupt instruction setup done %x\n", *((ushort_t *)(&&ext_int_seq_start))); - -ext_int_seq_start: - asm("int $0"); - } + if (max_msrs < 4) { + PrintError(core->vm_info, core, "Max MSR cache size is too small (%d)\n", max_msrs); + return -1; + } - break; - case 2: // NMI - PrintTrace("Type: NMI\n"); - break; - case 3: // hw exception - PrintTrace("Type: HW Exception\n"); - break; - case 4: // sw exception - PrintTrace("Type: SW Exception\n"); - break; - default: - PrintTrace("Invalid Interrupt Type\n"); - return -1; - } + vmx_state->msr_area_paddr = (addr_t)V3_AllocPages(1); // need not be shadow-safe, not exposed to guest + + if (vmx_state->msr_area_paddr == (addr_t)NULL) { + PrintError(core->vm_info, core, "could not allocate msr load/store area\n"); + return -1; + } + + msr_entries = (struct vmcs_msr_save_area *)V3_VAddr((void *)(vmx_state->msr_area_paddr)); + vmx_state->msr_area = msr_entries; // cache in vmx_info + + memset(msr_entries, 0, PAGE_SIZE); + + msr_entries->guest_star.index = IA32_STAR_MSR; + msr_entries->guest_lstar.index = IA32_LSTAR_MSR; + msr_entries->guest_fmask.index = IA32_FMASK_MSR; + msr_entries->guest_kern_gs.index = IA32_KERN_GS_BASE_MSR; + + msr_entries->host_star.index = IA32_STAR_MSR; + msr_entries->host_lstar.index = IA32_LSTAR_MSR; + msr_entries->host_fmask.index = IA32_FMASK_MSR; + msr_entries->host_kern_gs.index = IA32_KERN_GS_BASE_MSR; + + msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_CNT, 4); + msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_CNT, 4); + msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_CNT, 4); + + msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs)); + msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs)); + msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->host_msrs)); + + + msr_ret |= v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL); + + + // IMPORTANT: These MSRs appear to be cached by the hardware.... + msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL); + + msr_ret |= v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL); + + msr_ret |= v3_hook_msr(core->vm_info, IA32_PAT_MSR, NULL, NULL, NULL); + + // Not sure what to do about this... Does not appear to be an explicit hardware cache version... + msr_ret |= v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL); + + if (msr_ret != 0) { + PrintError(core->vm_info, core, "Error configuring MSR save/restore area\n"); + return -1; + } + + + } + + /* Sanity check ctrl/reg fields against hw_defaults */ + + + + + /*** Write all the info to the VMCS ***/ - if (intInfo->valid && intInfo->errorCode) { - PrintTrace("IntError: %x\n", exitinfo->intErrorCode); - } + /* + { + // IS THIS NECESSARY??? +#define DEBUGCTL_MSR 0x1d9 + struct v3_msr tmp_msr; + v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo)); + vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value); + core->dbg_regs.dr7 = 0x400; + } + */ +#ifdef __V3_64BIT__ + vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL); +#else + vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL); + vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL); +#endif - return 0; + + + + if (v3_update_vmcs_ctrl_fields(core)) { + PrintError(core->vm_info, core, "Could not write control fields!\n"); + return -1; + } + + /* + if (v3_update_vmcs_host_state(core)) { + PrintError(core->vm_info, core, "Could not write host state\n"); + return -1; + } + */ + + // reenable global interrupts for vm state initialization now + // that the vm state is initialized. If another VM kicks us off, + // it'll update our vmx state so that we know to reload ourself + v3_enable_ints(); + + return 0; } +static void __init_vmx_vmcs(void * arg) { + struct guest_info * core = arg; + struct vmx_data * vmx_state = NULL; + int vmx_ret = 0; + + vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data)); -void DecodeCurrentInstruction(struct VM *vm, struct Instruction *inst) -{ - // this is a gruesome hack - uint_t address = GetLinearIP(vm); - uint_t length = vm->vmcs.exitInfoFields.instrLength; - unsigned char *t = (unsigned char *) address; + if (!vmx_state) { + PrintError(core->vm_info, core, "Unable to allocate in initializing vmx vmcs\n"); + return; + } + memset(vmx_state, 0, sizeof(struct vmx_data)); - - PrintTrace("DecodeCurrentInstruction: instruction is\n"); - PrintTraceMemDump(t,length); - - if (length==3 && t[0]==0x0f && t[1]==0x22 && t[2]==0xc0) { - // mov from eax to cr0 - // usually used to signal - inst->type=VM_MOV_TO_CR0; - inst->address=address; - inst->size=length; - inst->input1=vm->registers.eax; - inst->input2=vm->vmcs.guestStateArea.cr0; - inst->output=vm->registers.eax; - PrintTrace("MOV FROM EAX TO CR0\n"); - } else { - inst->type=VM_UNKNOWN_INST; - } + PrintDebug(core->vm_info, core, "vmx_data pointer: %p\n", (void *)vmx_state); + + PrintDebug(core->vm_info, core, "Allocating VMCS\n"); + vmx_state->vmcs_ptr_phys = allocate_vmcs(); + + PrintDebug(core->vm_info, core, "VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys)); + + core->vmm_data = vmx_state; + vmx_state->state = VMX_UNLAUNCHED; + + PrintDebug(core->vm_info, core, "Initializing VMCS (addr=%p)\n", core->vmm_data); + + // TODO: Fix vmcs fields so they're 32-bit + + PrintDebug(core->vm_info, core, "Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys); + vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys); + + if (vmx_ret != VMX_SUCCESS) { + PrintError(core->vm_info, core, "VMCLEAR failed\n"); + return; + } + + if (core->vm_info->vm_class == V3_PC_VM) { + PrintDebug(core->vm_info, core, "Initializing VMCS\n"); + if (init_vmcs_bios(core, vmx_state) == -1) { + PrintError(core->vm_info, core, "Error initializing VMCS to BIOS state\n"); + return; + } + } else { + PrintError(core->vm_info, core, "Invalid VM Class\n"); + return; + } + + PrintDebug(core->vm_info, core, "Serializing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys); + vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys); + + core->core_run_state = CORE_STOPPED; + return; } -static void V8086ModeSegmentRegisterFixup(struct VM *vm) -{ - vm->vmcs.guestStateArea.cs.baseAddr=vm->vmcs.guestStateArea.cs.selector<<4; - vm->vmcs.guestStateArea.es.baseAddr=vm->vmcs.guestStateArea.es.selector<<4; - vm->vmcs.guestStateArea.ss.baseAddr=vm->vmcs.guestStateArea.ss.selector<<4; - vm->vmcs.guestStateArea.ds.baseAddr=vm->vmcs.guestStateArea.ds.selector<<4; - vm->vmcs.guestStateArea.fs.baseAddr=vm->vmcs.guestStateArea.fs.selector<<4; - vm->vmcs.guestStateArea.gs.baseAddr=vm->vmcs.guestStateArea.gs.selector<<4; + +int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) { + extern v3_cpu_arch_t v3_cpu_types[]; + + if (v3_cpu_types[V3_Get_CPU()] == V3_INVALID_CPU) { + int i = 0; + + for (i = 0; i < V3_CONFIG_MAX_CPUS; i++) { + if (v3_cpu_types[i] != V3_INVALID_CPU) { + break; + } + } + + if (i == V3_CONFIG_MAX_CPUS) { + PrintError(core->vm_info, core, "Could not find VALID CPU for VMX guest initialization\n"); + return -1; + } + + V3_Call_On_CPU(i, __init_vmx_vmcs, core); + + } else { + __init_vmx_vmcs(core); + } + + if (core->core_run_state != CORE_STOPPED) { + PrintError(core->vm_info, core, "Error initializing VMX Core\n"); + return -1; + } + + return 0; } -static void SetupV8086ModeForBoot(struct VM *vm) -{ - vm->state = VM_VMXASSIST_V8086_BIOS; - // Put guest into V8086 mode on return - vm->vmcs.guestStateArea.rflags |= EFLAGS_VM | EFLAGS_IOPL_HI | EFLAGS_IOPL_LO ; - - // We will start at f000:fff0 on return - // - // We want this to look as much as possible as a processor - // reset - vm->vmcs.guestStateArea.rip = 0xfff0; // note, 16 bit rip - vm->vmcs.guestStateArea.cs.selector = 0xf000; - vm->vmcs.guestStateArea.cs.limit=0xffff; - vm->vmcs.guestStateArea.cs.access.as_dword = 0xf3; - - vm->vmcs.guestStateArea.ss.selector = 0x0000; - vm->vmcs.guestStateArea.ss.limit=0xffff; - vm->vmcs.guestStateArea.ss.access.as_dword = 0xf3; - - vm->vmcs.guestStateArea.ds.selector = 0x0000; - vm->vmcs.guestStateArea.ds.limit=0xffff; - vm->vmcs.guestStateArea.ds.access.as_dword = 0xf3; - - vm->vmcs.guestStateArea.es.selector = 0x0000; - vm->vmcs.guestStateArea.es.limit=0xffff; - vm->vmcs.guestStateArea.es.access.as_dword = 0xf3; - - vm->vmcs.guestStateArea.fs.selector = 0x0000; - vm->vmcs.guestStateArea.fs.limit=0xffff; - vm->vmcs.guestStateArea.fs.access.as_dword = 0xf3; - - vm->vmcs.guestStateArea.gs.selector = 0x0000; - vm->vmcs.guestStateArea.gs.limit=0xffff; - vm->vmcs.guestStateArea.gs.access.as_dword = 0xf3; - - V8086ModeSegmentRegisterFixup(vm); +int v3_deinit_vmx_vmcs(struct guest_info * core) { + struct vmx_data * vmx_state = core->vmm_data; + + V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1); + V3_FreePages(V3_PAddr(vmx_state->msr_area), 1); - PrintTrace_VMCSData(&(vm->vmcs)); + V3_Free(vmx_state); + return 0; } - -static int HandleExceptionOrNMI(struct VM *vm) -{ - struct Instruction inst; - uint_t num; - uint_t type; - uint_t errorvalid; - uint_t error; - uint_t ext=0; - uint_t idt=0; - uint_t ti=0; - uint_t selectorindex=0; - PrintTrace("Exception or NMI occurred\n"); +#ifdef V3_CONFIG_CHECKPOINT +/* + * JRL: This is broken + */ +int v3_vmx_save_core(struct guest_info * core, void * ctx){ + struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data); - num=vm->vmcs.exitInfoFields.intInfo & 0xff; - type=(vm->vmcs.exitInfoFields.intInfo & 0x700)>>8; - errorvalid=(vm->vmcs.exitInfoFields.intInfo & 0x800)>>11; - if (errorvalid) { - error=vm->vmcs.exitInfoFields.intErrorCode; - ext=error&0x1; - idt=(error&0x2)>>1; - ti=(error&0x4)>>2; - selectorindex=(error>>3)&0xffff; + // note that the vmcs pointer is an HPA, but we need an HVA + if (v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE_4KB, + V3_VAddr((void*) (vmx_info->vmcs_ptr_phys)))) { + PrintError(core->vm_info, core, "Could not save vmcs data for VMX\n"); + return -1; } - PrintTrace("Exception %d now - handled by HandleExceptionOrNMI\n",num); + return 0; +} + +int v3_vmx_load_core(struct guest_info * core, void * ctx){ + struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data); + struct cr0_32 * shadow_cr0; + addr_t vmcs_page_paddr; //HPA + + vmcs_page_paddr = (addr_t) V3_AllocPages(1); // need not be shadow-safe, not exposed to guest + + if (!vmcs_page_paddr) { + PrintError(core->vm_info, core, "Could not allocate space for a vmcs in VMX\n"); + return -1; + } + + if (v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB, + V3_VAddr((void *)vmcs_page_paddr)) == -1) { + PrintError(core->vm_info, core, "Could not load vmcs data for VMX\n"); + V3_FreePages((void*)vmcs_page_paddr,1); + return -1; + } + + vmcs_clear(vmx_info->vmcs_ptr_phys); + + // Probably need to delete the old one... + V3_FreePages((void*)(vmx_info->vmcs_ptr_phys),1); + + vmcs_load(vmcs_page_paddr); + + v3_vmx_save_vmcs(core); + + shadow_cr0 = (struct cr0_32 *)&(core->ctrl_regs.cr0); + - PrintTrace("Exception Number %u : %s\n", num, exception_names[num]); - PrintTrace("Exception Type %u : %s\n", type, exception_type_names[type]); - if (errorvalid) { - if (ext) { - PrintTrace("External\n"); + /* Get the CPU mode to set the guest_ia32e entry ctrl */ + + if (core->shdw_pg_mode == SHADOW_PAGING) { + if (v3_get_vm_mem_mode(core) == VIRTUAL_MEM) { + if (v3_activate_shadow_pt(core) == -1) { + PrintError(core->vm_info, core, "Failed to activate shadow page tables\n"); + return -1; + } } else { - PrintTrace("%s - Selector Index is %u\n", idt ? "IDT" : ti ? "LDT" : "GDT", selectorindex); + if (v3_activate_passthrough_pt(core) == -1) { + PrintError(core->vm_info, core, "Failed to activate passthrough page tables\n"); + return -1; + } } } + + return 0; +} +#endif - DecodeCurrentInstruction(vm,&inst); - if (inst.type==VM_MOV_TO_CR0) { - PrintTrace("MOV TO CR0, oldvalue=0x%x, newvalue=0x%x\n",inst.input2, inst.input1); - if ((inst.input2 & CR0_PE) && !(inst.input1 & CR0_PE) && vm->state==VM_VMXASSIST_STARTUP) { - // This is VMXAssist signalling for us to turn on V8086 mode and - // jump into the bios - PrintTrace("VMXAssist is signaling us for switch to V8086 mode and jump to 0xf000:fff0\n"); - SetupV8086ModeForBoot(vm); - goto leave; - } else { - PrintTrace("Instruction is a write to CR0, but we don't understand it so we'll just exec it\n"); - } - } +void v3_flush_vmx_vm_core(struct guest_info * core) { + struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data); + vmcs_clear(vmx_info->vmcs_ptr_phys); + vmx_info->state = VMX_UNLAUNCHED; +} - PrintTrace("Trying to execute the faulting instruction in VMM context now\n"); - ExecFaultingInstructionInVMM(vm); - leave: - // - //PanicUnhandledVMExit(vmcs,regs); - //VMXPanic(); - return 0; -} +static int update_irq_exit_state(struct guest_info * info) { + struct vmx_exit_idt_vec_info idt_vec_info; + check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value)); -static struct VM *FindVM() -{ - return &theVM; + if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) { +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "Calling v3_injecting_intr\n"); +#endif + info->intr_core_state.irq_started = 0; + v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ); + } + + return 0; } +static int update_irq_entry_state(struct guest_info * info) { + struct vmx_exit_idt_vec_info idt_vec_info; + struct vmcs_interrupt_state intr_core_state; + struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data); + + check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value)); + check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state)); + + /* Check for pending exceptions to inject */ + if (v3_excp_pending(info)) { + struct vmx_entry_int_info int_info; + int_info.value = 0; + + // In VMX, almost every exception is hardware + // Software exceptions are pretty much only for breakpoint or overflow + int_info.type = 3; + int_info.vector = v3_get_excp_number(info); + + if (info->excp_state.excp_error_code_valid) { + check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code); + int_info.error_code = 1; + +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "Injecting exception %d with error code %x\n", + int_info.vector, info->excp_state.excp_error_code); +#endif + } + + int_info.valid = 1; +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip); +#endif + check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value); + + v3_injecting_excp(info, int_info.vector); + + } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) && + (intr_core_state.val == 0)) { + + if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) { + +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "IRQ pending from previous injection\n"); +#endif + + // Copy the IDT vectoring info over to reinject the old interrupt + if (idt_vec_info.error_code == 1) { + uint32_t err_code = 0; + + check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code); + check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code); + } + + idt_vec_info.undef = 0; + check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value); + + } else { + struct vmx_entry_int_info ent_int; + ent_int.value = 0; + + switch (v3_intr_pending(info)) { + case V3_EXTERNAL_IRQ: { + + int irq = v3_get_intr(info); + + if (irq<0) { + break; + } + + info->intr_core_state.irq_vector = irq; + ent_int.vector = info->intr_core_state.irq_vector; + ent_int.type = 0; + ent_int.error_code = 0; + ent_int.valid = 1; + +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "Injecting Interrupt %d at exit %u(EIP=%p)\n", + info->intr_core_state.irq_vector, + (uint32_t)info->num_exits, + (void *)(addr_t)info->rip); +#endif + + check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value); + info->intr_core_state.irq_started = 1; + + break; + } + case V3_NMI: + PrintDebug(info->vm_info, info, "Injecting NMI\n"); + + ent_int.type = 2; + ent_int.vector = 2; + ent_int.valid = 1; + check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value); + + break; + case V3_SOFTWARE_INTR: + PrintDebug(info->vm_info, info, "Injecting software interrupt\n"); + ent_int.type = 4; + + ent_int.valid = 1; + check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value); + + break; + case V3_VIRTUAL_IRQ: + // Not sure what to do here, Intel doesn't have virtual IRQs + // May be the same as external interrupts/IRQs + + break; + case V3_INVALID_INTR: + default: + break; + } + } + } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) { + // Enable INTR window exiting so we know when IF=1 + uint32_t instr_len; + + check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len); + +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "Enabling Interrupt-Window exiting: %d\n", instr_len); +#endif + + vmx_info->pri_proc_ctrls.int_wndw_exit = 1; + check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value); + } -int Do_VMM(struct VMXRegs regs) -{ - ullong_t vmcs_ptr = 0; - uint_t vmcs_ptr_low = 0; - int ret = 0; - uint_t vmx_abort = 0; + return 0; +} - - PrintTrace("Vm Exit\n"); - ret = VMCS_STORE(&vmcs_ptr); - vmcs_ptr &= 0xffffffff; - vmcs_ptr_low += vmcs_ptr; +static struct vmx_exit_info exit_log[10]; +static uint64_t rip_log[10]; - PrintTrace("ret=%d\n", ret); - PrintTrace("Revision: %x\n", *(uint_t *)(vmcs_ptr_low)); - vmx_abort = *(uint_t*)(((char *)vmcs_ptr_low)+4); +static void print_exit_log(struct guest_info * info) { + int cnt = info->num_exits % 10; + int i = 0; - struct VM *vm = FindVM(); - if (vmx_abort != 0) { - PrintTrace("VM ABORTED w/ code: %x\n", vmx_abort); - return -1; - } + V3_Print(info->vm_info, info, "\nExit Log (%d total exits):\n", (uint32_t)info->num_exits); - vm->registers = regs; + for (i = 0; i < 10; i++) { + struct vmx_exit_info * tmp = &exit_log[cnt]; - if (CopyOutVMCSData(&(vm->vmcs)) != 0) { - PrintTrace("Could not copy out VMCS\n"); - return -1; - } + V3_Print(info->vm_info, info, "%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason); + V3_Print(info->vm_info, info, "\texit_qual = %p\n", (void *)tmp->exit_qual); + V3_Print(info->vm_info, info, "\tint_info = %p\n", (void *)(addr_t)tmp->int_info); + V3_Print(info->vm_info, info, "\tint_err = %p\n", (void *)(addr_t)tmp->int_err); + V3_Print(info->vm_info, info, "\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info); + V3_Print(info->vm_info, info, "\tguest_linear_addr= %p\n", (void *)(addr_t)tmp->guest_linear_addr); + V3_Print(info->vm_info, info, "\tRIP = %p\n", (void *)rip_log[cnt]); - PrintTrace("Guest esp: 0x%x (%u)\n", vm->vmcs.guestStateArea.rsp, vm->vmcs.guestStateArea.rsp); + cnt--; - PrintTrace("VM Exit for reason: %d (%x)\n", - vm->vmcs.exitInfoFields.reason & 0x00000fff, - vm->vmcs.exitInfoFields.reason); + if (cnt == -1) { + cnt = 9; + } - if (vm->vmcs.exitInfoFields.reason & (0x1<<29) ) { - PrintTrace("VM Exit is from VMX root operation. Panicking\n"); - VMXPanic(); - } + } - if (vm->vmcs.exitInfoFields.reason & (0x1<<31) ) { - PrintTrace("VM Exit is due to a VM entry failure. Shouldn't happen here. Panicking\n"); - PrintTrace_VMCSData(&(vm->vmcs)); - VMXPanic(); - } +} - switch (vm->vmcs.exitInfoFields.reason) { - case VM_EXIT_REASON_INFO_EXCEPTION_OR_NMI: - ret = HandleExceptionOrNMI(vm); - break; - case VM_EXIT_REASON_EXTERNAL_INTR: - ret = HandleExternalIRQExit(vm); - break; - case VM_EXIT_REASON_TRIPLE_FAULT: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INIT_SIGNAL: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_STARTUP_IPI: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_IO_SMI: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_OTHER_SMI: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INTR_WINDOW: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_NMI_WINDOW: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_TASK_SWITCH: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_CPUID: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INVD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_INVLPG: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_RDPMC: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_RDTSC: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_RSM: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMCALL: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMCLEAR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMLAUNCH: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMPTRLD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMPTRST: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMREAD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMRESUME: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMWRITE: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMXOFF: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_VMXON: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_CR_REG_ACCESSES: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_MOV_DR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_IO_INSTR: - ret = HandleInOutExit(vm); - break; - case VM_EXIT_REASON_RDMSR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_WRMSR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_ENTRY_FAIL_INVALID_GUEST_STATE: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_ENTRY_FAIL_MSR_LOAD: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_MWAIT: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_MONITOR: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_PAUSE: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK: - ret = PanicUnhandledVMExit(vm); - break; - case VM_EXIT_REASON_TPR_BELOW_THRESHOLD: - ret = PanicUnhandledVMExit(vm); - break; - default: - ret = PanicUnhandledVMExit(vm); - break; - } - - - regs = vm->registers; - CopyInVMCSData(&(vm->vmcs)); +int +v3_vmx_config_tsc_virtualization(struct guest_info * info) { + struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data); + + if (info->time_state.flags & VM_TIME_TRAP_RDTSC) { + if (!vmx_info->pri_proc_ctrls.rdtsc_exit) { + vmx_info->pri_proc_ctrls.rdtsc_exit = 1; + check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value); + } + } else { + sint64_t tsc_offset; + uint32_t tsc_offset_low, tsc_offset_high; + + if (vmx_info->pri_proc_ctrls.rdtsc_exit) { + vmx_info->pri_proc_ctrls.rdtsc_exit = 0; + check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value); + } + + if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) { + tsc_offset = 0; + } else { + tsc_offset = v3_tsc_host_offset(&info->time_state); + } + tsc_offset_high = (uint32_t)(( tsc_offset >> 32) & 0xffffffff); + tsc_offset_low = (uint32_t)(tsc_offset & 0xffffffff); + + check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high); + check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low); + } + return 0; +} + +/* + * CAUTION and DANGER!!! + * + * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function + * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies + * on its contents will cause things to break. The contents at the time of the exit WILL + * change before the exit handler is executed. + */ +int v3_vmx_enter(struct guest_info * info) { + int ret = 0; + struct vmx_exit_info exit_info; + struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data); + uint64_t guest_cycles = 0; + + // Conditionally yield the CPU if the timeslice has expired + v3_schedule(info); + +#ifdef V3_CONFIG_MEM_TRACK + v3_mem_track_entry(info); +#endif + + // Update timer devices late after being in the VM so that as much + // of the time in the VM is accounted for as possible. Also do it before + // updating IRQ entry state so that any interrupts the timers raise get + // handled on the next VM entry. + v3_advance_time(info, NULL); + v3_update_timers(info); + + // disable global interrupts for vm state transition + v3_disable_ints(); + + if (vmcs_store() != vmx_info->vmcs_ptr_phys) { + vmcs_clear(vmx_info->vmcs_ptr_phys); + vmcs_load(vmx_info->vmcs_ptr_phys); + vmx_info->state = VMX_UNLAUNCHED; + } + + v3_vmx_restore_vmcs(info); + + +#ifdef V3_CONFIG_SYMCALL + if (info->sym_core_state.symcall_state.sym_call_active == 0) { + update_irq_entry_state(info); + } +#else + update_irq_entry_state(info); +#endif - /* { - VMCS_CLEAR(vmcs_ptr); + addr_t guest_cr3; + vmcs_read(VMCS_GUEST_CR3, &guest_cr3); + vmcs_write(VMCS_GUEST_CR3, guest_cr3); } - */ - PrintTrace("Returning from Do_VMM: %d\n", ret); - - return ret; -} + // Perform last-minute time setup prior to entering the VM + v3_vmx_config_tsc_virtualization(info); -static void ConfigureExits(struct VM *vm) -{ - CopyOutVMCSExecCtrlFields(&(vm->vmcs.execCtrlFields)); - - vm->vmcs.execCtrlFields.pinCtrls |= 0 - // EXTERNAL_INTERRUPT_EXITING - | NMI_EXITING; - vm->vmcs.execCtrlFields.procCtrls |= 0 - // INTERRUPT_WINDOWS_EXIT - | USE_TSC_OFFSETTING - | HLT_EXITING - |INVLPG_EXITING - |MWAIT_EXITING - |RDPMC_EXITING - |RDTSC_EXITING - |MOVDR_EXITING - |UNCONDITION_IO_EXITING - |MONITOR_EXITING - |PAUSE_EXITING ; - - CopyInVMCSExecCtrlFields(&(vm->vmcs.execCtrlFields)); - - CopyOutVMCSExitCtrlFields(&(vm->vmcs.exitCtrlFields)); + if (v3_update_vmcs_host_state(info)) { + v3_enable_ints(); + PrintError(info->vm_info, info, "Could not write host state\n"); + return -1; + } + + if (vmx_info->pin_ctrls.active_preempt_timer) { + /* Preemption timer is active */ + uint32_t preempt_window = 0xffffffff; + + if (info->timeouts.timeout_active) { + preempt_window = info->timeouts.next_timeout; + } + + check_vmcs_write(VMCS_PREEMPT_TIMER, preempt_window); + } - vm->vmcs.exitCtrlFields.exitCtrls |= ACK_IRQ_ON_EXIT; - - CopyInVMCSExitCtrlFields(&(vm->vmcs.exitCtrlFields)); + V3_FP_ENTRY_RESTORE(info); + { + uint64_t entry_tsc = 0; + uint64_t exit_tsc = 0; -/* VMCS_READ(VM_EXIT_CTRLS, &flags); */ -/* flags |= ACK_IRQ_ON_EXIT; */ -/* VMCS_WRITE(VM_EXIT_CTRLS, &flags); */ -} +#ifdef V3_CONFIG_PWRSTAT_TELEMETRY + v3_pwrstat_telemetry_enter(info); +#endif +#ifdef V3_CONFIG_PMU_TELEMETRY + v3_pmu_telemetry_enter(info); +#endif -extern int RunVMM(); -extern int SAFE_VM_LAUNCH(); + if (vmx_info->state == VMX_UNLAUNCHED) { + vmx_info->state = VMX_LAUNCHED; + rdtscll(entry_tsc); + ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs)); + rdtscll(exit_tsc); -int MyLaunch(struct VM *vm) -{ - ullong_t vmcs = (ullong_t)((uint_t) (vm->vmcsregion)); - uint_t entry_eip = vm->descriptor.entry_ip; - uint_t exit_eip = vm->descriptor.exit_eip; - uint_t guest_esp = vm->descriptor.guest_esp; - uint_t f = 0xffffffff; - uint_t tmpReg = 0; - int ret; - int vmm_ret = 0; + } else { + V3_ASSERT(info->vm_info, info,vmx_info->state != VMX_UNLAUNCHED); + rdtscll(entry_tsc); + ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs)); + rdtscll(exit_tsc); + } - PrintTrace("Guest ESP: 0x%x (%u)\n", guest_esp, guest_esp); + guest_cycles = exit_tsc - entry_tsc; - exit_eip=(uint_t)RunVMM; +#ifdef V3_CONFIG_PMU_TELEMETRY + v3_pmu_telemetry_exit(info); +#endif - PrintTrace("Clear\n"); - VMCS_CLEAR(vmcs); - PrintTrace("Load\n"); - VMCS_LOAD(vmcs); +#ifdef V3_CONFIG_PWRSTAT_TELEMETRY + v3_pwrstat_telemetry_exit(info); +#endif + } + // PrintDebug(info->vm_info, info, "VMX Exit: ret=%d\n", ret); - PrintTrace("VMCS_LINK_PTR\n"); - VMCS_WRITE(VMCS_LINK_PTR, &f); - PrintTrace("VMCS_LINK_PTR_HIGH\n"); - VMCS_WRITE(VMCS_LINK_PTR_HIGH, &f); + if (ret != VMX_SUCCESS) { + uint32_t error = 0; + vmcs_read(VMCS_INSTR_ERR, &error); - - SetCtrlBitsCorrectly(IA32_VMX_PINBASED_CTLS_MSR, PIN_VM_EXEC_CTRLS); - SetCtrlBitsCorrectly(IA32_VMX_PROCBASED_CTLS_MSR, PROC_VM_EXEC_CTRLS); - SetCtrlBitsCorrectly(IA32_VMX_EXIT_CTLS_MSR, VM_EXIT_CTRLS); - SetCtrlBitsCorrectly(IA32_VMX_ENTRY_CTLS_MSR, VM_ENTRY_CTRLS); - - // - // - //SetCtrlBitsCorrectly(IA32_something,GUEST_IA32_DEBUGCTL); - //SetCtrlBitsCorrectly(IA32_something,GUEST_IA32_DEBUGCTL_HIGH); - - - /* Host state */ - PrintTrace("Setting up host state\n"); - SetCRBitsCorrectly(IA32_VMX_CR0_FIXED0_MSR, IA32_VMX_CR0_FIXED1_MSR, HOST_CR0); - SetCRBitsCorrectly(IA32_VMX_CR4_FIXED0_MSR, IA32_VMX_CR4_FIXED1_MSR, HOST_CR4); - ret = Init_VMCS_HostState(); - - if (ret != VMX_SUCCESS) { - if (ret == VMX_FAIL_VALID) { - PrintTrace("Init Host state: VMCS FAILED WITH ERROR\n"); - } else { - PrintTrace("Init Host state: Invalid VMCS\n"); + v3_enable_ints(); + + PrintError(info->vm_info, info, "VMENTRY Error: %d (launch_ret = %d)\n", error, ret); + return -1; } - return ret; - } - // PrintTrace("HOST_RIP: %x (%u)\n", exit_eip, exit_eip); - VMCS_WRITE(HOST_RIP, &exit_eip); - /* Guest state */ - PrintTrace("Setting up guest state\n"); - PrintTrace("GUEST_RIP: %x (%u)\n", entry_eip, entry_eip); - VMCS_WRITE(GUEST_RIP,&entry_eip); + info->num_exits++; - SetCRBitsCorrectly(IA32_VMX_CR0_FIXED0_MSR, IA32_VMX_CR0_FIXED1_MSR, GUEST_CR0); - SetCRBitsCorrectly(IA32_VMX_CR4_FIXED0_MSR, IA32_VMX_CR4_FIXED1_MSR, GUEST_CR4); - ret = Init_VMCS_GuestState(); + V3_FP_EXIT_SAVE(info); - PrintTrace("InitGuestState returned\n"); - if (ret != VMX_SUCCESS) { - if (ret == VMX_FAIL_VALID) { - PrintTrace("Init Guest state: VMCS FAILED WITH ERROR\n"); - } else { - PrintTrace("Init Guest state: Invalid VMCS\n"); + /* If we have the preemption time, then use it to get more accurate guest time */ + if (vmx_info->pin_ctrls.active_preempt_timer) { + uint32_t cycles_left = 0; + check_vmcs_read(VMCS_PREEMPT_TIMER, &(cycles_left)); + + if (info->timeouts.timeout_active) { + guest_cycles = info->timeouts.next_timeout - cycles_left; + } else { + guest_cycles = 0xffffffff - cycles_left; + } } - return ret; - } - PrintTrace("GUEST_RSP: %x (%u)\n", guest_esp, (uint_t)guest_esp); - VMCS_WRITE(GUEST_RSP,&guest_esp); - // tmpReg = 0x4100; - tmpReg = 0xffffffff; - if (VMCS_WRITE(EXCEPTION_BITMAP,&tmpReg ) != VMX_SUCCESS) { - PrintInfo("Bitmap error\n"); - } + // Immediate exit from VM time bookkeeping + v3_advance_time(info, &guest_cycles); + + /* Update guest state */ + v3_vmx_save_vmcs(info); + + // info->cpl = info->segments.cs.selector & 0x3; + + info->mem_mode = v3_get_vm_mem_mode(info); + info->cpu_mode = v3_get_vm_cpu_mode(info); + + - ConfigureExits(vm); + check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len)); + check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info)); + check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason)); + check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual)); + check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info)); + check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err)); + check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr)); - PrintTrace("VMCS_LAUNCH\n"); + if (info->shdw_pg_mode == NESTED_PAGING) { + check_vmcs_read(VMCS_GUEST_PHYS_ADDR, &(exit_info.ept_fault_addr)); + } + + //PrintDebug(info->vm_info, info, "VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual); + + exit_log[info->num_exits % 10] = exit_info; + rip_log[info->num_exits % 10] = get_addr_linear(info, info->rip, &(info->segments.cs)); - vm->state=VM_VMXASSIST_STARTUP; +#ifdef V3_CONFIG_SYMCALL + if (info->sym_core_state.symcall_state.sym_call_active == 0) { + update_irq_exit_state(info); + } +#else + update_irq_exit_state(info); +#endif + + if (exit_info.exit_reason == VMX_EXIT_INTR_WINDOW) { + // This is a special case whose only job is to inject an interrupt + vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value)); + vmx_info->pri_proc_ctrls.int_wndw_exit = 0; + vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value); + +#ifdef V3_CONFIG_DEBUG_INTERRUPTS + V3_Print(info->vm_info, info, "Interrupts available again! (RIP=%llx)\n", info->rip); +#endif + } - vmm_ret = SAFE_VM_LAUNCH(); - PrintTrace("VMM error %d\n", vmm_ret); + // Lastly we check for an NMI exit, and reinject if so + { + struct vmx_basic_exit_info * basic_info = (struct vmx_basic_exit_info *)&(exit_info.exit_reason); - return vmm_ret; + if (basic_info->reason == VMX_EXIT_INFO_EXCEPTION_OR_NMI) { + if ((uint8_t)exit_info.int_info == 2) { + asm("int $2"); + } + } + } + + // reenable global interrupts after vm exit + v3_enable_ints(); + + // Conditionally yield the CPU if the timeslice has expired + v3_schedule(info); + v3_advance_time(info, NULL); + v3_update_timers(info); + + if (v3_handle_vmx_exit(info, &exit_info) == -1) { + PrintError(info->vm_info, info, "Error in VMX exit handler (Exit reason=%x)\n", exit_info.exit_reason); + return -1; + } + + if (info->timeouts.timeout_active) { + /* Check to see if any timeouts have expired */ + v3_handle_timeouts(info, guest_cycles); + } + +#ifdef V3_CONFIG_MEM_TRACK + v3_mem_track_exit(info); +#endif + + return 0; } +int v3_start_vmx_guest(struct guest_info * info) { - -int VMLaunch(struct VMDescriptor *vm) -{ - VMCS * vmcs = CreateVMCS(); - int rc; - - ullong_t vmcs_ptr = (ullong_t)((uint_t)vmcs); - uint_t top = (vmcs_ptr>>32)&0xffffffff; - uint_t bottom = (vmcs_ptr)&0xffffffff; - - theVM.vmcsregion = vmcs; - theVM.descriptor = *vm; - - PrintTrace("vmcs_ptr_top=%x vmcs_ptr_bottom=%x, eip=%x\n", top, bottom, vm->entry_ip); - rc=MyLaunch(&theVM); // vmcs_ptr, vm->entry_ip, vm->exit_eip, vm->guest_esp); - PrintTrace("Returned from MyLaunch();\n"); - return rc; + PrintDebug(info->vm_info, info, "Starting VMX core %u\n", info->vcpu_id); + +#if V3_CONFIG_HVM + if (v3_setup_hvm_vm_for_boot(vm)) { + PrintError(vm, VCORE_NONE, "HVM setup for boot failed\n"); + return -1; + } +#endif + + while (1) { + if (info->core_run_state == CORE_STOPPED) { + if (info->vcpu_id == 0) { + info->core_run_state = CORE_RUNNING; + } else { + + PrintDebug(info->vm_info, info, "VMX core %u: Waiting for core initialization\n", info->vcpu_id); + + V3_NO_WORK(info); + + while (info->core_run_state == CORE_STOPPED) { + + if (info->vm_info->run_state == VM_STOPPED) { + // The VM was stopped before this core was initialized. + return 0; + } + + V3_STILL_NO_WORK(info); + //PrintDebug(info->vm_info, info, "VMX core %u: still waiting for INIT\n",info->vcpu_id); + } + + V3_HAVE_WORK_AGAIN(info); + + PrintDebug(info->vm_info, info, "VMX core %u initialized\n", info->vcpu_id); + + // We'll be paranoid about race conditions here + v3_wait_at_barrier(info); + } + + + PrintDebug(info->vm_info, info, "VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n", + info->vcpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base), + info->segments.cs.limit, (void *)(info->rip)); + + + PrintDebug(info->vm_info, info, "VMX core %u: Launching VMX VM on logical core %u\n", info->vcpu_id, info->pcpu_id); + + v3_start_time(info); + + + if (info->vm_info->run_state == VM_STOPPED) { + info->core_run_state = CORE_STOPPED; + break; + } + } + + +#ifdef V3_CONFIG_PMU_TELEMETRY + v3_pmu_telemetry_start(info); +#endif + +#ifdef V3_CONFIG_PWRSTAT_TELEMETRY + v3_pwrstat_telemetry_start(info); +#endif + + + if (v3_vmx_enter(info) == -1) { + + addr_t host_addr; + addr_t linear_addr = 0; + + info->vm_info->run_state = VM_ERROR; + + V3_Print(info->vm_info, info, "VMX core %u: VMX ERROR!!\n", info->vcpu_id); + + v3_print_guest_state(info); + + V3_Print(info->vm_info, info, "VMX core %u\n", info->vcpu_id); + + linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs)); + + if (info->mem_mode == PHYSICAL_MEM) { + v3_gpa_to_hva(info, linear_addr, &host_addr); + } else if (info->mem_mode == VIRTUAL_MEM) { + v3_gva_to_hva(info, linear_addr, &host_addr); + } + + V3_Print(info->vm_info, info, "VMX core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr); + + V3_Print(info->vm_info, info, "VMX core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr); + v3_dump_mem((uint8_t *)host_addr, 15); + + v3_print_stack(info); + + + v3_print_vmcs(); + print_exit_log(info); + return -1; + } + + v3_wait_at_barrier(info); + + + if (info->vm_info->run_state == VM_STOPPED) { + info->core_run_state = CORE_STOPPED; + break; + } +/* + if ((info->num_exits % 5000) == 0) { + V3_Print(info->vm_info, info, "VMX Exit number %d\n", (uint32_t)info->num_exits); + } +*/ + + } + +#ifdef V3_CONFIG_PMU_TELEMETRY + v3_pmu_telemetry_end(info); +#endif + +#ifdef V3_CONFIG_PWRSTAT_TELEMETRY + v3_pwrstat_telemetry_end(info); +#endif + + return 0; +} + + + + +#define VMX_FEATURE_CONTROL_MSR 0x0000003a +#define CPUID_VMX_FEATURES 0x00000005 /* LOCK and VMXON */ +#define CPUID_1_ECX_VTXFLAG 0x00000020 + +int v3_is_vmx_capable() { + v3_msr_t feature_msr; + uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; + + v3_cpuid(0x1, &eax, &ebx, &ecx, &edx); + + PrintDebug(VM_NONE, VCORE_NONE, "ECX: 0x%x\n", ecx); + + if (ecx & CPUID_1_ECX_VTXFLAG) { + v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo)); + + PrintDebug(VM_NONE, VCORE_NONE, "MSRREGlow: 0x%.8x\n", feature_msr.lo); + + if ((feature_msr.lo & CPUID_VMX_FEATURES) != CPUID_VMX_FEATURES) { + PrintDebug(VM_NONE, VCORE_NONE, "VMX is locked -- enable in the BIOS\n"); + return 0; + } + + } else { + PrintDebug(VM_NONE, VCORE_NONE, "VMX not supported on this cpu\n"); + return 0; + } + + return 1; +} + + +int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) { + // init vmcs bios + + if ((core->shdw_pg_mode == NESTED_PAGING) && + (v3_mach_type == V3_VMX_EPT_UG_CPU)) { + // easy + core->rip = 0; + core->segments.cs.selector = rip << 8; + core->segments.cs.limit = 0xffff; + core->segments.cs.base = rip << 12; + } else { + core->vm_regs.rdx = core->vcpu_id; + core->vm_regs.rbx = rip; + } + + return 0; } -VmxOnRegion * CreateVmxOnRegion() { - union VMX_MSR basicMSR; - VmxOnRegion * region = (VmxOnRegion *)(os_hooks)->allocate_pages(1); - Get_MSR(IA32_VMX_BASIC_MSR, &basicMSR.regs.high, &basicMSR.regs.low); - // memcpy(region, &basicMSR.vmxBasic.revision, sizeof(uint_t)); +void v3_init_vmx_cpu(int cpu_id) { + addr_t vmx_on_region = 0; + extern v3_cpu_arch_t v3_mach_type; + extern v3_cpu_arch_t v3_cpu_types[]; + + if (v3_mach_type == V3_INVALID_CPU) { + if (v3_init_vmx_hw(&hw_info) == -1) { + PrintError(VM_NONE, VCORE_NONE, "Could not initialize VMX hardware features on cpu %d\n", cpu_id); + return; + } + } + + enable_vmx(); + - *(ulong_t*)region = basicMSR.vmxBasic.revision; + // Setup VMXON Region + vmx_on_region = allocate_vmcs(); - PrintInfo("VMX revision: 0x%lu\n", *(ulong_t *)region); - return region; + if (vmx_on(vmx_on_region) == VMX_SUCCESS) { + V3_Print(VM_NONE, VCORE_NONE, "VMX Enabled\n"); + host_vmcs_ptrs[cpu_id] = vmx_on_region; + } else { + V3_Print(VM_NONE, VCORE_NONE, "VMX already enabled\n"); + V3_FreePages((void *)vmx_on_region, 1); + } + + PrintDebug(VM_NONE, VCORE_NONE, "VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]); + + { + struct vmx_sec_proc_ctrls sec_proc_ctrls; + sec_proc_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.sec_proc_ctrls)); + + if (sec_proc_ctrls.enable_ept == 0) { + V3_Print(VM_NONE, VCORE_NONE, "VMX EPT (Nested) Paging not supported\n"); + v3_cpu_types[cpu_id] = V3_VMX_CPU; + } else if (sec_proc_ctrls.unrstrct_guest == 0) { + V3_Print(VM_NONE, VCORE_NONE, "VMX EPT (Nested) Paging supported\n"); + v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU; + } else { + V3_Print(VM_NONE, VCORE_NONE, "VMX EPT (Nested) Paging + Unrestricted guest supported\n"); + v3_cpu_types[cpu_id] = V3_VMX_EPT_UG_CPU; + } + } + } -VMCS * CreateVMCS() { - union VMX_MSR basicMSR; - VMCS * vmcs = (VMCS *)(os_hooks)->allocate_pages(1); - Get_MSR(IA32_VMX_BASIC_MSR, &basicMSR.regs.high, &basicMSR.regs.low); - *(ulong_t *)vmcs = basicMSR.vmxBasic.revision; - *(ulong_t *)((char*)vmcs + 4) = 0; +void v3_deinit_vmx_cpu(int cpu_id) { + extern v3_cpu_arch_t v3_cpu_types[]; + v3_cpu_types[cpu_id] = V3_INVALID_CPU; + + if (host_vmcs_ptrs[cpu_id] != 0) { + V3_Print(VM_NONE, VCORE_NONE, "Disabling VMX\n"); - PrintTrace("VMCS Region size: %u\n", basicMSR.vmxBasic.regionSize); - PrintTrace("VMCS Abort: %x\n",*(uint_t *)(((char*)vmcs)+4)); + if (vmx_off() != VMX_SUCCESS) { + PrintError(VM_NONE, VCORE_NONE, "Error executing VMXOFF\n"); + } - return vmcs; + V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1); + + host_vmcs_ptrs[cpu_id] = 0; + } }