X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fpalacios%2Fvmx.c;h=c341982e37cbf584e6212fcab4f3c0b453a41f91;hb=a7bd09077efcd826376f9c49ab97f9f9a1fbbefe;hp=d6dfafccfa94f359fe3993f747431913bd333971;hpb=65301e679dd7e1e8ab4ab4746e6b650c9e24d901;p=palacios.git diff --git a/palacios/src/palacios/vmx.c b/palacios/src/palacios/vmx.c index d6dfafc..c341982 100644 --- a/palacios/src/palacios/vmx.c +++ b/palacios/src/palacios/vmx.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #ifdef V3_CONFIG_CHECKPOINT #include @@ -51,7 +53,7 @@ /* These fields contain the hardware feature sets supported by the local CPU */ static struct vmx_hw_info hw_info; -extern v3_cpu_arch_t v3_cpu_types[]; +extern v3_cpu_arch_t v3_mach_type; static addr_t host_vmcs_ptrs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0}; @@ -68,6 +70,9 @@ static int inline check_vmcs_write(vmcs_field_t field, addr_t val) { return 1; } + + + return 0; } @@ -87,11 +92,17 @@ static int inline check_vmcs_read(vmcs_field_t field, void * val) { static addr_t allocate_vmcs() { + void *temp; struct vmcs_data * vmcs_page = NULL; PrintDebug("Allocating page\n"); - vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1)); + temp = V3_AllocPages(1); + if (!temp) { + PrintError("Cannot allocate VMCS\n"); + return -1; + } + vmcs_page = (struct vmcs_data *)V3_VAddr(temp); memset(vmcs_page, 0, 4096); vmcs_page->revision = hw_info.basic_info.revision; @@ -101,11 +112,42 @@ static addr_t allocate_vmcs() { } +#if 0 +static int debug_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * src, void * priv_data) { + struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer); + V3_Print("\n\nEFER READ (val = %p)\n", (void *)efer->value); + + v3_print_guest_state(core); + v3_print_vmcs(); + + + src->value = efer->value; + return 0; +} + +static int debug_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) { + struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer); + V3_Print("\n\nEFER WRITE (old_val = %p) (new_val = %p)\n", (void *)efer->value, (void *)src.value); + + v3_print_guest_state(core); + v3_print_vmcs(); + + efer->value = src.value; + + return 0; +} +#endif static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) { int vmx_ret = 0; + /* Get Available features */ + struct vmx_pin_ctrls avail_pin_ctrls; + avail_pin_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.pin_ctrls)); + /* ** */ + + // disable global interrupts for vm state initialization v3_disable_ints(); @@ -128,8 +170,8 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) vmx_state->sec_proc_ctrls.value = hw_info.sec_proc_ctrls.def_val; /* Print Control MSRs */ - PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)hw_info.cr0.value); - PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)hw_info.cr4.value); + V3_Print("CR0 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr0.req_val, (void *)(addr_t)hw_info.cr0.req_mask); + V3_Print("CR4 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr4.req_val, (void *)(addr_t)hw_info.cr4.req_mask); @@ -142,13 +184,29 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) /* Add external interrupts, NMI exiting, and virtual NMI */ vmx_state->pin_ctrls.nmi_exit = 1; + vmx_state->pin_ctrls.virt_nmi = 1; vmx_state->pin_ctrls.ext_int_exit = 1; + + /* We enable the preemption timer by default to measure accurate guest time */ + if (avail_pin_ctrls.active_preempt_timer) { + V3_Print("VMX Preemption Timer is available\n"); + vmx_state->pin_ctrls.active_preempt_timer = 1; + vmx_state->exit_ctrls.save_preempt_timer = 1; + } + + // we want it to use this when halting vmx_state->pri_proc_ctrls.hlt_exit = 1; + // cpuid tells it that it does not have these instructions + vmx_state->pri_proc_ctrls.monitor_exit = 1; + vmx_state->pri_proc_ctrls.mwait_exit = 1; + // we don't need to handle a pause, although this is where + // we could pull out of a spin lock acquire or schedule to find its partner vmx_state->pri_proc_ctrls.pause_exit = 0; + vmx_state->pri_proc_ctrls.tsc_offset = 1; #ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC vmx_state->pri_proc_ctrls.rdtsc_exit = 1; @@ -171,11 +229,7 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) vmx_state->exit_ctrls.host_64_on = 1; #endif - // Hook all accesses to EFER register - v3_hook_msr(core->vm_info, EFER_MSR, - &v3_handle_efer_read, - &v3_handle_efer_write, - core); + // Restore host's EFER register on each VM EXIT vmx_state->exit_ctrls.ld_efer = 1; @@ -184,13 +238,21 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) vmx_state->exit_ctrls.save_efer = 1; vmx_state->entry_ctrls.ld_efer = 1; - // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written - vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE); + vmx_state->exit_ctrls.save_pat = 1; + vmx_state->exit_ctrls.ld_pat = 1; + vmx_state->entry_ctrls.ld_pat = 1; + /* Temporary GPF trap */ + // vmx_state->excp_bmap.gp = 1; // Setup Guests initial PAT field vmx_ret |= check_vmcs_write(VMCS_GUEST_PAT, 0x0007040600070406LL); + // Capture CR8 mods so that we can keep the apic_tpr correct + vmx_state->pri_proc_ctrls.cr8_ld_exit = 1; + vmx_state->pri_proc_ctrls.cr8_str_exit = 1; + + /* Setup paging */ if (core->shdw_pg_mode == SHADOW_PAGING) { PrintDebug("Creating initial shadow page table\n"); @@ -203,7 +265,12 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) #define CR0_PE 0x00000001 #define CR0_PG 0x80000000 #define CR0_WP 0x00010000 // To ensure mem hooks work - vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP)); +#define CR0_NE 0x00000020 + vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE)); + + + // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written + vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE); core->ctrl_regs.cr3 = core->direct_map_pt; @@ -221,16 +288,26 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) // Setup VMX Assist v3_vmxassist_init(core, vmx_state); + // Hook all accesses to EFER register + v3_hook_msr(core->vm_info, EFER_MSR, + &v3_handle_efer_read, + &v3_handle_efer_write, + core); + } else if ((core->shdw_pg_mode == NESTED_PAGING) && - (v3_cpu_types[core->pcpu_id] == V3_VMX_EPT_CPU)) { + (v3_mach_type == V3_VMX_EPT_CPU)) { #define CR0_PE 0x00000001 #define CR0_PG 0x80000000 #define CR0_WP 0x00010000 // To ensure mem hooks work - vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP)); +#define CR0_NE 0x00000020 + vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE)); // vmx_state->pinbased_ctrls |= NMI_EXIT; + // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written + vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE); + /* Disable CR exits */ vmx_state->pri_proc_ctrls.cr3_ld_exit = 0; vmx_state->pri_proc_ctrls.cr3_str_exit = 0; @@ -254,8 +331,11 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) return -1; } + // Hook all accesses to EFER register + v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL); + } else if ((core->shdw_pg_mode == NESTED_PAGING) && - (v3_cpu_types[core->pcpu_id] == V3_VMX_EPT_UG_CPU)) { + (v3_mach_type == V3_VMX_EPT_UG_CPU)) { int i = 0; // For now we will assume that unrestricted guest mode is assured w/ EPT @@ -264,7 +344,7 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) core->rip = 0xfff0; core->vm_regs.rdx = 0x00000f00; core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1 - core->ctrl_regs.cr0 = 0x00000030; + core->ctrl_regs.cr0 = 0x60010030; core->ctrl_regs.cr4 = 0x00002010; // Enable VMX and PSE flag @@ -336,13 +416,22 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) vmx_state->pri_proc_ctrls.invlpg_exit = 0; + // Cause VM_EXIT whenever the CR4.VMXE bit is set + vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE); +#define CR0_NE 0x00000020 + vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, CR0_NE); + ((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->ne = 1; + if (v3_init_ept(core, &hw_info) == -1) { PrintError("Error initializing EPT\n"); return -1; } + // Hook all accesses to EFER register + // v3_hook_msr(core->vm_info, EFER_MSR, &debug_efer_read, &debug_efer_write, core); + v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL); } else { - PrintError("Invalid Virtual paging mode\n"); + PrintError("Invalid Virtual paging mode (pg_mode=%d) (mach_type=%d)\n", core->shdw_pg_mode, v3_mach_type); return -1; } @@ -410,6 +499,7 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) msr_ret |= v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL); msr_ret |= v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL); + msr_ret |= v3_hook_msr(core->vm_info, IA32_PAT_MSR, NULL, NULL, NULL); // Not sure what to do about this... Does not appear to be an explicit hardware cache version... msr_ret |= v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL); @@ -448,6 +538,7 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) #endif + if (v3_update_vmcs_ctrl_fields(core)) { @@ -470,11 +561,19 @@ static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) return 0; } -int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) { + +static void __init_vmx_vmcs(void * arg) { + struct guest_info * core = arg; struct vmx_data * vmx_state = NULL; int vmx_ret = 0; vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data)); + + if (!vmx_state) { + PrintError("Unable to allocate in initializing vmx vmcs\n"); + return; + } + memset(vmx_state, 0, sizeof(struct vmx_data)); PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state); @@ -496,23 +595,57 @@ int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) { if (vmx_ret != VMX_SUCCESS) { PrintError("VMCLEAR failed\n"); - return -1; + return; } - if (vm_class == V3_PC_VM) { + if (core->vm_info->vm_class == V3_PC_VM) { PrintDebug("Initializing VMCS\n"); if (init_vmcs_bios(core, vmx_state) == -1) { PrintError("Error initializing VMCS to BIOS state\n"); - return -1; + return; } } else { PrintError("Invalid VM Class\n"); - return -1; + return; } PrintDebug("Serializing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys); vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys); + core->core_run_state = CORE_STOPPED; + return; +} + + + +int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) { + extern v3_cpu_arch_t v3_cpu_types[]; + + if (v3_cpu_types[V3_Get_CPU()] == V3_INVALID_CPU) { + int i = 0; + + for (i = 0; i < V3_CONFIG_MAX_CPUS; i++) { + if (v3_cpu_types[i] != V3_INVALID_CPU) { + break; + } + } + + if (i == V3_CONFIG_MAX_CPUS) { + PrintError("Could not find VALID CPU for VMX guest initialization\n"); + return -1; + } + + V3_Call_On_CPU(i, __init_vmx_vmcs, core); + + } else { + __init_vmx_vmcs(core); + } + + if (core->core_run_state != CORE_STOPPED) { + PrintError("Error initializing VMX Core\n"); + return -1; + } + return 0; } @@ -535,9 +668,14 @@ int v3_deinit_vmx_vmcs(struct guest_info * core) { * JRL: This is broken */ int v3_vmx_save_core(struct guest_info * core, void * ctx){ - uint64_t vmcs_ptr = vmcs_store(); + struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data); - v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE, (void *)vmcs_ptr); + // note that the vmcs pointer is an HPA, but we need an HVA + if (v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE_4KB, + V3_VAddr((void*) (vmx_info->vmcs_ptr_phys))) ==-1) { + PrintError("Could not save vmcs data for VMX\n"); + return -1; + } return 0; } @@ -545,12 +683,27 @@ int v3_vmx_save_core(struct guest_info * core, void * ctx){ int v3_vmx_load_core(struct guest_info * core, void * ctx){ struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data); struct cr0_32 * shadow_cr0; - char vmcs[PAGE_SIZE_4KB]; + addr_t vmcs_page_paddr; //HPA + + vmcs_page_paddr = (addr_t) V3_AllocPages(1); + + if (!vmcs_page_paddr) { + PrintError("Could not allocate space for a vmcs in VMX\n"); + return -1; + } - v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB, vmcs); + if (v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB, + V3_VAddr((void *)vmcs_page_paddr)) == -1) { + PrintError("Could not load vmcs data for VMX\n"); + return -1; + } vmcs_clear(vmx_info->vmcs_ptr_phys); - vmcs_load((addr_t)vmcs); + + // Probably need to delete the old one... + V3_FreePages((void*)(vmx_info->vmcs_ptr_phys),1); + + vmcs_load(vmcs_page_paddr); v3_vmx_save_vmcs(core); @@ -763,41 +916,35 @@ static void print_exit_log(struct guest_info * info) { } -int -v3_vmx_schedule_timeout(struct guest_info * info) -{ - struct vmx_data * vmx_state = (struct vmx_data *)(info->vmm_data); - sint64_t cycles; - uint32_t timeout; - - /* Check if the hardware supports an active timeout */ -#define VMX_ACTIVE_PREEMPT_TIMER_PIN 0x40 - if (hw_info.pin_ctrls.req_mask & VMX_ACTIVE_PREEMPT_TIMER_PIN) { - /* The hardware doesn't support us modifying this pin control */ - return 0; - } +int +v3_vmx_config_tsc_virtualization(struct guest_info * info) { + struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data); - /* Check if we have one to schedule and schedule it if we do */ - cycles = (sint64_t)info->time_state.next_timeout - (sint64_t)v3_get_guest_time(&info->time_state); - if (info->time_state.next_timeout == (ullong_t) -1) { - timeout = 0; - vmx_state->pin_ctrls.active_preempt_timer = 0; - } else if (cycles < 0) { - /* set the timeout to 0 to force an immediate re-exit since it expired between - * when we checked a timeout and now. IF SOMEONE CONTINAULLY SETS A SHORT TIMEOUT, - * THIS CAN LOCK US OUT OF THE GUEST! */ - timeout = 0; - vmx_state->pin_ctrls.active_preempt_timer = 1; + if (info->time_state.flags & VM_TIME_TRAP_RDTSC) { + if (!vmx_info->pri_proc_ctrls.rdtsc_exit) { + vmx_info->pri_proc_ctrls.rdtsc_exit = 1; + check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value); + } } else { - /* The hardware supports scheduling a timeout, and we have one to - * schedule */ - timeout = (uint32_t)cycles >> hw_info.misc_info.tsc_multiple; - vmx_state->pin_ctrls.active_preempt_timer = 1; - } + sint64_t tsc_offset; + uint32_t tsc_offset_low, tsc_offset_high; - /* Actually program the timer based on the settings above. */ - check_vmcs_write(VMCS_PREEMPT_TIMER, timeout); - check_vmcs_write(VMCS_PIN_CTRLS, vmx_state->pin_ctrls.value); + if (vmx_info->pri_proc_ctrls.rdtsc_exit) { + vmx_info->pri_proc_ctrls.rdtsc_exit = 0; + check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value); + } + + if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) { + tsc_offset = 0; + } else { + tsc_offset = v3_tsc_host_offset(&info->time_state); + } + tsc_offset_high = (uint32_t)(( tsc_offset >> 32) & 0xffffffff); + tsc_offset_low = (uint32_t)(tsc_offset & 0xffffffff); + + check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high); + check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low); + } return 0; } @@ -811,30 +958,23 @@ v3_vmx_schedule_timeout(struct guest_info * info) */ int v3_vmx_enter(struct guest_info * info) { int ret = 0; - uint32_t tsc_offset_low, tsc_offset_high; struct vmx_exit_info exit_info; struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data); + uint64_t guest_cycles = 0; // Conditionally yield the CPU if the timeslice has expired - v3_yield_cond(info); - - // Perform any additional yielding needed for time adjustment - v3_adjust_time(info); - - // Check for timeout - since this calls generic hooks in devices - // that may do things like pause the VM, it cannot be with interrupts - // disabled. - v3_check_timeout(info); - - // disable global interrupts for vm state transition - v3_disable_ints(); + v3_yield_cond(info,-1); // Update timer devices late after being in the VM so that as much // of the time in the VM is accounted for as possible. Also do it before // updating IRQ entry state so that any interrupts the timers raise get - // handled on the next VM entry. Must be done with interrupts disabled. + // handled on the next VM entry. + v3_advance_time(info, NULL); v3_update_timers(info); + // disable global interrupts for vm state transition + v3_disable_ints(); + if (vmcs_store() != vmx_info->vmcs_ptr_phys) { vmcs_clear(vmx_info->vmcs_ptr_phys); vmcs_load(vmx_info->vmcs_ptr_phys); @@ -858,34 +998,47 @@ int v3_vmx_enter(struct guest_info * info) { vmcs_write(VMCS_GUEST_CR3, guest_cr3); } - // Update vmx active preemption timer to exit at the next timeout if - // the hardware supports it. - v3_vmx_schedule_timeout(info); - - // Perform last-minute time bookkeeping prior to entering the VM - v3_time_enter_vm(info); - tsc_offset_high = (uint32_t)((v3_tsc_host_offset(&info->time_state) >> 32) & 0xffffffff); - tsc_offset_low = (uint32_t)(v3_tsc_host_offset(&info->time_state) & 0xffffffff); - check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high); - check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low); + // Perform last-minute time setup prior to entering the VM + v3_vmx_config_tsc_virtualization(info); if (v3_update_vmcs_host_state(info)) { v3_enable_ints(); PrintError("Could not write host state\n"); return -1; } + + if (vmx_info->pin_ctrls.active_preempt_timer) { + /* Preemption timer is active */ + uint32_t preempt_window = 0xffffffff; - - if (vmx_info->state == VMX_UNLAUNCHED) { - vmx_info->state = VMX_LAUNCHED; - ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs)); - } else { - V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED); - ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs)); + if (info->timeouts.timeout_active) { + preempt_window = info->timeouts.next_timeout; + } + + check_vmcs_write(VMCS_PREEMPT_TIMER, preempt_window); } - + + + { + uint64_t entry_tsc = 0; + uint64_t exit_tsc = 0; + + if (vmx_info->state == VMX_UNLAUNCHED) { + vmx_info->state = VMX_LAUNCHED; + rdtscll(entry_tsc); + ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs)); + rdtscll(exit_tsc); + + } else { + V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED); + rdtscll(entry_tsc); + ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs)); + rdtscll(exit_tsc); + } + guest_cycles = exit_tsc - entry_tsc; + } // PrintDebug("VMX Exit: ret=%d\n", ret); @@ -900,11 +1053,22 @@ int v3_vmx_enter(struct guest_info * info) { } + info->num_exits++; - // Immediate exit from VM time bookkeeping - v3_time_exit_vm(info); + /* If we have the preemption time, then use it to get more accurate guest time */ + if (vmx_info->pin_ctrls.active_preempt_timer) { + uint32_t cycles_left = 0; + check_vmcs_read(VMCS_PREEMPT_TIMER, &(cycles_left)); - info->num_exits++; + if (info->timeouts.timeout_active) { + guest_cycles = info->timeouts.next_timeout - cycles_left; + } else { + guest_cycles = 0xffffffff - cycles_left; + } + } + + // Immediate exit from VM time bookkeeping + v3_advance_time(info, &guest_cycles); /* Update guest state */ v3_vmx_save_vmcs(info); @@ -915,6 +1079,7 @@ int v3_vmx_enter(struct guest_info * info) { info->cpu_mode = v3_get_vm_cpu_mode(info); + check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len)); check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info)); check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason)); @@ -940,7 +1105,7 @@ int v3_vmx_enter(struct guest_info * info) { update_irq_exit_state(info); #endif - if (exit_info.exit_reason == VMEXIT_INTR_WINDOW) { + if (exit_info.exit_reason == VMX_EXIT_INTR_WINDOW) { // This is a special case whose only job is to inject an interrupt vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value)); vmx_info->pri_proc_ctrls.int_wndw_exit = 0; @@ -951,17 +1116,36 @@ int v3_vmx_enter(struct guest_info * info) { #endif } + + // Lastly we check for an NMI exit, and reinject if so + { + struct vmx_basic_exit_info * basic_info = (struct vmx_basic_exit_info *)&(exit_info.exit_reason); + + if (basic_info->reason == VMX_EXIT_INFO_EXCEPTION_OR_NMI) { + if ((uint8_t)exit_info.int_info == 2) { + asm("int $2"); + } + } + } + // reenable global interrupts after vm exit v3_enable_ints(); // Conditionally yield the CPU if the timeslice has expired - v3_yield_cond(info); + v3_yield_cond(info,-1); + v3_advance_time(info, NULL); + v3_update_timers(info); if (v3_handle_vmx_exit(info, &exit_info) == -1) { PrintError("Error in VMX exit handler (Exit reason=%x)\n", exit_info.exit_reason); return -1; } + if (info->timeouts.timeout_active) { + /* Check to see if any timeouts have expired */ + v3_handle_timeouts(info, guest_cycles); + } + return 0; } @@ -983,7 +1167,7 @@ int v3_start_vmx_guest(struct guest_info * info) { return 0; } - v3_yield(info); + v3_yield(info,-1); //PrintDebug("VMX core %u: still waiting for INIT\n",info->vcpu_id); } @@ -1100,7 +1284,7 @@ int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) { // init vmcs bios if ((core->shdw_pg_mode == NESTED_PAGING) && - (v3_cpu_types[core->pcpu_id] == V3_VMX_EPT_UG_CPU)) { + (v3_mach_type == V3_VMX_EPT_UG_CPU)) { // easy core->rip = 0; core->segments.cs.selector = rip << 8; @@ -1119,6 +1303,7 @@ int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) { void v3_init_vmx_cpu(int cpu_id) { addr_t vmx_on_region = 0; extern v3_cpu_arch_t v3_mach_type; + extern v3_cpu_arch_t v3_cpu_types[]; if (v3_mach_type == V3_INVALID_CPU) { if (v3_init_vmx_hw(&hw_info) == -1) {