X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fpalacios%2Fvmm_hvm.c;h=24ae9fdca54347f5d32f465628501d50b35d892c;hb=aeb2b4bea5822761eebe0c9f4d2bef40324354c7;hp=b1f7013d8cbeeca843f97724ac18a54250978c30;hpb=60ad6a41c6d0ee08ed689e8505eb0c3df0c2a289;p=palacios.git diff --git a/palacios/src/palacios/vmm_hvm.c b/palacios/src/palacios/vmm_hvm.c index b1f7013..24ae9fd 100644 --- a/palacios/src/palacios/vmm_hvm.c +++ b/palacios/src/palacios/vmm_hvm.c @@ -28,8 +28,8 @@ #include -#include -#include +#include + /* @@ -68,6 +68,13 @@ #define PrintDebug(fmt, args...) #endif + +// if set, we will map the first 1 GB of memory using a 3 level +// hierarchy, for compatibility with Nautilus out of the box. +// Otherwise we will map the first 512 GB using a 2 level +// hieratchy +#define HVM_MAP_1G_2M 1 + int v3_init_hvm() { PrintDebug(VM_NONE,VCORE_NONE, "hvm: init\n"); @@ -83,8 +90,16 @@ int v3_deinit_hvm() static int hvm_hcall_handler(struct guest_info * core , hcall_id_t hcall_id, void * priv_data) { - V3_Print(core->vm_info,core, "hvm: received hypercall %x rax=%llx rbx=%llx rcx=%llx\n", - hcall_id, core->vm_regs.rax, core->vm_regs.rbx, core->vm_regs.rcx); + uint64_t c; + + rdtscll(c); + + + V3_Print(core->vm_info,core, "hvm: received hypercall %x rax=%llx rbx=%llx rcx=%llx at cycle count %llu (%llu cycles since last boot start) num_exits=%llu since initial boot\n", + hcall_id, core->vm_regs.rax, core->vm_regs.rbx, core->vm_regs.rcx, c, c-core->hvm_state.last_boot_start, core->num_exits); + //v3_print_core_telemetry(core); + // v3_print_guest_state(core); + return 0; } @@ -98,7 +113,7 @@ int v3_init_hvm_vm(struct v3_vm_info *vm, struct v3_xml *config) char *enable; char *ros_cores; char *ros_mem; - char *hrt_file_id; + char *hrt_file_id=0; PrintDebug(vm, VCORE_NONE, "hvm: vm init\n"); @@ -223,11 +238,7 @@ uint64_t v3_get_hvm_ros_memsize(struct v3_vm_info *vm) } uint64_t v3_get_hvm_hrt_memsize(struct v3_vm_info *vm) { - if (vm->hvm_state.is_hvm) { - return vm->mem_size - vm->hvm_state.first_hrt_gpa; - } else { - return 0; - } + return vm->mem_size; } uint32_t v3_get_hvm_ros_cores(struct v3_vm_info *vm) @@ -317,10 +328,18 @@ void v3_hvm_find_apics_seen_by_core(struct guest_info *core, struct v3_vm_in } } +#define MAX(x,y) ((x)>(y)?(x):(y)) +#define MIN(x,y) ((x)<(y)?(x):(y)) + +#ifdef HVM_MAP_1G_2M +#define BOOT_STATE_END_ADDR (MIN(vm->mem_size,0x40000000ULL)) +#else +#define BOOT_STATE_END_ADDR (MIN(vm->mem_size,0x800000000ULL)) +#endif static void get_null_int_handler_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) { - *base = (void*) PAGE_ADDR(vm->mem_size - PAGE_SIZE); + *base = (void*) PAGE_ADDR(BOOT_STATE_END_ADDR - PAGE_SIZE); *limit = PAGE_SIZE; } @@ -372,7 +391,7 @@ static void write_null_int_handler(struct v3_vm_info *vm) static void get_idt_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) { - *base = (void*) PAGE_ADDR(vm->mem_size - 2 * PAGE_SIZE); + *base = (void*) PAGE_ADDR(BOOT_STATE_END_ADDR - 2 * PAGE_SIZE); *limit = 16*256; } @@ -450,7 +469,7 @@ static void write_idt(struct v3_vm_info *vm) static void get_gdt_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) { - *base = (void*)PAGE_ADDR(vm->mem_size - 3 * PAGE_SIZE); + *base = (void*)PAGE_ADDR(BOOT_STATE_END_ADDR - 3 * PAGE_SIZE); *limit = 8*3; } @@ -475,22 +494,18 @@ static void write_gdt(struct v3_vm_info *vm) static void get_tss_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) { - *base = (void*)PAGE_ADDR(vm->mem_size - 4 * PAGE_SIZE); + *base = (void*)PAGE_ADDR(BOOT_STATE_END_ADDR - 4 * PAGE_SIZE); *limit = PAGE_SIZE; } -static uint64_t tss_data=0x0; - static void write_tss(struct v3_vm_info *vm) { void *base; uint64_t limit; - int i; get_tss_loc(vm,&base,&limit); - for (i=0;icores[0],(addr_t)(base+8*i),8,(uint8_t*) &tss_data); - } + + v3_set_gpa_memory(&vm->cores[0],(addr_t)base,limit,0); PrintDebug(vm,VCORE_NONE,"hvm: wrote TSS at %p\n",base); } @@ -501,15 +516,31 @@ static void write_tss(struct v3_vm_info *vm) 512 entries 1 top level 1 entries + +OR + + PTS MAP FIRST 1 GB identity mapped: + 1 third level + 512 entries + 1 second level + 1 entries + 1 top level + 1 entries */ static void get_pt_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) { - *base = (void*)PAGE_ADDR(vm->mem_size-(5+1)*PAGE_SIZE); +#ifdef HVM_MAP_1G_2M + *base = (void*)PAGE_ADDR(BOOT_STATE_END_ADDR-(5+2)*PAGE_SIZE); + *limit = 3*PAGE_SIZE; +#else + *base = (void*)PAGE_ADDR(BOOT_STATE_END_ADDR-(5+1)*PAGE_SIZE); *limit = 2*PAGE_SIZE; +#endif } -static void write_pt(struct v3_vm_info *vm) +#ifndef HVM_MAP_1G_2M +static void write_pt_2level_512GB(struct v3_vm_info *vm) { void *base; uint64_t size; @@ -522,6 +553,10 @@ static void write_pt(struct v3_vm_info *vm) PrintError(vm,VCORE_NONE,"Cannot support pt request, defaulting\n"); } + if (vm->mem_size > 0x800000000ULL) { + PrintError(vm,VCORE_NONE, "VM has more than 512 GB\n"); + } + memset(&pdpe,0,sizeof(pdpe)); pdpe.present=1; pdpe.writable=1; @@ -544,71 +579,294 @@ static void write_pt(struct v3_vm_info *vm) v3_write_gpa_memory(&vm->cores[0],(addr_t)(base+i*sizeof(pml4e)),sizeof(pml4e),(uint8_t*)&pml4e); } - PrintDebug(vm,VCORE_NONE,"hvm: Wrote page tables (1 PML4, 1 PDPE) at %p\n",base); + PrintDebug(vm,VCORE_NONE,"hvm: Wrote page tables (1 PML4, 1 PDPE) at %p (512 GB mapped)\n",base); } -static void get_bp_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) -{ - *base = (void*) PAGE_ADDR(vm->mem_size-(6+1)*PAGE_SIZE); - *limit = PAGE_SIZE; -} +#else -static void write_bp(struct v3_vm_info *vm) +static void write_pt_3level_1GB(struct v3_vm_info *vm) { void *base; - uint64_t limit; - uint64_t data=-1; - int i; + uint64_t size; + struct pml4e64 pml4e; + struct pdpe64 pdpe; + struct pde64 pde; + + uint64_t i; + + get_pt_loc(vm,&base, &size); + if (size!=3*PAGE_SIZE) { + PrintError(vm,VCORE_NONE,"Cannot support pt request, defaulting\n"); + } + + if (vm->mem_size > 0x40000000ULL) { + PrintError(vm,VCORE_NONE, "VM has more than 1 GB\n"); + } - get_bp_loc(vm,&base,&limit); + memset(&pde,0,sizeof(pde)); + pde.present=1; + pde.writable=1; + pde.large_page=1; - for (i=0;icores[0],(addr_t)(base+i*8),8,(uint8_t*)&data); + for (i=0;i<512;i++) { + pde.pt_base_addr = i*0x200; // 0x200 = 512 pages = 2 MB + v3_write_gpa_memory(&vm->cores[0], + (addr_t)(base+2*PAGE_SIZE+i*sizeof(pde)), + sizeof(pde),(uint8_t*)&pde); } - PrintDebug(vm,VCORE_NONE,"hvm: wrote boundary page at %p\n", base); + memset(&pdpe,0,sizeof(pdpe)); + pdpe.present=1; + pdpe.writable=1; + pdpe.large_page=0; + + pdpe.pd_base_addr = PAGE_BASE_ADDR((addr_t)(base+2*PAGE_SIZE)); + + v3_write_gpa_memory(&vm->cores[0],(addr_t)base+PAGE_SIZE,sizeof(pdpe),(uint8_t*)&pdpe); + for (i=1;i<512;i++) { + pdpe.present = 0; + v3_write_gpa_memory(&vm->cores[0],(addr_t)(base+PAGE_SIZE+i*sizeof(pdpe)),sizeof(pdpe),(uint8_t*)&pdpe); + } + + memset(&pml4e,0,sizeof(pml4e)); + pml4e.present=1; + pml4e.writable=1; + pml4e.pdp_base_addr = PAGE_BASE_ADDR((addr_t)(base+PAGE_SIZE)); + + v3_write_gpa_memory(&vm->cores[0],(addr_t)base,sizeof(pml4e),(uint8_t*)&pml4e); + + for (i=1;i<512;i++) { + pml4e.present=0; + v3_write_gpa_memory(&vm->cores[0],(addr_t)(base+i*sizeof(pml4e)),sizeof(pml4e),(uint8_t*)&pml4e); + } + + PrintDebug(vm,VCORE_NONE,"hvm: Wrote page tables (1 PML4, 1 PDPE, 1 PDP) at %p (1 GB mapped)\n",base); +} + +#endif + +static void write_pt(struct v3_vm_info *vm) +{ +#ifdef HVM_MAP_1G_2M + write_pt_3level_1GB(vm); +#else + write_pt_2level_512GB(vm); +#endif +} + +static void get_mb_info_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) +{ +#ifdef HVM_MAP_1G_2M + *base = (void*) PAGE_ADDR(BOOT_STATE_END_ADDR-(6+2)*PAGE_SIZE); +#else + *base = (void*) PAGE_ADDR(BOOT_STATE_END_ADDR-(6+1)*PAGE_SIZE); +#endif + *limit = PAGE_SIZE; +} + +static void write_mb_info(struct v3_vm_info *vm) +{ + if (vm->hvm_state.hrt_type!=HRT_MBOOT64) { + PrintError(vm, VCORE_NONE,"hvm: Cannot handle this HRT type\n"); + return; + } else { + uint8_t buf[256]; + uint64_t size; + void *base; + uint64_t limit; + + get_mb_info_loc(vm,&base,&limit); + + if ((size=v3_build_multiboot_table(&vm->cores[vm->hvm_state.first_hrt_core],buf,256))==-1) { + PrintError(vm,VCORE_NONE,"hvm: Failed to build MB info\n"); + return; + } + + if (size>limit) { + PrintError(vm,VCORE_NONE,"hvm: MB info is too large\n"); + return; + } + + v3_write_gpa_memory(&vm->cores[vm->hvm_state.first_hrt_core], + (addr_t)base, + size, + buf); + + PrintDebug(vm,VCORE_NONE, "hvm: wrote MB info at %p\n", base); + } } -#define MIN_STACK (4096*4) +#define SCRATCH_STACK_SIZE 4096 static void get_hrt_loc(struct v3_vm_info *vm, void **base, uint64_t *limit) { - void *bp_base; - uint64_t bp_limit; + void *mb_base; + uint64_t mb_limit; - get_bp_loc(vm,&bp_base,&bp_limit); + get_mb_info_loc(vm,&mb_base,&mb_limit); - // assume at least a minimal stack - - bp_base-=MIN_STACK; + mb_base-=SCRATCH_STACK_SIZE*v3_get_hvm_hrt_cores(vm); *base = (void*)PAGE_ADDR(vm->hvm_state.first_hrt_gpa); - if (bp_base < *base+PAGE_SIZE) { + if (mb_base < *base+PAGE_SIZE) { PrintError(vm,VCORE_NONE,"hvm: HRT stack colides with HRT\n"); } - *limit = bp_base - *base; + *limit = mb_base - *base; +} + + +#define ERROR(fmt, args...) PrintError(VM_NONE,VCORE_NONE,"hvm: " fmt,##args) +#define INFO(fmt, args...) PrintDebug(VM_NONE,VCORE_NONE,"hvm: " fmt,##args) + +#define ELF_MAGIC 0x464c457f +#define MB2_MAGIC 0xe85250d6 + +#define MB2_INFO_MAGIC 0x36d76289 + +static int is_elf(uint8_t *data, uint64_t size) +{ + if (*((uint32_t*)data)==ELF_MAGIC) { + return 1; + } else { + return 0; + } +} + +static mb_header_t *find_mb_header(uint8_t *data, uint64_t size) +{ + uint64_t limit = size > 32768 ? 32768 : size; + uint64_t i; + + // Scan for the .boot magic cookie + // must be in first 32K, assume 4 byte aligned + for (i=0;icores[0],(addr_t)base,vm->hvm_state.hrt_file->size,vm->hvm_state.hrt_file->data); + + vm->hvm_state.hrt_entry_addr = (uint64_t) (base+0x40); + + PrintDebug(vm,VCORE_NONE,"hvm: wrote HRT ELF %s at %p\n", vm->hvm_state.hrt_file->tag,base); + PrintDebug(vm,VCORE_NONE,"hvm: set ELF entry to %p and hoping for the best...\n", (void*) vm->hvm_state.hrt_entry_addr); + + vm->hvm_state.hrt_type = HRT_ELF64; + + return 0; + } -static void write_hrt(struct v3_vm_info *vm) +static int setup_mb_kernel(struct v3_vm_info *vm, void *base, uint64_t limit) +{ + mb_data_t mb; + + if (v3_parse_multiboot_header(vm->hvm_state.hrt_file,&mb)) { + PrintError(vm,VCORE_NONE, "hvm: failed to parse multiboot kernel header\n"); + return -1; + } + + + if (v3_write_multiboot_kernel(vm,&mb,vm->hvm_state.hrt_file,base,limit)) { + PrintError(vm,VCORE_NONE, "hvm: failed to write multiboot kernel into memory\n"); + return -1; + } + + /* + if (!mb.addr || !mb.entry) { + PrintError(vm,VCORE_NONE, "hvm: kernel is missing address or entry point\n"); + return -1; + } + + if (((void*)(uint64_t)(mb.addr->header_addr) < base ) || + ((void*)(uint64_t)(mb.addr->load_end_addr) > base+limit) || + ((void*)(uint64_t)(mb.addr->bss_end_addr) > base+limit)) { + PrintError(vm,VCORE_NONE, "hvm: kernel is not within the allowed portion of HVM\n"); + return -1; + } + + offset = mb.addr->load_addr - mb.addr->header_addr; + + // Skip the ELF header - assume 1 page... weird.... + // FIX ME TO CONFORM TO MULTIBOOT.C + v3_write_gpa_memory(&vm->cores[0], + (addr_t)(mb.addr->load_addr), + vm->hvm_state.hrt_file->size-PAGE_SIZE-offset, + vm->hvm_state.hrt_file->data+PAGE_SIZE+offset); + + + // vm->hvm_state.hrt_entry_addr = (uint64_t) mb.entry->entry_addr + PAGE_SIZE; //HACK PAD + + + PrintDebug(vm,VCORE_NONE, + "hvm: wrote 0x%llx bytes starting at offset 0x%llx to %p; set entry to %p\n", + (uint64_t) vm->hvm_state.hrt_file->size-PAGE_SIZE-offset, + (uint64_t) PAGE_SIZE+offset, + (void*)(addr_t)(mb.addr->load_addr), + (void*) vm->hvm_state.hrt_entry_addr); + + + */ + + vm->hvm_state.hrt_entry_addr = (uint64_t) mb.entry->entry_addr; + + vm->hvm_state.hrt_type = HRT_MBOOT64; + + return 0; + +} + + +static int setup_hrt(struct v3_vm_info *vm) { void *base; uint64_t limit; get_hrt_loc(vm,&base,&limit); - + if (vm->hvm_state.hrt_file->size > limit) { PrintError(vm,VCORE_NONE,"hvm: Cannot map HRT because it is too big (%llu bytes, but only have %llu space\n", vm->hvm_state.hrt_file->size, (uint64_t)limit); - return; + return -1; } - v3_write_gpa_memory(&vm->cores[0],(addr_t)base,vm->hvm_state.hrt_file->size,vm->hvm_state.hrt_file->data); + if (!is_elf(vm->hvm_state.hrt_file->data,vm->hvm_state.hrt_file->size)) { + PrintError(vm,VCORE_NONE,"hvm: supplied HRT is not an ELF but we are going to act like it is!\n"); + if (setup_elf(vm,base,limit)) { + PrintError(vm,VCORE_NONE,"hvm: Fake ELF setup failed\n"); + return -1; + } + vm->hvm_state.hrt_type=HRT_BLOB; + } else { + if (find_mb_header(vm->hvm_state.hrt_file->data,vm->hvm_state.hrt_file->size)) { + PrintDebug(vm,VCORE_NONE,"hvm: appears to be a multiboot kernel\n"); + if (setup_mb_kernel(vm,base,limit)) { + PrintError(vm,VCORE_NONE,"hvm: multiboot kernel setup failed\n"); + return -1; + } + } else { + PrintDebug(vm,VCORE_NONE,"hvm: supplied HRT is an ELF\n"); + if (setup_elf(vm,base,limit)) { + PrintError(vm,VCORE_NONE,"hvm: Fake ELF setup failed\n"); + return -1; + } + } + } - PrintDebug(vm,VCORE_NONE,"hvm: wrote HRT %s at %p\n", vm->hvm_state.hrt_file->tag,base); - + return 0; } @@ -631,8 +889,11 @@ static void write_hrt(struct v3_vm_info *vm) PAGETABLES (identy map of first N GB) ROOT PT first, followed by 2nd level, etc. Currently PML4 followed by 1 PDPE for 512 GB of mapping - BOUNDARY PAGE (all 0xff - avoid smashing page tables in case we keep going...) - (stack - we will push machine description) + MBINFO_PAGE + SCRATCH_STACK_HRT_CORE0 + SCRATCH_STACK_HRT_CORE1 + .. + SCRATCH_STACK_HRT_COREN ... HRT (as many pages as needed, page-aligned, starting at first HRT address) --- @@ -657,10 +918,14 @@ int v3_setup_hvm_vm_for_boot(struct v3_vm_info *vm) write_pt(vm); - write_bp(vm); - write_hrt(vm); + if (setup_hrt(vm)) { + PrintError(vm,VCORE_NONE,"hvm: failed to setup HRT\n"); + return -1; + } + // need to parse HRT first + write_mb_info(vm); PrintDebug(vm,VCORE_NONE,"hvm: setup of HVM memory done\n"); @@ -668,7 +933,7 @@ int v3_setup_hvm_vm_for_boot(struct v3_vm_info *vm) } /* - On entry: + On entry for every core: IDTR points to stub IDT GDTR points to stub GDT @@ -676,12 +941,12 @@ int v3_setup_hvm_vm_for_boot(struct v3_vm_info *vm) CR3 points to root page table CR0 has PE and PG EFER has LME AND LMA - RSP is TOS (looks like a call) - INFO <= RDI - 0 (fake return address) <= RSP - - RIP is entry point to HRT - RDI points to machine info on stack + RSP is TOS of core's scratch stack (looks like a call) + + RAX = MB magic cookie + RBX = address of multiboot info table + RCX = this core id / apic id (0..N-1) + RDX = this core id - first HRT core ID (==0 for the first HRT core) Other regs are zeroed @@ -693,6 +958,8 @@ int v3_setup_hvm_hrt_core_for_boot(struct guest_info *core) void *base; uint64_t limit; + rdtscll(core->hvm_state.last_boot_start); + if (!core->hvm_state.is_hrt) { PrintDebug(core->vm_info,core,"hvm: skipping HRT setup for core %u as it is not an HRT core\n", core->vcpu_id); return 0; @@ -701,6 +968,8 @@ int v3_setup_hvm_hrt_core_for_boot(struct guest_info *core) PrintDebug(core->vm_info, core, "hvm: setting up HRT core (%u) for boot\n", core->vcpu_id); + + memset(&core->vm_regs,0,sizeof(core->vm_regs)); memset(&core->ctrl_regs,0,sizeof(core->ctrl_regs)); memset(&core->dbg_regs,0,sizeof(core->dbg_regs)); @@ -715,31 +984,69 @@ int v3_setup_hvm_hrt_core_for_boot(struct guest_info *core) core->mem_mode = VIRTUAL_MEM; core->core_run_state = CORE_RUNNING ; - // We are going to enter right into the HRT - // HRT stack and argument passing - get_bp_loc(core->vm_info, &base,&limit); - // TODO: push description here - core->vm_regs.rsp = (v3_reg_t) base; // so if we ret, we will blow up - core->vm_regs.rbp = (v3_reg_t) base; - // TODO: RDI should really get pointer to description - core->vm_regs.rdi = (v3_reg_t) base; + + // magic + core->vm_regs.rax = MB2_INFO_MAGIC; + + // multiboot info pointer + get_mb_info_loc(core->vm_info, &base,&limit); + core->vm_regs.rbx = (uint64_t) base; + + // core number + core->vm_regs.rcx = core->vcpu_id; + + // HRT core number + core->vm_regs.rdx = core->vcpu_id - core->vm_info->hvm_state.first_hrt_core; + + // Now point to scratch stack for this core + // it begins at an ofset relative to the MB info page + get_mb_info_loc(core->vm_info, &base,&limit); + base -= core->vm_regs.rdx * SCRATCH_STACK_SIZE; + core->vm_regs.rsp = (v3_reg_t) base; + core->vm_regs.rbp = (v3_reg_t) base-8; + + // push onto the stack a bad rbp and bad return address + core->vm_regs.rsp-=16; + v3_set_gpa_memory(core, + core->vm_regs.rsp, + 16, + 0xff); + + // HRT entry point get_hrt_loc(core->vm_info, &base,&limit); - core->rip = (uint64_t) base + 0x40; // hack for test.o + core->rip = (uint64_t) core->vm_info->hvm_state.hrt_entry_addr ; + + + PrintDebug(core->vm_info,core,"hvm: hrt core %u has rip=%p, rsp=%p, rbp=%p, rax=%p, rbx=%p, rcx=%p, rdx=%p\n", + (core->vcpu_id - core->vm_info->hvm_state.first_hrt_core), + (void*)(core->rip), + (void*)(core->vm_regs.rsp), + (void*)(core->vm_regs.rbp), + (void*)(core->vm_regs.rax), + (void*)(core->vm_regs.rbx), + (void*)(core->vm_regs.rcx), + (void*)(core->vm_regs.rdx)); // Setup CRs for long mode and our stub page table // CR0: PG, PE core->ctrl_regs.cr0 = 0x80000001; + core->shdw_pg_state.guest_cr0 = core->ctrl_regs.cr0; + // CR2: don't care (output from #PF) // CE3: set to our PML4E, without setting PCD or PWT get_pt_loc(core->vm_info, &base,&limit); core->ctrl_regs.cr3 = PAGE_ADDR((addr_t)base); + core->shdw_pg_state.guest_cr3 = core->ctrl_regs.cr3; + // CR4: PGE, PAE, PSE (last byte: 1 0 1 1 0 0 0 0) core->ctrl_regs.cr4 = 0xb0; + core->shdw_pg_state.guest_cr4 = core->ctrl_regs.cr4; // CR8 as usual // RFLAGS zeroed is fine: come in with interrupts off - // EFER needs SVME LMA LME (last 16 bites: 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 + // EFER needs SVME LMA LME (last 16 bits: 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 core->ctrl_regs.efer = 0x1500; + core->shdw_pg_state.guest_efer.value = core->ctrl_regs.efer; /* @@ -817,12 +1124,70 @@ int v3_setup_hvm_hrt_core_for_boot(struct guest_info *core) memcpy(&core->segments.fs,&core->segments.ds,sizeof(core->segments.ds)); memcpy(&core->segments.gs,&core->segments.ds,sizeof(core->segments.ds)); + // reset paging here for shadow... if (core->shdw_pg_mode != NESTED_PAGING) { PrintError(core->vm_info, core, "hvm: shadow paging guest... this will end badly\n"); + return -1; } return 0; } + +int v3_handle_hvm_reset(struct guest_info *core) +{ + + if (core->core_run_state != CORE_RESETTING) { + return 0; + } + + if (!core->vm_info->hvm_state.is_hvm) { + return 0; + } + + if (v3_is_hvm_hrt_core(core)) { + // this is an HRT reset + int rc=0; + + // wait for all the HRT cores + v3_counting_barrier(&core->vm_info->reset_barrier); + + if (core->vcpu_id==core->vm_info->hvm_state.first_hrt_core) { + // I am leader + core->vm_info->run_state = VM_RESETTING; + } + + core->core_run_state = CORE_RESETTING; + + if (core->vcpu_id==core->vm_info->hvm_state.first_hrt_core) { + // we really only need to clear the bss + // and recopy the .data, but for now we'll just + // do everything + rc |= v3_setup_hvm_vm_for_boot(core->vm_info); + } + + // now everyone is ready to reset + rc |= v3_setup_hvm_hrt_core_for_boot(core); + + core->core_run_state = CORE_RUNNING; + + if (core->vcpu_id==core->vm_info->hvm_state.first_hrt_core) { + // leader + core->vm_info->run_state = VM_RUNNING; + } + + v3_counting_barrier(&core->vm_info->reset_barrier); + + if (rc<0) { + return rc; + } else { + return 1; + } + + } else { + // ROS core will be handled by normal reset functionality + return 0; + } +}