X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fpalacios%2Fvmm_ctrl_regs.c;h=c80f60594eee113b04ee46dd6baec8021e725107;hb=a5264d4dcf50d633e01e92dba62a5cf00c3bae2a;hp=afecc746db78616a069449e005afb6ea04af73a7;hpb=5aac3f94fc38bfef003c41496089eb3793778342;p=palacios.git

diff --git a/palacios/src/palacios/vmm_ctrl_regs.c b/palacios/src/palacios/vmm_ctrl_regs.c
index afecc74..c80f605 100644
--- a/palacios/src/palacios/vmm_ctrl_regs.c
+++ b/palacios/src/palacios/vmm_ctrl_regs.c
@@ -26,7 +26,7 @@
 #include <palacios/vmm_direct_paging.h>
 #include <palacios/svm.h>
 
-#ifndef CONFIG_DEBUG_CTRL_REGS
+#ifndef V3_CONFIG_DEBUG_CTRL_REGS
 #undef PrintDebug
 #define PrintDebug(fmt, args...)
 #endif
@@ -108,13 +108,18 @@ static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_in
     *guest_cr0 = *new_cr0;
     
     // This value must always be set to 1 
-    guest_cr0->et = 1;    
+    guest_cr0->et = 1;
     
     // Set the shadow register to catch non-virtualized flags
     *shadow_cr0 = *guest_cr0;
     
     // Paging is always enabled
-    shadow_cr0->pg = 1;  
+    shadow_cr0->pg = 1;
+
+    if (guest_cr0->pg == 0) {
+	// If paging is not enabled by the guest, then we always enable write-protect to catch memory hooks
+	shadow_cr0->wp = 1;
+    }
     
     // Was there a paging transition
     // Meaning we need to change the page tables
@@ -425,7 +430,7 @@ int v3_handle_cr3_read(struct guest_info * info) {
 
 // We don't need to virtualize CR4, all we need is to detect the activation of PAE
 int v3_handle_cr4_read(struct guest_info * info) {
-    //  PrintError("CR4 Read not handled\n");
+    PrintError("CR4 Read not handled\n");
     // Do nothing...
     return 0;
 }
@@ -455,6 +460,7 @@ int v3_handle_cr4_write(struct guest_info * info) {
     
     // Check to see if we need to flush the tlb
     
+
     if (v3_get_vm_mem_mode(info) == VIRTUAL_MEM) { 
 	struct cr4_32 * new_cr4 = (struct cr4_32 *)(dec_instr.src_operand.operand);
 	struct cr4_32 * cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4);
@@ -528,16 +534,16 @@ int v3_handle_cr4_write(struct guest_info * info) {
 	return -1;
     }
     
-    
-    if (flush_tlb) {
-	PrintDebug("Handling PSE/PGE/PAE -> TLBFlush (doing flush now!)\n");
-	if (v3_activate_shadow_pt(info) == -1) {
-	    PrintError("Failed to activate shadow page tables when emulating TLB flush in handling cr4 write\n");
-	    return -1;
+    if (info->shdw_pg_mode == SHADOW_PAGING) {
+	if (flush_tlb) {
+	    PrintDebug("Handling PSE/PGE/PAE -> TLBFlush (doing flush now!)\n");
+	    if (v3_activate_shadow_pt(info) == -1) {
+		PrintError("Failed to activate shadow page tables when emulating TLB flush in handling cr4 write\n");
+		return -1;
+	    }
 	}
     }
     
-    
     info->rip += dec_instr.instr_length;
     return 0;
 }
@@ -552,24 +558,48 @@ int v3_handle_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * ds
 }
 
 
-
-// TODO: this is a disaster we need to clean this up...
 int v3_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
-    //struct efer_64 * new_efer = (struct efer_64 *)&(src.value);
-    struct efer_64 * shadow_efer = (struct efer_64 *)&(core->ctrl_regs.efer);
-    struct v3_msr * guest_efer = &(core->shdw_pg_state.guest_efer);
-    
-    PrintDebug("EFER Write\n");
-    PrintDebug("EFER Write Values: HI=%x LO=%x\n", src.hi, src.lo);
-    //PrintDebug("Old EFER=%p\n", (void *)*(addr_t*)(shadow_efer));
-    
-    // We virtualize the guests efer to hide the SVME and LMA bits
-    guest_efer->value = src.value;
-    
-    
-    // Enable/Disable Syscall
-    shadow_efer->sce = src.value & 0x1;
-    
+    struct v3_msr *  vm_efer     = &(core->shdw_pg_state.guest_efer);
+    struct efer_64 * hw_efer     = (struct efer_64 *)&(core->ctrl_regs.efer);
+    struct efer_64   old_hw_efer = *((struct efer_64 *)&core->ctrl_regs.efer);
+    
+    PrintDebug("EFER Write HI=%x LO=%x\n", src.hi, src.lo);
+
+    // Set EFER value seen by guest if it reads EFER
+    vm_efer->value = src.value;
+
+    // Set EFER value seen by hardware while the guest is running
+    *(uint64_t *)hw_efer = src.value;
+
+    // We have gotten here either because we are using
+    // shadow paging, or we are using nested paging on SVM
+    // In the latter case, we don't need to do anything
+    // like the following
+    if (core->shdw_pg_mode == SHADOW_PAGING) { 
+      // Catch unsupported features
+      if ((old_hw_efer.lme == 1) && (hw_efer->lme == 0)) {
+	PrintError("Disabling long mode once it has been enabled is not supported\n");
+	return -1;
+      }
+      
+      // Set LME and LMA bits seen by hardware
+      if (old_hw_efer.lme == 0) {
+	// Long mode was not previously enabled, so the lme bit cannot
+	// be set yet. It will be set later when the guest sets CR0.PG
+	// to enable paging.
+    	hw_efer->lme = 0;
+      } else {
+	// Long mode was previously enabled. Ensure LMA bit is set.
+	// VMX does not automatically set LMA, and this should not affect SVM.
+	hw_efer->lma = 1;
+      }
+    }
+      
+      
+    PrintDebug("RIP=%p\n", (void *)core->rip);
+    PrintDebug("New EFER value HW(hi=%p), VM(hi=%p)\n", (void *)*(uint64_t *)hw_efer, (void *)vm_efer->value); 
+
+
     return 0;
 }