X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fpalacios%2Fvmm_ctrl_regs.c;h=add91ff5ea4842adb3a3ad538877aa00ad32d5a0;hb=c0ecfba627c1d6c3f46d59bd4e5e6f883a494dc4;hp=bbeaf4ceb54650315d27194748721c89bd8ca51b;hpb=be31ae90ff05da4b33a8389b6814f094a7385cd9;p=palacios.git diff --git a/palacios/src/palacios/vmm_ctrl_regs.c b/palacios/src/palacios/vmm_ctrl_regs.c index bbeaf4c..add91ff 100644 --- a/palacios/src/palacios/vmm_ctrl_regs.c +++ b/palacios/src/palacios/vmm_ctrl_regs.c @@ -24,8 +24,9 @@ #include #include #include +#include -#ifndef CONFIG_DEBUG_CTRL_REGS +#ifndef V3_CONFIG_DEBUG_CTRL_REGS #undef PrintDebug #define PrintDebug(fmt, args...) #endif @@ -44,13 +45,18 @@ int v3_handle_cr0_write(struct guest_info * info) { struct x86_instr dec_instr; if (info->mem_mode == PHYSICAL_MEM) { - ret = read_guest_pa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); } else { - ret = read_guest_va_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } + + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; } if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { - PrintError("Could not decode instruction\n"); + PrintError(info->vm_info, info, "Could not decode instruction\n"); return -1; } @@ -68,7 +74,7 @@ int v3_handle_cr0_write(struct guest_info * info) { return -1; } } else { - PrintError("Unhandled opcode in handle_cr0_write\n"); + PrintError(info->vm_info, info, "Unhandled opcode in handle_cr0_write\n"); return -1; } @@ -90,12 +96,12 @@ static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_in struct cr0_32 * guest_cr0 = (struct cr0_32 *)&(info->shdw_pg_state.guest_cr0); uint_t paging_transition = 0; - PrintDebug("MOV2CR0 (MODE=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); + PrintDebug(info->vm_info, info, "MOV2CR0 (MODE=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); - PrintDebug("OperandVal = %x, length=%d\n", *(uint_t *)new_cr0, dec_instr->src_operand.size); + PrintDebug(info->vm_info, info, "OperandVal = %x, length=%d\n", *(uint_t *)new_cr0, dec_instr->src_operand.size); - PrintDebug("Old CR0=%x\n", *(uint_t *)shadow_cr0); - PrintDebug("Old Guest CR0=%x\n", *(uint_t *)guest_cr0); + PrintDebug(info->vm_info, info, "Old CR0=%x\n", *(uint_t *)shadow_cr0); + PrintDebug(info->vm_info, info, "Old Guest CR0=%x\n", *(uint_t *)guest_cr0); // We detect if this is a paging transition @@ -107,13 +113,18 @@ static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_in *guest_cr0 = *new_cr0; // This value must always be set to 1 - guest_cr0->et = 1; + guest_cr0->et = 1; // Set the shadow register to catch non-virtualized flags *shadow_cr0 = *guest_cr0; // Paging is always enabled - shadow_cr0->pg = 1; + shadow_cr0->pg = 1; + + if (guest_cr0->pg == 0) { + // If paging is not enabled by the guest, then we always enable write-protect to catch memory hooks + shadow_cr0->wp = 1; + } // Was there a paging transition // Meaning we need to change the page tables @@ -125,19 +136,19 @@ static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_in // Check long mode LME to set LME if (guest_efer->lme == 1) { - PrintDebug("Enabing Long Mode\n"); + PrintDebug(info->vm_info, info, "Enabing Long Mode\n"); guest_efer->lma = 1; shadow_efer->lma = 1; shadow_efer->lme = 1; - PrintDebug("New EFER %p\n", (void *)*(addr_t *)(shadow_efer)); + PrintDebug(info->vm_info, info, "New EFER %p\n", (void *)*(addr_t *)(shadow_efer)); } - PrintDebug("Activating Shadow Page Tables\n"); + PrintDebug(info->vm_info, info, "Activating Shadow Page Tables\n"); if (v3_activate_shadow_pt(info) == -1) { - PrintError("Failed to activate shadow page tables\n"); + PrintError(info->vm_info, info, "Failed to activate shadow page tables\n"); return -1; } } else { @@ -145,15 +156,15 @@ static int handle_mov_to_cr0(struct guest_info * info, struct x86_instr * dec_in shadow_cr0->wp = 1; if (v3_activate_passthrough_pt(info) == -1) { - PrintError("Failed to activate passthrough page tables\n"); + PrintError(info->vm_info, info, "Failed to activate passthrough page tables\n"); return -1; } } } - PrintDebug("New Guest CR0=%x\n",*(uint_t *)guest_cr0); - PrintDebug("New CR0=%x\n", *(uint_t *)shadow_cr0); + PrintDebug(info->vm_info, info, "New Guest CR0=%x\n",*(uint_t *)guest_cr0); + PrintDebug(info->vm_info, info, "New CR0=%x\n", *(uint_t *)shadow_cr0); return 0; } @@ -181,28 +192,28 @@ static int handle_lmsw(struct guest_info * info, struct x86_instr * dec_instr) { struct cr0_real * new_cr0 = (struct cr0_real *)(dec_instr->dst_operand.operand); uchar_t new_cr0_val; - PrintDebug("LMSW\n"); + PrintDebug(info->vm_info, info, "LMSW\n"); new_cr0_val = (*(char*)(new_cr0)) & 0x0f; - PrintDebug("OperandVal = %x\n", new_cr0_val); + PrintDebug(info->vm_info, info, "OperandVal = %x\n", new_cr0_val); // We can just copy the new value through // we don't need to virtualize the lower 4 bits - PrintDebug("Old CR0=%x\n", *(uint_t *)real_cr0); + PrintDebug(info->vm_info, info, "Old CR0=%x\n", *(uint_t *)real_cr0); *(uchar_t*)real_cr0 &= 0xf0; *(uchar_t*)real_cr0 |= new_cr0_val; - PrintDebug("New CR0=%x\n", *(uint_t *)real_cr0); + PrintDebug(info->vm_info, info, "New CR0=%x\n", *(uint_t *)real_cr0); // If Shadow paging is enabled we push the changes to the virtualized copy of cr0 if (info->shdw_pg_mode == SHADOW_PAGING) { struct cr0_real * guest_cr0 = (struct cr0_real*)&(info->shdw_pg_state.guest_cr0); - PrintDebug("Old Guest CR0=%x\n", *(uint_t *)guest_cr0); + PrintDebug(info->vm_info, info, "Old Guest CR0=%x\n", *(uint_t *)guest_cr0); *(uchar_t*)guest_cr0 &= 0xf0; *(uchar_t*)guest_cr0 |= new_cr0_val; - PrintDebug("New Guest CR0=%x\n", *(uint_t *)guest_cr0); + PrintDebug(info->vm_info, info, "New Guest CR0=%x\n", *(uint_t *)guest_cr0); } return 0; } @@ -219,19 +230,23 @@ int v3_handle_cr0_read(struct guest_info * info) { struct x86_instr dec_instr; if (info->mem_mode == PHYSICAL_MEM) { - ret = read_guest_pa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); } else { - ret = read_guest_va_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } + + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; } - if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { - PrintError("Could not decode instruction\n"); + PrintError(info->vm_info, info, "Could not decode instruction\n"); return -1; } if (dec_instr.op_type == V3_OP_MOVCR2) { - PrintDebug("MOVCR2 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); + PrintDebug(info->vm_info, info, "MOVCR2 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); if ((v3_get_vm_cpu_mode(info) == LONG) || (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) { @@ -245,7 +260,7 @@ int v3_handle_cr0_read(struct guest_info * info) { *dst_reg = *shadow_cr0; } - PrintDebug("returned CR0: %p\n", (void *)*(addr_t *)dst_reg); + PrintDebug(info->vm_info, info, "returned CR0: %p\n", (void *)*(addr_t *)dst_reg); } else { struct cr0_32 * dst_reg = (struct cr0_32 *)(dec_instr.dst_operand.operand); @@ -257,7 +272,7 @@ int v3_handle_cr0_read(struct guest_info * info) { *dst_reg = *shadow_cr0; } - PrintDebug("returned CR0: %x\n", *(uint_t*)dst_reg); + PrintDebug(info->vm_info, info, "returned CR0: %x\n", *(uint_t*)dst_reg); } } else if (dec_instr.op_type == V3_OP_SMSW) { @@ -265,7 +280,7 @@ int v3_handle_cr0_read(struct guest_info * info) { struct cr0_real * dst_reg = (struct cr0_real *)(dec_instr.dst_operand.operand); char cr0_val = *(char*)shadow_cr0 & 0x0f; - PrintDebug("SMSW\n"); + PrintDebug(info->vm_info, info, "SMSW\n"); // The lower 4 bits of the guest/shadow CR0 are mapped through // We can treat nested and shadow paging the same here @@ -273,7 +288,7 @@ int v3_handle_cr0_read(struct guest_info * info) { *(char *)dst_reg |= cr0_val; } else { - PrintError("Unhandled opcode in handle_cr0_read\n"); + PrintError(info->vm_info, info, "Unhandled opcode in handle_cr0_read\n"); return -1; } @@ -293,21 +308,26 @@ int v3_handle_cr3_write(struct guest_info * info) { struct x86_instr dec_instr; if (info->mem_mode == PHYSICAL_MEM) { - ret = read_guest_pa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); } else { - ret = read_guest_va_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } + + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; } if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { - PrintError("Could not decode instruction\n"); + PrintError(info->vm_info, info, "Could not decode instruction\n"); return -1; } if (dec_instr.op_type == V3_OP_MOV2CR) { - PrintDebug("MOV2CR3 (cpu_mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); + PrintDebug(info->vm_info, info, "MOV2CR3 (cpu_mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); if (info->shdw_pg_mode == SHADOW_PAGING) { - PrintDebug("Old Shadow CR3=%p; Old Guest CR3=%p\n", + PrintDebug(info->vm_info, info, "Old Shadow CR3=%p; Old Guest CR3=%p\n", (void *)(addr_t)(info->ctrl_regs.cr3), (void*)(addr_t)(info->shdw_pg_state.guest_cr3)); @@ -324,33 +344,15 @@ int v3_handle_cr3_write(struct guest_info * info) { } -#ifdef CONFIG_CRAY_XT - - // If Paging is enabled in the guest then we need to change the shadow page tables - if (info->mem_mode == VIRTUAL_MEM) { - if (info->shdw_pg_state.prev_guest_cr3 != info->shdw_pg_state.guest_cr3) { - if (v3_activate_shadow_pt(info) == -1) { - PrintError("Failed to activate 32 bit shadow page table\n"); - return -1; - } - } - } - - info->shdw_pg_state.prev_guest_cr3 = info->shdw_pg_state.guest_cr3; -#else - // If Paging is enabled in the guest then we need to change the shadow page tables if (info->mem_mode == VIRTUAL_MEM) { if (v3_activate_shadow_pt(info) == -1) { - PrintError("Failed to activate 32 bit shadow page table\n"); + PrintError(info->vm_info, info, "Failed to activate 32 bit shadow page table\n"); return -1; } } - -#endif - - PrintDebug("New Shadow CR3=%p; New Guest CR3=%p\n", + PrintDebug(info->vm_info, info, "New Shadow CR3=%p; New Guest CR3=%p\n", (void *)(addr_t)(info->ctrl_regs.cr3), (void*)(addr_t)(info->shdw_pg_state.guest_cr3)); @@ -369,7 +371,7 @@ int v3_handle_cr3_write(struct guest_info * info) { } } else { - PrintError("Unhandled opcode in handle_cr3_write\n"); + PrintError(info->vm_info, info, "Unhandled opcode in handle_cr3_write\n"); return -1; } @@ -388,18 +390,23 @@ int v3_handle_cr3_read(struct guest_info * info) { struct x86_instr dec_instr; if (info->mem_mode == PHYSICAL_MEM) { - ret = read_guest_pa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); } else { - ret = read_guest_va_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } + + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; } if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { - PrintError("Could not decode instruction\n"); + PrintError(info->vm_info, info, "Could not decode instruction\n"); return -1; } if (dec_instr.op_type == V3_OP_MOVCR2) { - PrintDebug("MOVCR32 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); + PrintDebug(info->vm_info, info, "MOVCR32 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); if (info->shdw_pg_mode == SHADOW_PAGING) { @@ -430,7 +437,7 @@ int v3_handle_cr3_read(struct guest_info * info) { } } else { - PrintError("Unhandled opcode in handle_cr3_read\n"); + PrintError(info->vm_info, info, "Unhandled opcode in handle_cr3_read\n"); return -1; } @@ -440,13 +447,66 @@ int v3_handle_cr3_read(struct guest_info * info) { } -// We don't need to virtualize CR4, all we need is to detect the activation of PAE +//return guest cr4 - shadow PAE is always on int v3_handle_cr4_read(struct guest_info * info) { - // PrintError("CR4 Read not handled\n"); - // Do nothing... + uchar_t instr[15]; + int ret; + struct x86_instr dec_instr; + + if (info->mem_mode == PHYSICAL_MEM) { + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } else { + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } + + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; + } + + if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { + PrintError(info->vm_info, info, "Could not decode instruction\n"); + return -1; + } + if (dec_instr.op_type != V3_OP_MOVCR2) { + PrintError(info->vm_info, info, "Invalid opcode in read CR4\n"); + return -1; + } + + if (info->shdw_pg_mode == SHADOW_PAGING) { + + if ((v3_get_vm_cpu_mode(info) == LONG) || + (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) { + struct cr4_64 * dst_reg = (struct cr4_64 *)(dec_instr.dst_operand.operand); + struct cr4_64 * guest_cr4 = (struct cr4_64 *)&(info->ctrl_regs.cr4); + *dst_reg = *guest_cr4; + } + else { + struct cr4_32 * dst_reg = (struct cr4_32 *)(dec_instr.dst_operand.operand); + struct cr4_32 * guest_cr4 = (struct cr4_32 *)&(info->shdw_pg_state.guest_cr4); + *dst_reg = *guest_cr4; + } + + } else if (info->shdw_pg_mode == NESTED_PAGING) { + + + if ((v3_get_vm_cpu_mode(info) == LONG) || + (v3_get_vm_cpu_mode(info) == LONG_32_COMPAT)) { + struct cr4_64 * dst_reg = (struct cr4_64 *)(dec_instr.dst_operand.operand); + struct cr4_64 * guest_cr4 = (struct cr4_64 *)&(info->ctrl_regs.cr4); + *dst_reg = *guest_cr4; + } else { + struct cr4_32 * dst_reg = (struct cr4_32 *)(dec_instr.dst_operand.operand); + struct cr4_32 * guest_cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4); + *dst_reg = *guest_cr4; + } + } + + info->rip += dec_instr.instr_length; return 0; } + int v3_handle_cr4_write(struct guest_info * info) { uchar_t instr[15]; int ret; @@ -455,26 +515,33 @@ int v3_handle_cr4_write(struct guest_info * info) { v3_cpu_mode_t cpu_mode = v3_get_vm_cpu_mode(info); if (info->mem_mode == PHYSICAL_MEM) { - ret = read_guest_pa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); } else { - ret = read_guest_va_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); } + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; + } + + if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { - PrintError("Could not decode instruction\n"); + PrintError(info->vm_info, info, "Could not decode instruction\n"); return -1; } if (dec_instr.op_type != V3_OP_MOV2CR) { - PrintError("Invalid opcode in write to CR4\n"); + PrintError(info->vm_info, info, "Invalid opcode in write to CR4\n"); return -1; } // Check to see if we need to flush the tlb + if (v3_get_vm_mem_mode(info) == VIRTUAL_MEM) { struct cr4_32 * new_cr4 = (struct cr4_32 *)(dec_instr.src_operand.operand); - struct cr4_32 * cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4); + struct cr4_32 * cr4 = (struct cr4_32 *)&(info->shdw_pg_state.guest_cr4); // if pse, pge, or pae have changed while PG (in any mode) is on // the side effect is a TLB flush, which means we need to @@ -485,8 +552,8 @@ int v3_handle_cr4_write(struct guest_info * info) { if ((cr4->pse != new_cr4->pse) || (cr4->pge != new_cr4->pge) || (cr4->pae != new_cr4->pae)) { - PrintDebug("Handling PSE/PGE/PAE -> TLBFlush case, flag set\n"); - flush_tlb=1; + PrintDebug(info->vm_info, info, "Handling PSE/PGE/PAE -> TLBFlush case, flag set\n"); + flush_tlb = 1; } } @@ -494,100 +561,273 @@ int v3_handle_cr4_write(struct guest_info * info) { if ((cpu_mode == PROTECTED) || (cpu_mode == PROTECTED_PAE)) { struct cr4_32 * new_cr4 = (struct cr4_32 *)(dec_instr.src_operand.operand); - struct cr4_32 * cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4); - - PrintDebug("OperandVal = %x, length = %d\n", *(uint_t *)new_cr4, dec_instr.src_operand.size); - PrintDebug("Old CR4=%x\n", *(uint_t *)cr4); + struct cr4_32 * shadow_cr4 = (struct cr4_32 *)&(info->ctrl_regs.cr4); + struct cr4_32 * guest_cr4 = (struct cr4_32 *)&(info->shdw_pg_state.guest_cr4); + PrintDebug(info->vm_info, info, "OperandVal = %x, length = %d\n", *(uint_t *)new_cr4, dec_instr.src_operand.size); + PrintDebug(info->vm_info, info, "Old guest CR4=%x\n", *(uint_t *)guest_cr4); if ((info->shdw_pg_mode == SHADOW_PAGING)) { if (v3_get_vm_mem_mode(info) == PHYSICAL_MEM) { - if ((cr4->pae == 0) && (new_cr4->pae == 1)) { - PrintDebug("Creating PAE passthrough tables\n"); + if ((guest_cr4->pae == 0) && (new_cr4->pae == 1)) { + PrintDebug(info->vm_info, info, "Creating PAE passthrough tables\n"); // create 32 bit PAE direct map page table if (v3_reset_passthrough_pts(info) == -1) { - PrintError("Could not create 32 bit PAE passthrough pages tables\n"); + PrintError(info->vm_info, info, "Could not create 32 bit PAE passthrough pages tables\n"); return -1; } // reset cr3 to new page tables info->ctrl_regs.cr3 = *(addr_t*)&(info->direct_map_pt); - } else if ((cr4->pae == 1) && (new_cr4->pae == 0)) { + } else if ((guest_cr4->pae == 1) && (new_cr4->pae == 0)) { // Create passthrough standard 32bit pagetables - PrintError("Switching From PAE to Protected mode not supported\n"); + PrintError(info->vm_info, info, "Switching From PAE to Protected mode not supported\n"); return -1; } } } - *cr4 = *new_cr4; - PrintDebug("New CR4=%x\n", *(uint_t *)cr4); + *guest_cr4 = *new_cr4; + *shadow_cr4 = *guest_cr4; + shadow_cr4->pae = 1; // always on for the shadow pager + PrintDebug(info->vm_info, info, "New guest CR4=%x and shadow CR4=%x\n", *(uint_t *)guest_cr4,*(uint_t*)shadow_cr4); } else if ((cpu_mode == LONG) || (cpu_mode == LONG_32_COMPAT)) { struct cr4_64 * new_cr4 = (struct cr4_64 *)(dec_instr.src_operand.operand); struct cr4_64 * cr4 = (struct cr4_64 *)&(info->ctrl_regs.cr4); - PrintDebug("Old CR4=%p\n", (void *)*(addr_t *)cr4); - PrintDebug("New CR4=%p\n", (void *)*(addr_t *)new_cr4); + PrintDebug(info->vm_info, info, "Old CR4=%p\n", (void *)*(addr_t *)cr4); + PrintDebug(info->vm_info, info, "New CR4=%p\n", (void *)*(addr_t *)new_cr4); if (new_cr4->pae == 0) { // cannot turn off PAE in long mode GPF the guest - PrintError("Cannot disable PAE in long mode, should send GPF\n"); + PrintError(info->vm_info, info, "Cannot disable PAE in long mode, should send GPF\n"); return -1; } *cr4 = *new_cr4; } else { - PrintError("CR4 write not supported in CPU_MODE: %s\n", v3_cpu_mode_to_str(cpu_mode)); + PrintError(info->vm_info, info, "CR4 write not supported in CPU_MODE: %s\n", v3_cpu_mode_to_str(cpu_mode)); return -1; } - - if (flush_tlb) { - PrintDebug("Handling PSE/PGE/PAE -> TLBFlush (doing flush now!)\n"); - if (v3_activate_shadow_pt(info) == -1) { - PrintError("Failed to activate shadow page tables when emulating TLB flush in handling cr4 write\n"); - return -1; + if (info->shdw_pg_mode == SHADOW_PAGING) { + if (flush_tlb) { + PrintDebug(info->vm_info, info, "Handling PSE/PGE/PAE -> TLBFlush (doing flush now!)\n"); + if (v3_activate_shadow_pt(info) == -1) { + PrintError(info->vm_info, info, "Failed to activate shadow page tables when emulating TLB flush in handling cr4 write\n"); + return -1; + } } } - info->rip += dec_instr.instr_length; return 0; } -int v3_handle_efer_read(uint_t msr, struct v3_msr * dst, void * priv_data) { - struct guest_info * info = (struct guest_info *)(priv_data); - PrintDebug("EFER Read HI=%x LO=%x\n", info->shdw_pg_state.guest_efer.hi, info->shdw_pg_state.guest_efer.lo); +/* + The CR8 and APIC TPR interaction are kind of crazy. + + CR8 mandates that the priority class is in bits 3:0 + + The interaction of CR8 and an actual APIC is somewhat implementation dependent, but + a basic current APIC has the priority class at 7:4 and the *subclass* at 3:0 + + The APIC TPR (both fields) can be written as the APIC register + A write to CR8 sets the priority class field, and should zero the subclass + A read from CR8 gets just the priority class field + + In the apic_tpr storage location, we have: + + zeros [class] [subclass] + + Because of this, an APIC implementation should use apic_tpr to store its TPR + In fact, it *should* do this, otherwise its TPR may get out of sync with the architected TPR + + On a CR8 read, we return just + + zeros 0000 [class] + + On a CR8 write, we set the register to + + zeros [class] 0000 + +*/ + +int v3_handle_cr8_write(struct guest_info * info) { + int ret; + uchar_t instr[15]; + struct x86_instr dec_instr; - dst->value = info->shdw_pg_state.guest_efer.value; + if (info->mem_mode == PHYSICAL_MEM) { + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } else { + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } + + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; + } + + if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { + PrintError(info->vm_info, info, "Could not decode instruction\n"); + return -1; + } + + if (dec_instr.op_type == V3_OP_MOV2CR) { + PrintDebug(info->vm_info, info, "MOV2CR8 (cpu_mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); + + if ((info->cpu_mode == LONG) || + (info->cpu_mode == LONG_32_COMPAT)) { + uint64_t *val = (uint64_t *)(dec_instr.src_operand.operand); + + info->ctrl_regs.apic_tpr = (*val & 0xf) << 4; + + V3_Print(info->vm_info, info, "Write of CR8 sets apic_tpr to 0x%llx\n",info->ctrl_regs.apic_tpr); + + } else { + // probably should raise exception here + } + } else { + PrintError(info->vm_info, info, "Unhandled opcode in handle_cr8_write\n"); + return -1; + } + + info->rip += dec_instr.instr_length; return 0; } -// TODO: this is a disaster we need to clean this up... -int v3_handle_efer_write(uint_t msr, struct v3_msr src, void * priv_data) { - struct guest_info * info = (struct guest_info *)(priv_data); - //struct efer_64 * new_efer = (struct efer_64 *)&(src.value); - struct efer_64 * shadow_efer = (struct efer_64 *)&(info->ctrl_regs.efer); - struct v3_msr * guest_efer = &(info->shdw_pg_state.guest_efer); +int v3_handle_cr8_read(struct guest_info * info) { + uchar_t instr[15]; + int ret; + struct x86_instr dec_instr; - PrintDebug("EFER Write\n"); - PrintDebug("EFER Write Values: HI=%x LO=%x\n", src.hi, src.lo); - //PrintDebug("Old EFER=%p\n", (void *)*(addr_t*)(shadow_efer)); + if (info->mem_mode == PHYSICAL_MEM) { + ret = v3_read_gpa_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } else { + ret = v3_read_gva_memory(info, get_addr_linear(info, info->rip, &(info->segments.cs)), 15, instr); + } - // We virtualize the guests efer to hide the SVME and LMA bits - guest_efer->value = src.value; + if (ret!=15) { + PrintError(info->vm_info, info, "Could not read instruction\n"); + return -1; + } + if (v3_decode(info, (addr_t)instr, &dec_instr) == -1) { + PrintError(info->vm_info, info, "Could not decode instruction\n"); + return -1; + } - // Enable/Disable Syscall - shadow_efer->sce = src.value & 0x1; + if (dec_instr.op_type == V3_OP_MOVCR2) { + PrintDebug(info->vm_info, info, "MOVCR82 (mode=%s)\n", v3_cpu_mode_to_str(info->cpu_mode)); + + if ((info->cpu_mode == LONG) || + (info->cpu_mode == LONG_32_COMPAT)) { + uint64_t *dst_reg = (uint64_t *)(dec_instr.dst_operand.operand); + + *dst_reg = (info->ctrl_regs.apic_tpr >> 4) & 0xf; + + V3_Print(info->vm_info, info, "Read of CR8 (apic_tpr) returns 0x%llx\n",*dst_reg); + + } else { + // probably should raise exception + } + + } else { + PrintError(info->vm_info, info, "Unhandled opcode in handle_cr8_read\n"); + return -1; + } + + info->rip += dec_instr.instr_length; + + return 0; +} + + +int v3_handle_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * dst, void * priv_data) { + PrintDebug(core->vm_info, core, "EFER Read HI=%x LO=%x\n", core->shdw_pg_state.guest_efer.hi, core->shdw_pg_state.guest_efer.lo); + + dst->value = core->shdw_pg_state.guest_efer.value; + + return 0; +} + + +int v3_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) { + struct v3_msr * vm_efer = &(core->shdw_pg_state.guest_efer); + struct efer_64 * hw_efer = (struct efer_64 *)&(core->ctrl_regs.efer); + struct efer_64 old_hw_efer = *((struct efer_64 *)&core->ctrl_regs.efer); + + PrintDebug(core->vm_info, core, "EFER Write HI=%x LO=%x\n", src.hi, src.lo); + + // Set EFER value seen by guest if it reads EFER + vm_efer->value = src.value; + + // Set EFER value seen by hardware while the guest is running + *(uint64_t *)hw_efer = src.value; + + // We have gotten here either because we are using + // shadow paging, or we are using nested paging on SVM + // In the latter case, we don't need to do anything + // like the following + if (core->shdw_pg_mode == SHADOW_PAGING) { + // Catch unsupported features + if ((old_hw_efer.lme == 1) && (hw_efer->lme == 0)) { + PrintError(core->vm_info, core, "Disabling long mode once it has been enabled is not supported\n"); + return -1; + } + + // Set LME and LMA bits seen by hardware + if (old_hw_efer.lme == 0) { + // Long mode was not previously enabled, so the lme bit cannot + // be set yet. It will be set later when the guest sets CR0.PG + // to enable paging. + hw_efer->lme = 0; + } else { + // Long mode was previously enabled. Ensure LMA bit is set. + // VMX does not automatically set LMA, and this should not affect SVM. + hw_efer->lma = 1; + } + } + + + PrintDebug(core->vm_info, core, "RIP=%p\n", (void *)core->rip); + PrintDebug(core->vm_info, core, "New EFER value HW(hi=%p), VM(hi=%p)\n", (void *)*(uint64_t *)hw_efer, (void *)vm_efer->value); + + + return 0; +} + +int v3_handle_vm_cr_read(struct guest_info * core, uint_t msr, struct v3_msr * dst, void * priv_data) { + /* tell the guest that the BIOS disabled SVM, that way it doesn't get + * confused by the fact that CPUID reports SVM as available but it still + * cannot be used + */ + dst->value = SVM_VM_CR_MSR_lock | SVM_VM_CR_MSR_svmdis; + PrintDebug(core->vm_info, core, "VM_CR Read HI=%x LO=%x\n", dst->hi, dst->lo); + return 0; +} + +int v3_handle_vm_cr_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) { + PrintDebug(core->vm_info, core, "VM_CR Write\n"); + PrintDebug(core->vm_info, core, "VM_CR Write Values: HI=%x LO=%x\n", src.hi, src.lo); + + /* writes to LOCK and SVMDIS are silently ignored (according to the spec), + * other writes indicate the guest wants to use some feature we haven't + * implemented + */ + if (src.value & ~(SVM_VM_CR_MSR_lock | SVM_VM_CR_MSR_svmdis)) { + PrintDebug(core->vm_info, core, "VM_CR write sets unsupported bits: HI=%x LO=%x\n", src.hi, src.lo); + return -1; + } return 0; }