X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fpiix3.c;h=b482b488e59576fdb46a2cf893b0448f5b62e1a2;hb=eb2dd607efd35a1521ae6a707e0a2178dd1f74ee;hp=ab82bdbcc135ff32638d3c9e5a2d6a9843e5f586;hpb=6d6988cc9c8bac21d96afd800076afe0915cf2cd;p=palacios.git

diff --git a/palacios/src/devices/piix3.c b/palacios/src/devices/piix3.c
index ab82bdb..b482b48 100644
--- a/palacios/src/devices/piix3.c
+++ b/palacios/src/devices/piix3.c
@@ -74,7 +74,7 @@ struct top_of_mem_reg {
 	uint8_t value;
 	struct {
 	    uint8_t rsvd1                    : 1;
-	    uint8_t isadma_reg_fwd_en        : 1;
+    uint8_t isadma_reg_fwd_en        : 1;
 	    uint8_t piix_rsvd                : 1;
 	    uint8_t isadma_lo_bios_fwd_en    : 1;
 	    uint8_t top_of_mem               : 4;
@@ -361,7 +361,15 @@ static int reset_piix3(struct v3_southbridge * piix3) {
 }
 
 
-//irq is pirq_rc[intr_pin + pci_dev_num - 1] & 0x3
+//irq is pirq_rc[intr_pin + pci_dev_num - 1] & 0xf
+/*
+struct pirq_rc_reg {
+       uint8_t irq         : 4;
+       uint8_t rsvd        : 3;
+       uint8_t disabled    : 1; // (1=disabled, 0=enabled)
+}
+*/
+
 
 static int raise_pci_irq(struct pci_device * pci_dev, void * dev_data) {
     struct v3_southbridge * piix3 = dev_data;
@@ -369,10 +377,27 @@ static int raise_pci_irq(struct pci_device * pci_dev, void * dev_data) {
     struct piix3_config_space * piix3_cfg = (struct piix3_config_space *)(piix3_pci->config_data);
     int intr_pin = pci_dev->config_header.intr_pin - 1;
     int irq_index = (intr_pin + pci_dev->dev_num - 1) & 0x3;
+
+    /*
+    PrintError("Raising PCI dev %d intr %d via IOAPIC as IRQ %d and via PIRQ as IRQ %d on VM %p\n", 
+	       pci_dev->dev_num, pci_dev->config_header.intr_pin, 
+	       16+irq_index,
+	       piix3_cfg->pirq_rc[irq_index], piix3->vm);
+    */
+
+    // deliver first by PIRQ, if it exists
+    //
+    if (piix3_cfg->pirq_rc[irq_index] < 16) {
+	v3_raise_irq(piix3->vm, piix3_cfg->pirq_rc[irq_index] & 0xf);
+    } else {
+      // not an error
+    }
+
+    // deliver next via the PCI0 to ioapic mapping defined in the 
+    // mptable (ioapic, pins 16->19 are used for PCI0)
+    // ideally this would check to verify that an ioapic is actually available
+    v3_raise_irq(piix3->vm, 16+irq_index);
     
-    //PrintError("Raising PCI IRQ %d, %p\n", piix3_cfg->pirq_rc[irq_index], piix3->vm);
-    
-    v3_raise_irq(piix3->vm, piix3_cfg->pirq_rc[irq_index]);
 
     return 0;
 }
@@ -387,8 +412,16 @@ static int lower_pci_irq(struct pci_device * pci_dev, void * dev_data) {
     int irq_index = (intr_pin + pci_dev->dev_num - 1) & 0x3;
     
     //    PrintError("Lowering PCI IRQ %d\n", piix3_cfg->pirq_rc[irq_index]);
+
+    // First, lower the pin on the ioapic
+    v3_lower_irq(piix3->vm, irq_index+16);
     
-    v3_lower_irq(piix3->vm, piix3_cfg->pirq_rc[irq_index]);
+    // Next, lower whatever we asserted by the PIRQs
+    if (piix3_cfg->pirq_rc[irq_index] < 16) {
+	v3_lower_irq(piix3->vm, piix3_cfg->pirq_rc[irq_index] & 0xf);
+    } else {
+      // not an error
+    }
 
     return 0;
 }