X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fpci.c;h=ef57cdb71a674d7ac7e40547631a6113e1a89950;hb=3c86fc75c137455a3cc45d7383c6bca69a4f7168;hp=42077e975a24525bb03a562c20333f3ec6076cfc;hpb=95ca28a23f949b13c857ba0b061a2ca465683e8e;p=palacios.git

diff --git a/palacios/src/devices/pci.c b/palacios/src/devices/pci.c
index 42077e9..ef57cdb 100644
--- a/palacios/src/devices/pci.c
+++ b/palacios/src/devices/pci.c
@@ -315,6 +315,21 @@ static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_de
 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
     if (header_type == 0x00) {
 	switch (reg_num) {
+	    case 0x00:
+	    case 0x01:
+	    case 0x02:
+	    case 0x03:
+	    case 0x08:
+	    case 0x09:
+	    case 0x0a:
+	    case 0x0b:
+	    case 0x0e:
+	    case 0x3d:
+		return 0;
+                           
+           default:
+               return 1;
+ 
 	    // case (non writable reg list):
 	    
 	    default:
@@ -374,6 +389,7 @@ static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_d
 		// COMMAND update
 	    } else if (cur_reg == 0x0f) {
 		// BIST update
+		pci_dev->config_header.BIST = 0x00;
 	    }
 	}
     }
@@ -385,10 +401,16 @@ static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_d
     // Scan for BAR updated
     if (pci_dev->bar_update_flag) {
 	for (i = 0; i < 6; i++) {
-	    if ((pci_dev->bar[i].updated) && (pci_dev->bar[i].bar_update)) {
-		pci_dev->bar[i].bar_update(pci_dev, i);
+	    if (pci_dev->bar[i].updated) {
+		int bar_offset = 0x10 + 4 * i;
+
+		*(uint32_t *)pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
+
+		if (pci_dev->bar[i].bar_update) {
+		    pci_dev->bar[i].bar_update(pci_dev, i);
+		}
+		pci_dev->bar[i].updated = 0;
 	    }
-	    pci_dev->bar[i].updated = 0;
 	}
 	pci_dev->bar_update_flag = 0;
     }
@@ -521,6 +543,37 @@ struct vm_device * v3_create_pci() {
 
 
 
+static inline int init_bars(struct pci_device * pci_dev) {
+    int i = 0;
+
+    for (i = 0; i < 6; i++) {
+	int bar_offset = 0x10 + 4 * i;
+
+	if (pci_dev->bar[i].type == PCI_BAR_IO) {
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000001;
+	} else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
+	    pci_dev->bar[i].mask = (pci_dev->bar[i].num_pages << 12) - 1;
+	    pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
+	     
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000008;
+	    
+	    if (pci_dev->bar[i].mem_hook) {
+		// clear the prefetchable flag...
+		*(uint8_t *)(pci_dev->config_space + bar_offset) &= ~0x00000008;
+	    }
+	} else if (pci_dev->bar[i].type == PCI_BAR_MEM16) {
+	    PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
+	} else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000000;
+	} else {
+	    PrintError("Invalid BAR type for bar #%d\n", i);
+	    return -1;
+	}
+	    
+
+    }
+}
+
 
 
 // if dev_num == -1, auto assign 
@@ -565,7 +618,7 @@ struct pci_device * v3_pci_register_device(struct vm_device * pci,
     }
 
     memset(pci_dev, 0, sizeof(struct pci_device));
-	
+    
     
     pci_dev->bus_num = bus_num;
     pci_dev->dev_num = dev_num;
@@ -582,12 +635,16 @@ struct pci_device * v3_pci_register_device(struct vm_device * pci,
     
     //copy bars
     for (i = 0; i < 6; i ++){
-      pci_dev->bar[i].updated = bars[i].updated;
       pci_dev->bar[i].type = bars[i].type;
       pci_dev->bar[i].num_resources = bars[i].num_resources;
       pci_dev->bar[i].bar_update = bars[i].bar_update;
     }
 
+    if (init_bars(pci_dev) == -1) {
+	PrintError("could not initialize bar registers\n");
+	return NULL;
+    }
+
     pci_dev->cmd_update = cmd_update;
     pci_dev->ext_rom_update = ext_rom_update;