X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fpci.c;h=ad53670453fb001cb8c3a853988039ff6ab2d4e1;hb=db77959ea07c25b21177bad78509ef7c82412fe8;hp=91623848d90b4bb9d95f576fe93d8129e77ce3d5;hpb=643fbf6c339a64667edc263063de8f3345b82b3d;p=palacios.git

diff --git a/palacios/src/devices/pci.c b/palacios/src/devices/pci.c
index 9162384..ad53670 100644
--- a/palacios/src/devices/pci.c
+++ b/palacios/src/devices/pci.c
@@ -125,7 +125,7 @@ static int get_free_dev_num(struct pci_bus * bus) {
 	    // availability
 	    for (j = 0; j < 8; j++) {
 		if (!(bus->dev_map[i] & (0x1 << j))) {
-		    return i * 8 + j;
+		    return ((i * 8) + j);
 		}
 	    }
 	}
@@ -135,7 +135,7 @@ static int get_free_dev_num(struct pci_bus * bus) {
 }
 
 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
-    int major = dev_num / 8;
+    int major = (dev_num / 8);
     int minor = dev_num % 8;
 
     bus->dev_map[major] |= (0x1 << minor);
@@ -216,7 +216,7 @@ static int addr_port_read(ushort_t port, void * dst, uint_t length, struct vm_de
     int reg_offset = port & 0x3;
     uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
 
-    PrintDebug("Reading PCI Address Port (%x): %x\n", port, pci_state->addr_reg.val);
+    PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
 
     if (length == 4) {
 	if (reg_offset != 0) {
@@ -276,38 +276,47 @@ static int addr_port_write(ushort_t port, void * src, uint_t length, struct vm_d
 
     PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
 
-
     return length;
 }
 
 
 static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * vmdev) {
-    struct pci_internal * pci_state =  (struct pci_internal *)vmdev->private_data;;
+    struct pci_internal * pci_state =  (struct pci_internal *)(vmdev->private_data);
     struct pci_device * pci_dev = NULL;
-    uint_t reg_num = pci_state->addr_reg.reg_num + (port & 0x3);
+    uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
     int i;
 
+    if (pci_state->addr_reg.bus_num != 0) {
+	int i = 0;
+	for (i = 0; i < length; i++) {
+	    *((uint8_t *)dst + i) = 0xff;
+	}
+
+	return length;
+    }
+
     PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n", 
 	       pci_state->addr_reg.bus_num, 
 	       pci_state->addr_reg.dev_num, 
 	       reg_num, reg_num, 
 	       pci_state->addr_reg.val);
 
-
     pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num);
     
     if (pci_dev == NULL) {
 	for (i = 0; i < length; i++) {
-	    *((uint8_t *)dst + i) = 0xff;
+	    *(uint8_t *)((uint8_t *)dst + i) = 0xff;
 	}
 
 	return length;
     }
 
     for (i = 0; i < length; i++) {
-	*((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
+	*(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
     }
-    
+
+    PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
+
     return length;
 }
 
@@ -315,10 +324,21 @@ static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_de
 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
     if (header_type == 0x00) {
 	switch (reg_num) {
-	    // case (non writable reg list):
-	    
-	    default:
-		return 1;
+	    case 0x00:
+	    case 0x01:
+	    case 0x02:
+	    case 0x03:
+	    case 0x08:
+	    case 0x09:
+	    case 0x0a:
+	    case 0x0b:
+	    case 0x0e:
+	    case 0x3d:
+		return 0;
+                           
+           default:
+               return 1;
+ 
 	}
     } else {
 	// PCI to PCI Bridge = 0x01
@@ -332,17 +352,29 @@ static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
 }
 
 
+static int bar_update(struct pci_device * pci, int bar_num) {
+    PrintError("Bar Updates not handled (bar=%d)\n", bar_num);
+    return -1;
+}
+
+
 static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_device * vmdev) {
-    struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;;
+    struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;
     struct pci_device * pci_dev = NULL;
-    uint_t reg_num = pci_state->addr_reg.reg_num + (port & 0x3);
+    uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
     int i;
 
-    PrintDebug("Writing PCI Data register. bus = %d, dev = %d, reg = %d (%x) addr_reg = %x\n", 
+
+    if (pci_state->addr_reg.bus_num != 0) {
+	return length;
+    }
+
+    PrintDebug("Writing PCI Data register. bus = %d, dev = %d, reg = %d (%x) addr_reg = %x (val=%x, len=%d)\n", 
 	       pci_state->addr_reg.bus_num, 
 	       pci_state->addr_reg.dev_num, 
 	       reg_num, reg_num, 
-	       pci_state->addr_reg.val);
+	       pci_state->addr_reg.val,
+	       *(uint32_t *)src, length);
 
 
     pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num);
@@ -355,15 +387,69 @@ static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_d
     
 
     for (i = 0; i < length; i++) {
-	if (is_cfg_reg_writable(pci_dev->config_header.header_type, reg_num)) {
-	    pci_dev->config_space[reg_num + i] = *((uint8_t *)src + i);
+	uint_t cur_reg = reg_num + i;
+	
+	if (is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg)) {
+	    pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
+
+	    if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
+		// BAR Reg
+		int bar_reg = (cur_reg & ~0x3) - 0x10;
+		
+		pci_dev->bar_update_flag = 1;
+		pci_dev->bar[bar_reg].updated = 1;
+		
+		PrintDebug("Updating BAR register\n");
+
+	    } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
+		pci_dev->ext_rom_update_flag = 1;
+	    } else if (cur_reg == 0x04) {
+		// COMMAND update	     
+		uint8_t command = *((uint8_t *)src + i);
+		
+		pci_dev->config_space[cur_reg] = command;	      
+		
+		if (pci_dev->cmd_update) {
+		    pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
+		}
+		
+	    } else if (cur_reg == 0x0f) {
+		// BIST update
+		pci_dev->config_header.BIST = 0x00;
+	    }
 	}
     }
 
     if (pci_dev->config_update) {
 	pci_dev->config_update(pci_dev, reg_num, length);
     }
-    
+
+    // Scan for BAR updated
+    if (pci_dev->bar_update_flag) {
+	for (i = 0; i < 6; i++) {
+	    if (pci_dev->bar[i].updated) {
+		int bar_offset = 0x10 + 4 * i;
+
+		*(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
+
+		// bar_update
+		if (bar_update(pci_dev, i) == -1) {
+		    PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
+		    return -1;
+		}
+
+		pci_dev->bar[i].updated = 0;
+	    }
+	}
+	pci_dev->bar_update_flag = 0;
+    }
+
+    if ((pci_dev->ext_rom_update_flag) && (pci_dev->ext_rom_update)) {
+	pci_dev->ext_rom_update(pci_dev);
+	pci_dev->ext_rom_update_flag = 0;
+    }
+
+
     return length;
 }
 
@@ -403,11 +489,19 @@ static int pci_deinit_device(struct vm_device * dev) {
 
 
 static int init_i440fx(struct vm_device * dev) {
-    struct pci_device * pci_dev = v3_pci_register_device(dev, 0, "i440FX", 0, 
-							 NULL, NULL);
+    struct pci_device * pci_dev = NULL;
+    struct v3_pci_bar bars[6];
+    int i;
+    
+    for (i = 0; i < 6; i++) {
+	bars[i].type = PCI_BAR_NONE;
+    }    
+
+    pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "i440FX", 0, bars,
+				     NULL, NULL, NULL, NULL);
     
     if (!pci_dev) {
-	return -1;
+ 	return -1;
     }
     
     pci_dev->config_header.vendor_id = 0x8086;
@@ -415,15 +509,14 @@ static int init_i440fx(struct vm_device * dev) {
     pci_dev->config_header.revision = 0x0002;
     pci_dev->config_header.subclass = 0x00; //  SubClass: host2pci
     pci_dev->config_header.class = 0x06;    // Class: PCI bridge
-    pci_dev->config_header.header_type = 0x00;
 
     pci_dev->bus_num = 0;
-    
     return 0;
 }
 
 
 
+
 static void init_pci_busses(struct pci_internal * pci_state) {
     int i;
 
@@ -454,6 +547,8 @@ static int pci_init_device(struct vm_device * dev) {
 	return -1;
     }
     
+    PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
+    
     for (i = 0; i < 4; i++) {
 	v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
 	v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
@@ -484,16 +579,79 @@ struct vm_device * v3_create_pci() {
 
 
 
+static inline int init_bars(struct pci_device * pci_dev) {
+    int i = 0;
+
+    for (i = 0; i < 6; i++) {
+	int bar_offset = 0x10 + (4 * i);
+
+	if (pci_dev->bar[i].type == PCI_BAR_IO) {
+	    int j = 0;
+	    pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
+	    
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) |= 0x00000001;
+
+	    for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
+		// hook IO
+		if (v3_dev_hook_io(pci_dev->vm_dev, pci_dev->bar[i].default_base_port + j,
+				   pci_dev->bar[i].io_read, pci_dev->bar[i].io_write) == -1) {
+		    PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
+		    return -1;
+		}
+	    }
+
+	} else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
+	    pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
+	    pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
+
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
+
+	    // hook memory
+	    if (pci_dev->bar[i].mem_read) {
+		// full hook
+		v3_hook_full_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
+				 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
+				 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->vm_dev);
+	    } else if (pci_dev->bar[i].mem_write) {
+		// write hook
+		PrintError("Write hooks not supported for PCI devices\n");
+		return -1;
+		/*
+		  v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr, 
+		  pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
+		  pci_dev->bar[i].mem_write, pci_dev->vm_dev);
+		*/
+ 	    } else {
+		// set the prefetchable flag...
+		*(uint8_t *)(pci_dev->config_space + bar_offset) |= 0x00000008;
+	    }
+
+	} else if (pci_dev->bar[i].type == PCI_BAR_MEM16) {
+	    PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
+	    return -1;
+	} else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
+	    *(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000000;
+	} else {
+	    PrintError("Invalid BAR type for bar #%d\n", i);
+	    return -1;
+	}
+    }
+
+    return 0;
+}
 
 
 // if dev_num == -1, auto assign 
 struct pci_device * v3_pci_register_device(struct vm_device * pci,
+					   pci_device_type_t dev_type, 
 					   uint_t bus_num,
 					   const char * name,
 					   int dev_num,
 					   struct v3_pci_bar * bars,
 					   int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
-					   int (*cmd_update)(struct pci_dev *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
+					   int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
+					   int (*ext_rom_update)(struct pci_device * pci_dev),
 					   void * private_data) {
 
     struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
@@ -527,34 +685,56 @@ struct pci_device * v3_pci_register_device(struct vm_device * pci,
     }
 
     memset(pci_dev, 0, sizeof(struct pci_device));
-	
     
+    
+    switch (dev_type) {
+	case PCI_STD_DEVICE:
+	    pci_dev->config_header.header_type = 0x00;
+	    break;
+	default:
+	    PrintError("Unhandled PCI Device Type: %d\n", dev_type);
+	    return NULL;
+    }
+
     pci_dev->bus_num = bus_num;
     pci_dev->dev_num = dev_num;
 
     strncpy(pci_dev->name, name, sizeof(pci_dev->name));
     pci_dev->vm_dev = pci;
 
+    // register update callbacks
     pci_dev->config_update = config_update;
+    pci_dev->cmd_update = cmd_update;
+    pci_dev->ext_rom_update = ext_rom_update;
 
     pci_dev->priv_data = private_data;
 
-    
+
     //copy bars
     for (i = 0; i < 6; i ++){
-      pci_dev->bar[i].updated = bars[i].updated;
-      pci_dev->bar[i].type = bars[i].type;
-      pci_dev->bar[i].num_resources = bars[i].num_resources;
-      pci_dev->bar[i].bar_update = bars[i].bar_update;
+	pci_dev->bar[i].type = bars[i].type;
+
+	if (pci_dev->bar[i].type == PCI_BAR_IO) {
+	    pci_dev->bar[i].num_ports = bars[i].num_ports;
+	    pci_dev->bar[i].default_base_port = bars[i].default_base_port;
+	    pci_dev->bar[i].io_read = bars[i].io_read;
+	    pci_dev->bar[i].io_write = bars[i].io_write;
+	} else {
+	    pci_dev->bar[i].num_pages = bars[i].num_pages;
+	    pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
+	    pci_dev->bar[i].mem_read = bars[i].mem_read;
+	    pci_dev->bar[i].mem_write = bars[i].mem_write;
+	}
     }
 
-    pci_dev->cmd_update = cmd_update;
-    pci_dev->ext_rom_update = ext_rom_update;
+    if (init_bars(pci_dev) == -1) {
+	PrintError("could not initialize bar registers\n");
+	return NULL;
+    }
 
     // add the device
     add_device_to_bus(bus, pci_dev);
 
-    
 #ifdef DEBUG_PCI
     pci_dump_state(pci_state);
 #endif