X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fio_apic.c;h=0d7c3dc14e375c17a41f1a63ee270db8e24e5b0c;hb=4dd1b9b1f155688a8196c1bc9f32f74275511718;hp=3579fdecbdf1755ae159ed58963cee290888d275;hpb=94f67717b6461df514dc225ed84f03b44c44061b;p=palacios.git

diff --git a/palacios/src/devices/io_apic.c b/palacios/src/devices/io_apic.c
index 3579fde..0d7c3dc 100644
--- a/palacios/src/devices/io_apic.c
+++ b/palacios/src/devices/io_apic.c
@@ -267,6 +267,17 @@ static int ioapic_raise_irq(struct v3_vm_info * vm, void * private_data, int irq
     struct io_apic_state * ioapic = (struct io_apic_state *)(private_data);  
     struct redir_tbl_entry * irq_entry = NULL;
 
+    if (irq==0) { 
+      // IRQ 0 being raised, in the Palacios context, means the PIT
+      // However, the convention is that it is the PIC that is connected
+      // to PIN 0 of the IOAPIC and the PIT is connected to pin 2
+      // Hence we convert this to the relvant pin.  In the future,
+      // the PIC may signal to the IOAPIC in a different path.
+      // Yes, this is kind of hideous, but it is needed to have the
+      // PIT correctly show up via the IOAPIC
+      irq=2;
+    }
+
     if (irq > 24) {
 	PrintDebug("ioapic %u: IRQ out of range of IO APIC\n", ioapic->ioapic_id.id);
 	return -1;
@@ -325,10 +336,42 @@ static int io_apic_free(struct io_apic_state * ioapic) {
     return 0;
 }
 
+#ifdef V3_CONFIG_CHECKPOINT
+static int io_apic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+    struct io_apic_state * io_apic = (struct io_apic_state *)private_data;
+
+    V3_CHKPT_STD_SAVE(ctx, io_apic->base_addr);
+    V3_CHKPT_STD_SAVE(ctx, io_apic->index_reg);
+    V3_CHKPT_STD_SAVE(ctx, io_apic->ioapic_id);
+    V3_CHKPT_STD_SAVE(ctx, io_apic->ioapic_ver);
+    V3_CHKPT_STD_SAVE(ctx, io_apic->ioapic_arb_id);
+    V3_CHKPT_STD_SAVE(ctx, io_apic->redir_tbl);
+
+    return 0;
+}
+
+static int io_apic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+    struct io_apic_state * io_apic = (struct io_apic_state *)private_data;
+
+    V3_CHKPT_STD_LOAD(ctx, io_apic->base_addr);
+    V3_CHKPT_STD_LOAD(ctx, io_apic->index_reg);
+    V3_CHKPT_STD_LOAD(ctx, io_apic->ioapic_id);
+    V3_CHKPT_STD_LOAD(ctx, io_apic->ioapic_ver);
+    V3_CHKPT_STD_LOAD(ctx, io_apic->ioapic_arb_id);
+    V3_CHKPT_STD_LOAD(ctx, io_apic->redir_tbl);
+
+    return 0;
+}
+#endif
+
+
 
 static struct v3_device_ops dev_ops = {
     .free = (int (*)(void *))io_apic_free,
-
+#ifdef V3_CONFIG_CHECKPOINT
+    .save = io_apic_save, 
+    .load = io_apic_load
+#endif
 };