X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fide.c;h=562688fe408ff9819a2455bbd4da03d5bfc5f183;hb=a7dc3322984b3c76fe990de506418e180ec1b0de;hp=43858a45340a8e0ab1a79db74b28edf573b616ce;hpb=a3843aa9457ed5a02159fd5a83620426b0a0f3fe;p=palacios.git diff --git a/palacios/src/devices/ide.c b/palacios/src/devices/ide.c index 43858a4..562688f 100644 --- a/palacios/src/devices/ide.c +++ b/palacios/src/devices/ide.c @@ -24,6 +24,11 @@ #include "ide-types.h" #include "atapi-types.h" +#ifndef DEBUG_IDE +#undef PrintDebug +#define PrintDebug(fmt, args...) +#endif + #define PRI_DEFAULT_IRQ 14 #define SEC_DEFAULT_IRQ 15 @@ -54,7 +59,6 @@ #define PRI_DEFAULT_DMA_PORT 0xc000 #define SEC_DEFAULT_DMA_PORT 0xc008 - #define DATA_BUFFER_SIZE 2048 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM", @@ -90,7 +94,7 @@ static inline const char * dma_port_to_str(uint16_t port) { } -static const char * ide_dev_type_strs[] = {"HARDDISK", "CDROM", "NONE"}; +static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" }; static inline const char * device_type_to_str(v3_ide_dev_type_t type) { @@ -105,13 +109,22 @@ static inline const char * device_type_to_str(v3_ide_dev_type_t type) { struct ide_cd_state { struct atapi_sense_data sense; - uint_t current_lba; + uint8_t atapi_cmd; struct atapi_error_recovery err_recovery; }; struct ide_hd_state { + int accessed; + /* this is the multiple sector transfer size as configured for read/write multiple sectors*/ + uint_t mult_sector_num; + + /* This is the current op sector size: + * for multiple sector ops this equals mult_sector_num + * for standard ops this equals 1 + */ + uint_t cur_sector_num; }; struct ide_drive { @@ -139,6 +152,7 @@ struct ide_drive { // calculated for easy access uint_t transfer_length; + uint64_t current_lba; // We have a local data buffer that we use for IO port accesses uint8_t data_buf[DATA_BUFFER_SIZE]; @@ -154,24 +168,23 @@ struct ide_drive { union { uint8_t sector_num; // 0x1f3,0x173 uint8_t lba0; - }; + } __attribute__((packed)); union { uint16_t cylinder; uint16_t lba12; - - + struct { uint8_t cylinder_low; // 0x1f4,0x174 uint8_t cylinder_high; // 0x1f5,0x175 } __attribute__((packed)); - + struct { uint8_t lba1; uint8_t lba2; } __attribute__((packed)); - - + + // The transfer length requested by the CPU uint16_t req_len; } __attribute__((packed)); @@ -211,11 +224,16 @@ struct ide_channel { struct ide_internal { struct ide_channel channels[2]; struct vm_device * pci; + struct vm_device * southbridge; struct pci_device * busmaster_pci; }; + + +/* Utility functions */ + static inline uint16_t be_to_le_16(const uint16_t val) { uint8_t * buf = (uint8_t *)&val; return (buf[0] << 8) | (buf[1]) ; @@ -265,6 +283,7 @@ static inline int is_lba_enabled(struct ide_channel * channel) { } +/* Drive Commands */ static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) { if (channel->ctrl_reg.irq_disable == 0) { PrintDebug("Raising IDE Interrupt %d\n", channel->irq); @@ -277,11 +296,14 @@ static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) static void drive_reset(struct ide_drive * drive) { drive->sector_count = 0x01; drive->sector_num = 0x01; + + PrintDebug("Resetting drive %s\n", drive->model); if (drive->drive_type == IDE_CDROM) { drive->cylinder = 0xeb14; } else { drive->cylinder = 0x0000; + //drive->hd_state.accessed = 0; } @@ -326,18 +348,25 @@ static void ide_abort_command(struct vm_device * dev, struct ide_channel * chann } -// Include the ATAPI interface handlers + + + + +/* ATAPI functions */ #include "atapi.h" +/* ATA functions */ +#include "ata.h" + +/* IO Operations */ static int dma_read(struct vm_device * dev, struct ide_channel * channel) { struct ide_drive * drive = get_selected_drive(channel); struct ide_dma_prd prd_entry; uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index); int ret; - PrintDebug("PRD table address = %x\n", channel->dma_prd_addr); ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry); @@ -356,11 +385,7 @@ static int dma_read(struct vm_device * dev, struct ide_channel * channel) { return -1; } - channel->status.busy = 0; - channel->status.ready = 1; - channel->status.data_req = 0; - channel->status.error = 0; - channel->status.seek_complete = 1; + /* drive->irq_flags.io_dir = 1; @@ -370,9 +395,18 @@ static int dma_read(struct vm_device * dev, struct ide_channel * channel) { // set DMA status - channel->dma_status.active = 0; - channel->dma_status.err = 1; - channel->dma_status.int_gen = 1; + + if (prd_entry.end_of_table) { + channel->dma_status.active = 0; + channel->dma_status.err = 0; + channel->dma_status.int_gen = 1; + + channel->status.busy = 0; + channel->status.ready = 1; + channel->status.data_req = 0; + channel->status.error = 0; + channel->status.seek_complete = 1; + } ide_raise_irq(dev, channel); @@ -454,6 +488,8 @@ static int write_dma_port(ushort_t port_offset, void * src, uint_t length, return -1; } } + + channel->dma_cmd.val &= 0x09; } break; @@ -560,7 +596,39 @@ static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_de channel->cmd_reg = *(uint8_t *)src; switch (channel->cmd_reg) { - + + case 0xa1: // ATAPI Identify Device Packet + if (drive->drive_type != IDE_CDROM) { + drive_reset(drive); + + // JRL: Should we abort here? + ide_abort_command(dev, channel); + } else { + + atapi_identify_device(drive); + + channel->error_reg.val = 0; + channel->status.val = 0x58; // ready, data_req, seek_complete + + ide_raise_irq(dev, channel); + } + break; + case 0xec: // Identify Device + if (drive->drive_type != IDE_DISK) { + drive_reset(drive); + + // JRL: Should we abort here? + ide_abort_command(dev, channel); + } else { + ata_identify_device(drive); + + channel->error_reg.val = 0; + channel->status.val = 0x58; + + ide_raise_irq(dev, channel); + } + break; + case 0xa0: // ATAPI Command Packet if (drive->drive_type != IDE_CDROM) { ide_abort_command(dev, channel); @@ -578,26 +646,31 @@ static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_de drive->transfer_index = 0; break; - case 0xa1: // ATAPI Identify Device Packet - atapi_identify_device(drive); - channel->error_reg.val = 0; - channel->status.val = 0x58; // ready, data_req, seek_complete - - ide_raise_irq(dev, channel); + case 0x20: // Read Sectors with Retry + case 0x21: // Read Sectors without Retry + drive->hd_state.cur_sector_num = 1; + + if (ata_read_sectors(dev, channel) == -1) { + PrintError("Error reading sectors\n"); + return -1; + } break; - case 0xec: // Identify Device - if (drive->drive_type != IDE_DISK) { - drive_reset(drive); - // JRL: Should we abort here? - ide_abort_command(dev, channel); - } else { - PrintError("IDE Disks currently not implemented\n"); + case 0x24: // Read Sectors Extended + drive->hd_state.cur_sector_num = 1; + + if (ata_read_sectors_ext(dev, channel) == -1) { + PrintError("Error reading extended sectors\n"); return -1; } break; + case 0xc8: // Read DMA with retry + case 0xc9: // Read DMA + drive->hd_state.cur_sector_num = 1; + + break; case 0xef: // Set Features // Prior to this the features register has been written to. // This command tells the drive to check if the new value is supported (the value is drive specific) @@ -614,6 +687,38 @@ static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_de ide_raise_irq(dev, channel); break; + + case 0x91: // Initialize Drive Parameters + case 0x10: // recalibrate? + channel->status.error = 0; + channel->status.ready = 1; + channel->status.seek_complete = 1; + ide_raise_irq(dev, channel); + break; + case 0xc6: { // Set multiple mode (IDE Block mode) + // This makes the drive transfer multiple sectors before generating an interrupt + uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS + + if (tmp_sect_num > MAX_MULT_SECTORS) { + ide_abort_command(dev, channel); + break; + } + + if (drive->sector_count == 0) { + drive->hd_state.mult_sector_num= 1; + } else { + drive->hd_state.mult_sector_num = drive->sector_count; + } + + channel->status.ready = 1; + channel->status.error = 0; + + ide_raise_irq(dev, channel); + + break; + } + case 0xc4: // read multiple sectors + drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num; default: PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg); return -1; @@ -658,15 +763,78 @@ static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_d static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) { - PrintError("Harddrive data port read not implemented\n"); - return -1; + struct ide_drive * drive = get_selected_drive(channel); + int data_offset = drive->transfer_index % IDE_SECTOR_SIZE; + + + + if (drive->transfer_index >= drive->transfer_length) { + PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n", + drive->transfer_length, drive->transfer_index, + drive->transfer_index + length); + return -1; + } + + + if ((data_offset == 0) && (drive->transfer_index > 0)) { + drive->current_lba++; + + if (ata_read(dev, channel, drive->data_buf, 1) == -1) { + PrintError("Could not read next disk sector\n"); + return -1; + } + } + + /* + PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n", + *(uint32_t *)(drive->data_buf + data_offset), + length, data_offset); + */ + memcpy(dst, drive->data_buf + data_offset, length); + + drive->transfer_index += length; + + + /* This is the trigger for interrupt injection. + * For read single sector commands we interrupt after every sector + * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num) + * cur_sector_num is configured depending on the operation we are currently running + * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count + */ + if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) || + (drive->transfer_index == drive->transfer_length)) { + if (drive->transfer_index < drive->transfer_length) { + // An increment is complete, but there is still more data to be transferred... + PrintDebug("Integral Complete, still transferring more sectors\n"); + channel->status.data_req = 1; + + drive->irq_flags.c_d = 0; + } else { + PrintDebug("Final Sector Transferred\n"); + // This was the final read of the request + channel->status.data_req = 0; + + + drive->irq_flags.c_d = 1; + drive->irq_flags.rel = 0; + } + + channel->status.ready = 1; + drive->irq_flags.io_dir = 1; + channel->status.busy = 0; + + ide_raise_irq(dev, channel); + } + + + return length; } static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) { struct ide_drive * drive = get_selected_drive(channel); - int data_offset = drive->transfer_index % DATA_BUFFER_SIZE; + int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE; int req_offset = drive->transfer_index % drive->req_len; if (drive->cd_state.atapi_cmd != 0x28) { @@ -683,14 +851,8 @@ static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, st if ((data_offset == 0) && (drive->transfer_index > 0)) { - - if (drive->drive_type == IDE_CDROM) { - if (atapi_update_data_buf(dev, channel) == -1) { - PrintError("Could not update CDROM data buffer\n"); - return -1; - } - } else { - PrintError("IDE Harddrives not implemented\n"); + if (atapi_update_data_buf(dev, channel) == -1) { + PrintError("Could not update CDROM data buffer\n"); return -1; } } @@ -699,6 +861,8 @@ static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, st drive->transfer_index += length; + + // Should the req_offset be recalculated here????? if ((req_offset == 0) && (drive->transfer_index > 0)) { if (drive->transfer_index < drive->transfer_length) { // An increment is complete, but there is still more data to be transferred... @@ -817,21 +981,25 @@ static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_de case PRI_SECT_CNT_PORT: case SEC_SECT_CNT_PORT: - drive->sector_count = *(uint8_t *)src; + channel->drives[0].sector_count = *(uint8_t *)src; + channel->drives[1].sector_count = *(uint8_t *)src; break; case PRI_SECT_NUM_PORT: case SEC_SECT_NUM_PORT: - drive->sector_num = *(uint8_t *)src; - + channel->drives[0].sector_num = *(uint8_t *)src; + channel->drives[1].sector_num = *(uint8_t *)src; + break; case PRI_CYL_LOW_PORT: case SEC_CYL_LOW_PORT: - drive->cylinder_low = *(uint8_t *)src; + channel->drives[0].cylinder_low = *(uint8_t *)src; + channel->drives[1].cylinder_low = *(uint8_t *)src; break; case PRI_CYL_HIGH_PORT: case SEC_CYL_HIGH_PORT: - drive->cylinder_high = *(uint8_t *)src; + channel->drives[0].cylinder_high = *(uint8_t *)src; + channel->drives[1].cylinder_high = *(uint8_t *)src; break; case PRI_DRV_SEL_PORT: @@ -962,7 +1130,6 @@ static void init_drive(struct ide_drive * drive) { memset(drive->data_buf, 0, sizeof(drive->data_buf)); - drive->private_data = NULL; drive->cd_ops = NULL; } @@ -990,80 +1157,81 @@ static void init_channel(struct ide_channel * channel) { static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) { - PrintDebug("Interupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line); + PrintDebug("PCI Config Update\n"); + PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line); return 0; } static int init_ide_state(struct vm_device * dev) { struct ide_internal * ide = (struct ide_internal *)(dev->private_data); - struct v3_pci_bar bars[6]; - struct pci_device * pci_dev = NULL; int i, j; - for (i = 0; i < 2; i++) { + + /* + Check if the PIIX 3 actually represents both IDE channels in a single PCI entry */ + + for (i = 0; i < 1; i++) { init_channel(&(ide->channels[i])); // JRL: this is a terrible hack... ide->channels[i].irq = PRI_DEFAULT_IRQ + i; - for (j = 0; j < 6; j++) { - bars[j].type = PCI_BAR_NONE; - } + if (ide->pci) { + struct v3_pci_bar bars[6]; + struct pci_device * pci_dev = NULL; - bars[4].type = PCI_BAR_IO; - bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8); - bars[4].num_ports = 8; - - if (i == 0) { - bars[4].io_read = read_pri_dma_port; - bars[4].io_write = write_pri_dma_port; - } else { - bars[4].io_read = read_sec_dma_port; - bars[4].io_write = write_sec_dma_port; - } - - pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars, - pci_config_update, NULL, NULL, dev); + for (j = 0; j < 6; j++) { + bars[j].type = PCI_BAR_NONE; + } - if (pci_dev == NULL) { - PrintError("Failed to register IDE BUS %d with PCI\n", i); - return -1; - } - ide->channels[i].pci_dev = pci_dev; + bars[4].type = PCI_BAR_IO; + bars[4].default_base_port = PRI_DEFAULT_DMA_PORT + (i * 0x8); + bars[4].num_ports = 8; + + if (i == 0) { + bars[4].io_read = read_pri_dma_port; + bars[4].io_write = write_pri_dma_port; + } else { + bars[4].io_read = read_sec_dma_port; + bars[4].io_write = write_sec_dma_port; + } - pci_dev->config_header.vendor_id = 0x1095; - pci_dev->config_header.device_id = 0x0646; - pci_dev->config_header.revision = 0x8f07; - pci_dev->config_header.subclass = 0x01; - pci_dev->config_header.class = 0x01; + pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars, + pci_config_update, NULL, NULL, dev); - pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i; - pci_dev->config_header.intr_pin = 1; - } + if (pci_dev == NULL) { + PrintError("Failed to register IDE BUS %d with PCI\n", i); + return -1; + } + ide->channels[i].pci_dev = pci_dev; + /* This is for CMD646 devices + pci_dev->config_header.vendor_id = 0x1095; + pci_dev->config_header.device_id = 0x0646; + pci_dev->config_header.revision = 0x8f07; + */ + pci_dev->config_header.vendor_id = 0x8086; + pci_dev->config_header.device_id = 0x7010; + pci_dev->config_header.revision = 0x8000; + + pci_dev->config_header.subclass = 0x01; + pci_dev->config_header.class = 0x01; + + + pci_dev->config_header.command = 0; + pci_dev->config_header.status = 0x0280; + + // pci_dev->config_header.intr_line = PRI_DEFAULT_IRQ + i; + // pci_dev->config_header.intr_pin = 1; + } + - /* Register PIIX3 Busmaster PCI device */ - for (j = 0; j < 6; j++) { - bars[j].type = PCI_BAR_NONE; } - pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars, - NULL, NULL, NULL, dev); - - - ide->busmaster_pci = pci_dev; - - pci_dev->config_header.vendor_id = 0x8086; - pci_dev->config_header.device_id = 0x7010; - pci_dev->config_header.revision = 0x80; - pci_dev->config_header.subclass = 0x01; - pci_dev->config_header.class = 0x01; - - return 0; } @@ -1148,11 +1316,12 @@ static struct vm_device_ops dev_ops = { }; -struct vm_device * v3_create_ide(struct vm_device * pci) { +struct vm_device * v3_create_ide(struct vm_device * pci, struct vm_device * southbridge) { struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal)); struct vm_device * device = v3_create_device("IDE", &dev_ops, ide); ide->pci = pci; + ide->southbridge = southbridge; PrintDebug("IDE: Creating IDE bus x 2\n"); @@ -1228,9 +1397,15 @@ int v3_ide_register_harddisk(struct vm_device * ide_dev, drive->drive_type = IDE_DISK; + drive->hd_state.accessed = 0; + drive->hd_state.mult_sector_num = 1; + drive->hd_ops = ops; drive->private_data = private_data; return 0; } + + +