X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fapic.c;h=c437c630522a532e0c8c3cbefe4a293b71910bca;hb=ae0d9f72adc43c791ac13037285385fd8bb3c206;hp=6fceccf04255bb4b61d8db93168a89799ffe6ec8;hpb=afed1e7a0d44d1fd59816e1ccf9563caceee0fcc;p=palacios.releases.git diff --git a/palacios/src/devices/apic.c b/palacios/src/devices/apic.c index 6fceccf..c437c63 100644 --- a/palacios/src/devices/apic.c +++ b/palacios/src/devices/apic.c @@ -120,7 +120,7 @@ typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT, struct apic_msr { union { - uint64_t val; + uint64_t value; struct { uchar_t rsvd; uint_t bootstrap_cpu : 1; @@ -139,7 +139,7 @@ struct apic_state { addr_t base_addr; /* MSRs */ - v3_msr_t base_addr_msr; + struct apic_msr base_addr_msr; /* memory map registers */ @@ -191,13 +191,23 @@ struct apic_state { static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data); static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data); -static void init_apic_state(struct apic_state * apic) { +static void init_apic_state(struct apic_state * apic, uint32_t id, struct vm_device * icc) { apic->base_addr = DEFAULT_BASE_ADDR; - apic->base_addr_msr.value = 0x0000000000000900LL; + if (id==0) { + // boot processor, enabled + apic->base_addr_msr.value = 0x0000000000000900LL; + } else { + // ap processor, enabled + apic->base_addr_msr.value = 0x0000000000000800LL; + } + + // same base address regardless of ap or main apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR); - PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n", - (uint_t)sizeof(apic->int_req_reg)); + PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value); + + PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n", + id, (uint_t)sizeof(apic->int_req_reg)); memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg)); memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg)); @@ -209,9 +219,9 @@ static void init_apic_state(struct apic_state * apic) { apic->tmr_init_cnt = 0x00000000; apic->tmr_cur_cnt = 0x00000000; - // TODO: - // We need to figure out what the APIC ID is.... - apic->lapic_id.val = 0x00000000; + apic->lapic_id.val = id; + + apic->icc_bus = icc; // The P6 has 6 LVT entries, so we set the value to (6-1)... apic->apic_ver.val = 0x80050010; @@ -247,6 +257,7 @@ static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, v struct apic_state * apics = (struct apic_state *)(dev->private_data); struct apic_state * apic = &(apics[core->cpu_id]); + PrintDebug("apic %u: core %u: MSR read\n",apic->lapic_id.val,core->cpu_id); v3_lock(apic->lock); dst->value = apic->base_addr; v3_unlock(apic->lock); @@ -261,9 +272,11 @@ static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, vo struct v3_mem_region * old_reg = v3_get_mem_region(dev->vm, core->cpu_id, apic->base_addr); + PrintDebug("apic %u: core %u: MSR write\n",apic->lapic_id.val,core->cpu_id); + if (old_reg == NULL) { // uh oh... - PrintError("APIC Base address region does not exit...\n"); + PrintError("apic %u: core %u: APIC Base address region does not exit...\n",apic->lapic_id.val,core->cpu_id); return -1; } @@ -274,7 +287,7 @@ static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, vo apic->base_addr = src.value; if (v3_hook_full_mem(dev->vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev) == -1) { - PrintError("Could not hook new APIC Base address\n"); + PrintError("apic %u: core %u: Could not hook new APIC Base address\n",apic->lapic_id.val,core->cpu_id); v3_unlock(apic->lock); return -1; } @@ -292,12 +305,18 @@ static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) { uchar_t * en_location = apic->int_en_reg + major_offset; uchar_t flag = 0x1 << minor_offset; + +#if 1 + if (irq_num <= 15) { - PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num); +// PrintError("apic %u: core ?: Attempting to raise an invalid interrupt: %d\n", apic->lapic_id.val,irq_num); return -1; } - PrintDebug("Raising APIC IRQ %d\n", irq_num); +#endif + + + PrintDebug("apic %u: core ?: Raising APIC IRQ %d\n", apic->lapic_id.val,irq_num); if (*req_location & flag) { //V3_Print("Interrupts coallescing\n"); @@ -306,7 +325,7 @@ static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) { if (*en_location & flag) { *req_location |= flag; } else { - PrintDebug("Interrupt not enabled... %.2x\n", *en_location); + PrintDebug("apic %u: core ?: Interrupt not enabled... %.2x\n", apic->lapic_id.val, *en_location); return 0; } @@ -369,7 +388,7 @@ static int apic_do_eoi(struct apic_state * apic) { uchar_t flag = 0x1 << minor_offset; uchar_t * svc_location = apic->int_svc_reg + major_offset; - PrintDebug("Received APIC EOI for IRQ %d\n", isr_irq); + PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq); *svc_location &= ~flag; @@ -377,7 +396,7 @@ static int apic_do_eoi(struct apic_state * apic) { if ((isr_irq == 238) || (isr_irq == 239)) { - PrintError("Acking IRQ %d\n", isr_irq); + PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq); } if (isr_irq == 238) { @@ -385,7 +404,7 @@ static int apic_do_eoi(struct apic_state * apic) { } #endif } else { - //PrintError("Spurious EOI...\n"); + //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val); } return 0; @@ -430,13 +449,13 @@ static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_t masked = apic->err_vec_tbl.mask; break; default: - PrintError("Invalid APIC interrupt type\n"); + PrintError("apic %u: core ?: Invalid APIC interrupt type\n",apic->lapic_id.val); return -1; } // interrupt is masked, don't send if (masked == 1) { - PrintDebug("Inerrupt is masked\n"); + PrintDebug("apic %u: core ?: Inerrupt is masked\n",apic->lapic_id.val); return 0; } @@ -444,24 +463,24 @@ static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_t //PrintDebug("Activating internal APIC IRQ %d\n", vec_num); return activate_apic_irq(apic, vec_num); } else { - PrintError("Unhandled Delivery Mode\n"); + PrintError("apic %u: core ?: Unhandled Delivery Mode\n",apic->lapic_id.val); return -1; } } static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) { - struct apic_state * apic = (struct apic_state *)priv_data; + struct apic_state * apic = (struct apic_state *)(priv_data); addr_t reg_addr = guest_addr - apic->base_addr; struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value); uint32_t val = 0; - PrintDebug("Read apic address space (%p)\n", - (void *)guest_addr); + PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",apic->lapic_id.val,core->cpu_id, apic, (void *)guest_addr); if (msr->apic_enable == 0) { - PrintError("Write to APIC address space with disabled APIC\n"); + PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",apic->lapic_id.val,core->cpu_id,apic->base_addr_msr.value); + return -1; } @@ -673,8 +692,9 @@ static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, ui case SEOI_OFFSET: default: - PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr); - return -1; + PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n", apic->lapic_id.val,core->cpu_id, (uint32_t)reg_addr); + // return -1; + val=0; } @@ -695,11 +715,11 @@ static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, ui *val_ptr = val; } else { - PrintError("Invalid apic read length (%d)\n", length); + PrintError("apic %u: core %u: Invalid apic read length (%d)\n", apic->lapic_id.val,core->cpu_id, length); return -1; } - PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst); + PrintDebug("apic %u: core %u: Read finished (val=%x)\n", apic->lapic_id.val,core->cpu_id, *(uint32_t *)dst); return length; } @@ -709,22 +729,23 @@ static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, ui * */ static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) { - struct apic_state * apic = (struct apic_state *)priv_data; + struct apic_state * apic = (struct apic_state *)(priv_data); addr_t reg_addr = guest_addr - apic->base_addr; struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value); uint32_t op_val = *(uint32_t *)src; - PrintDebug("Write to apic address space (%p) (val=%x)\n", + PrintDebug("apic %u: core %u: at %p and priv_data is at %p: Write to address space (%p) (val=%x)\n", + apic->lapic_id.val, core->cpu_id, apic,priv_data, (void *)guest_addr, *(uint32_t *)src); if (msr->apic_enable == 0) { - PrintError("Write to APIC address space with disabled APIC\n"); + PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",apic->lapic_id.val,core->cpu_id,apic->base_addr_msr.value); return -1; } if (length != 4) { - PrintError("Invalid apic write length (%d)\n", length); + PrintError("apic %u: core %u: Invalid apic write length (%d)\n", apic->lapic_id.val, length,core->cpu_id); return -1; } @@ -759,15 +780,16 @@ static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, u case PPR_OFFSET: case EXT_APIC_FEATURE_OFFSET: #if 1 - PrintError("Attempting to write to read only register %p (ignored)\n", (void *)reg_addr); + PrintError("apic %u: core %u: Attempting to write to read only register %p (ignored)\n", apic->lapic_id.val,core->cpu_id, (void *)reg_addr); #else - PrintError("Attempting to write to read only register %p (error)\n", (void *)reg_addr); + PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n", apic->lapic_id.val,core->cpu_id, (void *)reg_addr); return -1; #endif break; // Data registers case APIC_ID_OFFSET: + PrintDebug("apic %u: core %u: my id is being changed to %u\n",apic->lapic_id.val,core->cpu_id,op_val); apic->lapic_id.val = op_val; break; case TPR_OFFSET: @@ -864,7 +886,9 @@ static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, u case INT_CMD_LO_OFFSET: apic->int_cmd.lo = op_val; // ICC??? - v3_icc_send_irq(apic->icc_bus, apic->int_cmd.dst, apic->int_cmd.val); + PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",apic->lapic_id.val,core->cpu_id, + apic->int_cmd.val, apic->int_cmd.dst); + v3_icc_send_ipi(apic->icc_bus, apic->lapic_id.val, apic->int_cmd.val,0); break; case INT_CMD_HI_OFFSET: apic->int_cmd.hi = op_val; @@ -874,11 +898,11 @@ static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, u case EXT_APIC_CMD_OFFSET: case SEOI_OFFSET: default: - PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr); - return -1; + PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n", apic->lapic_id.val,core->cpu_id, (uint32_t)reg_addr); + // return -1; } - PrintDebug("Write finished\n"); + PrintDebug("apic %u: core %u: Write finished\n",apic->lapic_id.val,core->cpu_id); return length; } @@ -893,6 +917,8 @@ static int apic_intr_pending(struct guest_info * info, void * private_data) { int req_irq = get_highest_irr(apic); int svc_irq = get_highest_isr(apic); + // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq); + if ((req_irq >= 0) && (req_irq > svc_irq)) { return 1; @@ -932,8 +958,16 @@ static int apic_begin_irq(struct guest_info * info, void * private_data, int irq uchar_t * svc_location = apic->int_svc_reg + major_offset; uchar_t flag = 0x01 << minor_offset; - *svc_location |= flag; - *req_location &= ~flag; + if (*req_location & flag) { + // we will only pay attention to a begin irq if we + // know that we initiated it! + *svc_location |= flag; + *req_location &= ~flag; + } else { + // do nothing... + PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n", + apic->lapic_id.val,info->cpu_id,irq); + } @@ -945,7 +979,7 @@ static int apic_begin_irq(struct guest_info * info, void * private_data, int irq /* Timer Functions */ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) { - struct apic_state * apic = (struct apic_state *)priv_data; + struct apic_state * apic = (struct apic_state *)(priv_data); // The 32 bit GCC runtime is a pile of shit #ifdef __V3_64BIT__ uint64_t tmr_ticks = 0; @@ -963,7 +997,7 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo if ((apic->tmr_init_cnt == 0) || ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) && (apic->tmr_cur_cnt == 0))) { - //PrintDebug("APIC timer not yet initialized\n"); + //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id); return; } @@ -994,7 +1028,7 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo shift_num = 7; break; default: - PrintError("Invalid Timer Divider configuration\n"); + PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",apic->lapic_id.val,info->cpu_id); return; } @@ -1008,15 +1042,15 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo apic->tmr_cur_cnt = 0; // raise irq - PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n", + PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n", apic->lapic_id.val,info->cpu_id, apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num); if (apic_intr_pending(info, priv_data)) { - PrintDebug("Overriding pending IRQ %d\n", apic_get_intr_number(info, priv_data)); + PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n", apic->lapic_id.val,info->cpu_id, apic_get_intr_number(info, priv_data)); } if (activate_internal_irq(apic, APIC_TMR_INT) == -1) { - PrintError("Could not raise Timer interrupt\n"); + PrintError("apic %u: core %u: Could not raise Timer interrupt\n",apic->lapic_id.val,info->cpu_id); } if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) { @@ -1044,6 +1078,9 @@ static struct vm_timer_ops timer_ops = { static int apic_free(struct vm_device * dev) { + + /* TODO: This should crosscall to force an unhook on each CPU */ + // struct apic_state * apic = (struct apic_state *)dev->private_data; v3_unhook_msr(dev->vm, BASE_ADDR_MSR); @@ -1068,25 +1105,26 @@ static struct v3_icc_ops icc_ops = { static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) { - PrintDebug("Creating APIC\n"); - char * name = v3_cfg_val(cfg, "name"); - char * icc_name = v3_cfg_val(cfg,"irq_bus"); - struct vm_device * icc = v3_find_dev(vm, icc_name); + PrintDebug("apic: creating an APIC for each core\n"); + char * dev_id = v3_cfg_val(cfg, "ID"); + char * icc_bus_id = v3_cfg_val(cfg,"bus"); + struct vm_device * icc = v3_find_dev(vm, icc_bus_id); int i; if (!icc) { - PrintError("Cannot find ICC Bus (%s)\n", icc_name); + PrintError("apic: Cannot find ICC Bus (%s)\n", icc_bus_id); return -1; } // We allocate one apic per core // APICs are accessed via index which correlates with the core's cpu_id + // 0..num_cores-1 at num_cores is the ioapic (one only) struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state) * vm->num_cores); - struct vm_device * dev = v3_allocate_device(name, &dev_ops, apic); + struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, apic); if (v3_attach_device(vm, dev) == -1) { - PrintError("Could not attach device %s\n", name); + PrintError("apic: Could not attach device %s\n", dev_id); return -1; } @@ -1094,16 +1132,25 @@ static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) { for (i = 0; i < vm->num_cores; i++) { struct guest_info * core = &(vm->cores[i]); + init_apic_state(&(apic[i]),i,icc); + v3_register_intr_controller(core, &intr_ops, &(apic[i])); + v3_add_timer(core, &timer_ops, &(apic[i])); + v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, &(apic[i])); v3_icc_register_apic(core, icc, i, &icc_ops, &(apic[i])); - init_apic_state(&(apic[i])); - } + PrintDebug("apic %u: (setup device): done, my id is %u\n",i,apic[i].lapic_id.val); + } + for (i=0;inum_cores;i++) { + PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n", + i, &(apic[i]), apic[i].lapic_id.val, apic[i].base_addr_msr.value); + } + PrintDebug("apic: priv_data is at %p\n", apic); v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);