X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fapic.c;h=c051bc87a91249972dbbef80bd60852c4d0bbf4e;hb=0956466aad020813d1e470df366d552fdabab2a9;hp=c8ec4c7b05abae8eeb085f79b591360e2b515462;hpb=2af24dee6386a5fc694d74fa4281dff8b8e2f148;p=palacios.git

diff --git a/palacios/src/devices/apic.c b/palacios/src/devices/apic.c
index c8ec4c7..c051bc8 100644
--- a/palacios/src/devices/apic.c
+++ b/palacios/src/devices/apic.c
@@ -24,12 +24,33 @@
 #include <palacios/vmm_msr.h>
 #include <palacios/vmm_sprintf.h>
 #include <palacios/vm_guest.h>
+#include <palacios/vmm_types.h>
+
 
 #ifndef CONFIG_DEBUG_APIC
 #undef PrintDebug
 #define PrintDebug(fmt, args...)
 #endif
 
+#ifdef CONFIG_DEBUG_APIC
+static char *shorthand_str[] = { 
+    "(no shorthand)",
+    "(self)",
+    "(all)",
+    "(all-but-me)",
+};
+
+static char *deliverymode_str[] = { 
+    "(fixed)",
+    "(lowest priority)",
+    "(SMI)",
+    "(reserved)",
+    "(NMI)",
+    "(INIT)",
+    "(Start Up)",
+    "(ExtInt)",
+};
+#endif
 
 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT, 
 	       APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
@@ -41,7 +62,7 @@ typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
 #define APIC_EXTINT_DELIVERY 0x7
 
 
-#define BASE_ADDR_MSR 0x0000001B
+#define BASE_ADDR_MSR     0x0000001B
 #define DEFAULT_BASE_ADDR 0xfee00000
 
 #define APIC_ID_OFFSET                    0x020
@@ -114,30 +135,33 @@ typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
 #define EXT_INT_LOC_VEC_TBL_OFFSET2       0x520   // 0x500 - 0x530
 #define EXT_INT_LOC_VEC_TBL_OFFSET3       0x530   // 0x500 - 0x530
 
-
-
 struct apic_msr {
     union {
-	uint64_t val;
+	uint64_t value;
 	struct {
-	    uchar_t rsvd;
-	    uint_t bootstrap_cpu : 1;
-	    uint_t rsvd2         : 2;
-	    uint_t apic_enable   : 1;
-	    ullong_t base_addr   : 40;
-	    uint_t rsvd3         : 12;
+	    uint8_t rsvd;
+	    uint8_t bootstrap_cpu : 1;
+	    uint8_t rsvd2         : 2;
+	    uint8_t apic_enable   : 1;
+	    uint64_t base_addr    : 40;
+	    uint32_t rsvd3        : 12;
 	} __attribute__((packed));
     } __attribute__((packed));
 } __attribute__((packed));
 
 
 
+typedef enum {INIT_ST, 
+	      SIPI, 
+	      STARTED} ipi_state_t; 
+
+struct apic_dev_state;
 
 struct apic_state {
     addr_t base_addr;
 
     /* MSRs */
-    v3_msr_t base_addr_msr;
+    struct apic_msr base_addr_msr;
 
 
     /* memory map registers */
@@ -174,28 +198,52 @@ struct apic_state {
     uint32_t rem_rd_data;
 
 
-    uchar_t int_req_reg[32];
-    uchar_t int_svc_reg[32];
-    uchar_t int_en_reg[32];
-    uchar_t trig_mode_reg[32];
-  
-    uint32_t eoi;
+    ipi_state_t ipi_state;
 
+    uint8_t int_req_reg[32];
+    uint8_t int_svc_reg[32];
+    uint8_t int_en_reg[32];
+    uint8_t trig_mode_reg[32];
 
     struct guest_info * core;
+
+    uint32_t eoi;
+
+    v3_lock_t  lock;
 };
 
-static void apic_incoming_ipi(void *val);
-static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data);
-static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data);
 
-static void init_apic_state(struct apic_state * apic) {
+
+
+struct apic_dev_state {
+    int num_apics;
+
+    struct apic_state apics[0];
+} __attribute__((packed));
+
+
+
+static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
+static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
+
+static void init_apic_state(struct apic_state * apic, uint32_t id) {
     apic->base_addr = DEFAULT_BASE_ADDR;
-    apic->base_addr_msr.value = 0x0000000000000900LL;
+
+    if (id == 0) { 
+	// boot processor, enabled
+	apic->base_addr_msr.value = 0x0000000000000900LL;
+    } else {
+	// ap processor, enabled
+	apic->base_addr_msr.value = 0x0000000000000800LL;
+    }
+
+    // same base address regardless of ap or main
     apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR); 
 
-    PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n", 
-	       (uint_t)sizeof(apic->int_req_reg));
+    PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
+
+    PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
+	       id, (uint_t)sizeof(apic->int_req_reg));
 
     memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
     memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
@@ -207,9 +255,9 @@ static void init_apic_state(struct apic_state * apic) {
     apic->tmr_init_cnt = 0x00000000;
     apic->tmr_cur_cnt = 0x00000000;
 
-    // TODO:
-    // We need to figure out what the APIC ID is....
-    apic->lapic_id.val = 0x00000000;
+    apic->lapic_id.val = id;
+    
+    apic->ipi_state = INIT_ST;
 
     // The P6 has 6 LVT entries, so we set the value to (6-1)...
     apic->apic_ver.val = 0x80050010;
@@ -233,39 +281,56 @@ static void init_apic_state(struct apic_state * apic) {
     apic->ext_apic_feature.val = 0x00040007;
     apic->ext_apic_ctrl.val = 0x00000000;
     apic->spec_eoi.val = 0x00000000;
+
+    v3_lock_init(&(apic->lock));
 }
 
 
 
 
-static int read_apic_msr(uint_t msr, v3_msr_t * dst, void * priv_data) {
-    struct vm_device * dev = (struct vm_device *)priv_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
+static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
+
+    PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
+    v3_lock(apic->lock);
     dst->value = apic->base_addr;
+    v3_unlock(apic->lock);
     return 0;
 }
 
 
-static int write_apic_msr(uint_t msr, v3_msr_t src, void * priv_data) {
-    struct vm_device * dev = (struct vm_device *)priv_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
-    struct v3_shadow_region * old_reg = v3_get_shadow_region(dev->vm, apic->base_addr);
+static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
+    struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
+
+
+    PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
 
     if (old_reg == NULL) {
 	// uh oh...
-	PrintError("APIC Base address region does not exit...\n");
+	PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
+		   apic->lapic_id.val, core->cpu_id);
 	return -1;
     }
     
-    v3_delete_shadow_region(dev->vm, old_reg);
+    v3_lock(apic->lock);
+
+    v3_delete_mem_region(core->vm_info, old_reg);
 
     apic->base_addr = src.value;
 
-    if (v3_hook_full_mem(dev->vm, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev) == -1) {
-	PrintError("Could not hook new APIC Base address\n");
+    if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr, 
+			 apic->base_addr + PAGE_SIZE_4KB, 
+			 apic_read, apic_write, apic_dev) == -1) {
+	PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
+		   apic->lapic_id.val, core->cpu_id);
+	v3_unlock(apic->lock);
 	return -1;
     }
 
+    v3_unlock(apic->lock);
     return 0;
 }
 
@@ -274,25 +339,30 @@ static int write_apic_msr(uint_t msr, v3_msr_t src, void * priv_data) {
 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
     int major_offset = (irq_num & ~0x00000007) >> 3;
     int minor_offset = irq_num & 0x00000007;
-    uchar_t * req_location = apic->int_req_reg + major_offset;
-    uchar_t * en_location = apic->int_en_reg + major_offset;
-    uchar_t flag = 0x1 << minor_offset;
+    uint8_t * req_location = apic->int_req_reg + major_offset;
+    uint8_t * en_location = apic->int_en_reg + major_offset;
+    uint8_t flag = 0x1 << minor_offset;
+
+
 
     if (irq_num <= 15) {
-	PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num);
+	PrintError("apic %u: core %d: Attempting to raise an invalid interrupt: %d\n", 
+		   apic->lapic_id.val, apic->core->cpu_id, irq_num);
 	return -1;
     }
 
-    PrintDebug("Raising APIC IRQ %d\n", irq_num);
+
+    PrintDebug("apic %u: core %d: Raising APIC IRQ %d\n", apic->lapic_id.val, apic->core->cpu_id, irq_num);
 
     if (*req_location & flag) {
-	//V3_Print("Interrupts coallescing\n");
+	PrintDebug("Interrupt %d  coallescing\n", irq_num);
     }
 
     if (*en_location & flag) {
 	*req_location |= flag;
     } else {
-	PrintDebug("Interrupt  not enabled... %.2x\n", *en_location);
+	PrintDebug("apic %u: core %d: Interrupt  not enabled... %.2x\n", 
+		   apic->lapic_id.val, apic->core->cpu_id,*en_location);
 	return 0;
     }
 
@@ -306,11 +376,11 @@ static int get_highest_isr(struct apic_state * apic) {
 
     // We iterate backwards to find the highest priority
     for (i = 31; i >= 0; i--) {
-	uchar_t  * svc_major = apic->int_svc_reg + i;
+	uint8_t  * svc_major = apic->int_svc_reg + i;
     
 	if ((*svc_major) & 0xff) {
 	    for (j = 7; j >= 0; j--) {
-		uchar_t flag = 0x1 << j;
+		uint8_t flag = 0x1 << j;
 		if ((*svc_major) & flag) {
 		    return ((i * 8) + j);
 		}
@@ -328,11 +398,11 @@ static int get_highest_irr(struct apic_state * apic) {
 
     // We iterate backwards to find the highest priority
     for (i = 31; i >= 0; i--) {
-	uchar_t  * req_major = apic->int_req_reg + i;
+	uint8_t  * req_major = apic->int_req_reg + i;
     
 	if ((*req_major) & 0xff) {
 	    for (j = 7; j >= 0; j--) {
-		uchar_t flag = 0x1 << j;
+		uint8_t flag = 0x1 << j;
 		if ((*req_major) & flag) {
 		    return ((i * 8) + j);
 		}
@@ -352,10 +422,10 @@ static int apic_do_eoi(struct apic_state * apic) {
     if (isr_irq != -1) {
 	int major_offset = (isr_irq & ~0x00000007) >> 3;
 	int minor_offset = isr_irq & 0x00000007;
-	uchar_t flag = 0x1 << minor_offset;
-	uchar_t * svc_location = apic->int_svc_reg + major_offset;
+	uint8_t flag = 0x1 << minor_offset;
+	uint8_t * svc_location = apic->int_svc_reg + major_offset;
 	
-	PrintDebug("Received APIC EOI for IRQ %d\n", isr_irq);
+	PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
 	
 	*svc_location &= ~flag;
 
@@ -363,7 +433,7 @@ static int apic_do_eoi(struct apic_state * apic) {
 	
 	if ((isr_irq == 238) || 
 	    (isr_irq == 239)) {
-	    PrintError("Acking IRQ %d\n", isr_irq);
+	    PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
 	}
 	
 	if (isr_irq == 238) {
@@ -371,7 +441,7 @@ static int apic_do_eoi(struct apic_state * apic) {
 	}
 #endif
     } else {
-	//PrintError("Spurious EOI...\n");
+	//PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
     }
 	
     return 0;
@@ -416,13 +486,13 @@ static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_t
 	    masked = apic->err_vec_tbl.mask;
 	    break;
 	default:
-	    PrintError("Invalid APIC interrupt type\n");
+	    PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
 	    return -1;
     }
 
     // interrupt is masked, don't send
     if (masked == 1) {
-	PrintDebug("Inerrupt is masked\n");
+	PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
 	return 0;
     }
 
@@ -430,25 +500,312 @@ static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_t
 	//PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
 	return activate_apic_irq(apic, vec_num);
     } else {
-	PrintError("Unhandled Delivery Mode\n");
+	PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
+	return -1;
+    }
+}
+
+
+
+static inline int should_deliver_cluster_ipi(struct guest_info * dst_core, 
+					     struct apic_state * dst_apic, uint8_t mda) {
+
+    if 	( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) &&     // (I am in the cluster and
+	  ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) {  //  I am in the set)
+
+	PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
+		   dst_apic->lapic_id.val, dst_core->cpu_id, mda, 
+		   dst_apic->log_dst.dst_log_id);
+	
+	return 1;
+    } else {
+	PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
+		   dst_apic->lapic_id.val, dst_core->cpu_id, mda, 
+		   dst_apic->log_dst.dst_log_id);
+	return 0;
+    }
+}
+
+static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
+					  struct apic_state * dst_apic, uint8_t mda) {
+
+    if (dst_apic->log_dst.dst_log_id & mda) {  // I am in the set 
+
+	PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
+		   dst_apic->lapic_id.val, dst_core->cpu_id, mda, 
+		   dst_apic->log_dst.dst_log_id);
+      return 1;
+  } else {
+	PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
+		   dst_apic->lapic_id.val, dst_core->cpu_id, mda, 
+		   dst_apic->log_dst.dst_log_id);
+      return 0;
+  }
+}
+
+
+
+static int should_deliver_ipi(struct guest_info * dst_core, 
+			      struct apic_state * dst_apic, uint8_t mda) {
+
+
+    if (dst_apic->dst_fmt.model == 0xf) {
+
+	if (mda == 0xff) {
+	    // always deliver broadcast
+	    return 1;
+	}
+
+	return should_deliver_flat_ipi(dst_core, dst_apic, mda);
+    } else if (dst_apic->dst_fmt.model == 0x0) {
+
+	if (mda == 0xff) {
+	    // always deliver broadcast
+	    return 1;
+	}
+
+	return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
+    } else {
+	PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n", 
+		   dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
+	return -1;
+    }
+}
+
+
+static int deliver_ipi(struct apic_state * src_apic, 
+		       struct apic_state * dst_apic, 
+		       uint32_t vector, uint8_t del_mode) {
+
+    struct guest_info * dst_core = dst_apic->core;
+
+    switch (del_mode) {
+
+	case 0:  //fixed
+	case 1: // lowest priority
+	    PrintDebug("delivering IRQ %d to core %u\n", vector, dst_core->cpu_id); 
+
+	    activate_apic_irq(dst_apic, vector);
+
+	    if (dst_apic != src_apic) { 
+		// Assume core # is same as logical processor for now
+		// TODO FIX THIS FIX THIS
+		// THERE SHOULD BE:  guestapicid->virtualapicid map,
+		//                   cpu_id->logical processor map
+		//     host maitains logical proc->phsysical proc
+		PrintDebug(" non-local core, forcing it to exit\n"); 
+
+		v3_interrupt_cpu(dst_core->vm_info, dst_core->cpu_id, 0);
+	    }
+
+	    break;
+	case 5: { //INIT
+
+	    PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
+
+	    // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
+
+	    // Sanity check
+	    if (dst_apic->ipi_state != INIT_ST) { 
+		PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
+			   dst_core->cpu_id, dst_apic->ipi_state);
+		// Only a warning, since INIT INIT SIPI is common
+		break;
+	    }
+
+	    // We transition the target core to SIPI state
+	    dst_apic->ipi_state = SIPI;  // note: locking should not be needed here
+
+	    // That should be it since the target core should be
+	    // waiting in host on this transition
+	    // either it's on another core or on a different preemptive thread
+	    // in both cases, it will quickly notice this transition 
+	    // in particular, we should not need to force an exit here
+
+	    PrintDebug(" INIT delivery done\n");
+
+	    break;							
+	}
+	case 6: { //SIPI
+
+	    // Sanity check
+	    if (dst_apic->ipi_state != SIPI) { 
+		PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
+			   dst_core->cpu_id, dst_apic->ipi_state);
+		break;
+	    }
+
+	    // Write the RIP, CS, and descriptor
+	    // assume the rest is already good to go
+	    //
+	    // vector VV -> rip at 0
+	    //              CS = VV00
+	    //  This means we start executing at linear address VV000
+	    //
+	    // So the selector needs to be VV00
+	    // and the base needs to be VV000
+	    //
+	    dst_core->rip = 0;
+	    dst_core->segments.cs.selector = vector << 8;
+	    dst_core->segments.cs.limit = 0xffff;
+	    dst_core->segments.cs.base = vector << 12;
+
+	    PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
+		       vector, dst_core->segments.cs.selector, dst_core->cpu_id);
+	    // Maybe need to adjust the APIC?
+	    
+	    // We transition the target core to SIPI state
+	    dst_core->core_run_state = CORE_RUNNING;  // note: locking should not be needed here
+	    dst_apic->ipi_state = STARTED;
+
+	    // As with INIT, we should not need to do anything else
+
+	    PrintDebug(" SIPI delivery done\n");
+
+	    break;							
+	}
+	case 2: // SMI			
+	case 3: // reserved						
+	case 4: // NMI					
+	case 7: // ExtInt
+	default:
+	    PrintError("IPI %d delivery is unsupported\n", del_mode); 
+	    return -1;
+    }
+
+    return 0;
+
+}
+
+
+static int route_ipi(struct apic_dev_state * apic_dev,
+		     struct apic_state * src_apic, 
+		     struct int_cmd_reg * icr) {
+    struct apic_state * dest_apic = NULL;
+
+    PrintDebug("route_ipi: src_apic=%p, icr_data=%p\n", 
+	       src_apic, (void *)(addr_t)icr->val);
+
+
+    if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) { 
+	PrintError("route_ipi: Attempted send to unregistered apic id=%u\n", 
+		   icr->dst);
 	return -1;
     }
+
+    dest_apic =  &(apic_dev->apics[icr->dst]);
+
+
+    PrintDebug("route_ipi: IPI %s %u from apic %p to %s %s %u (icr=0x%llx)\n",
+	       deliverymode_str[icr->del_mode], 
+	       icr->vec, 
+	       src_apic, 	       
+	       (icr->dst_mode == 0) ? "(physical)" : "(logical)", 
+	       shorthand_str[icr->dst_shorthand], 
+	       icr->dst,
+	       icr->val);
+
+
+    switch (icr->dst_shorthand) {
+
+	case 0:  // no shorthand
+	    if (icr->dst_mode == 0) { 
+		// physical delivery
+
+		if (deliver_ipi(src_apic, dest_apic, 
+				icr->vec, icr->del_mode) == -1) {
+		    PrintError("Error: Could not deliver IPI\n");
+		    return -1;
+		}
+
+	    } else {
+		// logical delivery
+		int i;
+		uint8_t mda = icr->dst;
+
+		for (i = 0; i < apic_dev->num_apics; i++) { 
+		     dest_apic = &(apic_dev->apics[i]);
+		     int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
+		     
+		     if (del_flag == -1) {
+			 PrintError("Error checking delivery mode\n");
+			 return -1;
+		     } else if (del_flag == 1) {
+			if (deliver_ipi(src_apic, dest_apic, 
+					icr->vec, icr->del_mode) == -1) {
+			    PrintError("Error: Could not deliver IPI\n");
+			    return -1;
+			}
+		    }
+		}
+	    }
+	    
+	    break;
+	    
+	case 1:  // self
+
+	    if (src_apic == NULL) {
+		PrintError("Sending IPI to self from generic IPI sender\n");
+		break;
+	    }
+
+	    if (icr->dst_mode == 0) { 
+		if (deliver_ipi(src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
+		    PrintError("Could not deliver IPI\n");
+		    return -1;
+		}
+	    } else {
+		// logical delivery
+		PrintError("use of logical delivery in self is not yet supported.\n");
+		return -1;
+	    }
+	    break;
+	    
+	case 2: 
+	case 3: { // all and all-but-me
+	    // assuming that logical verus physical doesn't matter
+	    // although it is odd that both are used
+	    int i;
+
+	    for (i = 0; i < apic_dev->num_apics; i++) { 
+		dest_apic = &(apic_dev->apics[i]);
+
+		if ((dest_apic != src_apic) || (icr->dst_shorthand == 2)) { 
+		    if (deliver_ipi(src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
+			PrintError("Error: Could not deliver IPI\n");
+			return -1;
+		    }
+		}
+	    }	
+
+	    break;
+	}
+	default:
+	    PrintError("Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
+	    return -1;
+    }
+    
+
+    return 0;
 }
 
 
-static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
-    struct vm_device * dev = (struct vm_device *)priv_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
+
+static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
     addr_t reg_addr  = guest_addr - apic->base_addr;
     struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
     uint32_t val = 0;
 
 
-    PrintDebug("Read apic address space (%p)\n", 
-	       (void *)guest_addr);
+    PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
+	       apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
 
     if (msr->apic_enable == 0) {
-	PrintError("Write to APIC address space with disabled APIC\n");
+	PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
+		   apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
+
 	return -1;
     }
 
@@ -660,7 +1017,8 @@ static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_d
 	case SEOI_OFFSET:
 
 	default:
-	    PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
+	    PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n", 
+		       apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
 	    return -1;
     }
 
@@ -682,34 +1040,44 @@ static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_d
 	*val_ptr = val;
 
     } else {
-	PrintError("Invalid apic read length (%d)\n", length);
+	PrintError("apic %u: core %u: Invalid apic read length (%d)\n", 
+		   apic->lapic_id.val, core->cpu_id, length);
 	return -1;
     }
 
-    PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst);
+    PrintDebug("apic %u: core %u: Read finished (val=%x)\n", 
+	       apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
 
     return length;
 }
 
 
-static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data) {
-    struct vm_device * dev = (struct vm_device *)priv_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
+/**
+ *
+ */
+static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]); 
     addr_t reg_addr  = guest_addr - apic->base_addr;
     struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
     uint32_t op_val = *(uint32_t *)src;
 
-    PrintDebug("Write to apic address space (%p) (val=%x)\n", 
+    PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
+	       apic->lapic_id.val, core->cpu_id, apic, priv_data);
+
+    PrintDebug("Write to address space (%p) (val=%x)\n", 
 	       (void *)guest_addr, *(uint32_t *)src);
 
     if (msr->apic_enable == 0) {
-	PrintError("Write to APIC address space with disabled APIC\n");
+	PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
+		   apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
 	return -1;
     }
 
 
     if (length != 4) {
-	PrintError("Invalid apic write length (%d)\n", length);
+	PrintError("apic %u: core %u: Invalid apic write length (%d)\n", 
+		   apic->lapic_id.val, length, core->cpu_id);
 	return -1;
     }
 
@@ -743,22 +1111,26 @@ static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_
 	case TRIG_OFFSET7:
 	case PPR_OFFSET:
 	case EXT_APIC_FEATURE_OFFSET:
-#if 1
-	    PrintError("Attempting to write to read only register %p (ignored)\n", (void *)reg_addr);
-#else   
-	    PrintError("Attempting to write to read only register %p (error)\n", (void *)reg_addr);
-	    return -1;
-#endif
+
+	    PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n", 
+		       apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
+	    //  return -1;
+
 	    break;
 
 	    // Data registers
 	case APIC_ID_OFFSET:
+	    PrintDebug("apic %u: core %u: my id is being changed to %u\n", 
+		       apic->lapic_id.val, core->cpu_id, op_val);
+
 	    apic->lapic_id.val = op_val;
 	    break;
 	case TPR_OFFSET:
 	    apic->task_prio.val = op_val;
 	    break;
 	case LDR_OFFSET:
+	    PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
+		       apic->lapic_id.val, core->cpu_id, op_val);
 	    apic->log_dst.val = op_val;
 	    break;
 	case DFR_OFFSET:
@@ -848,22 +1220,34 @@ static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_
 
 	case INT_CMD_LO_OFFSET:
 	    apic->int_cmd.lo = op_val;
-	    V3_Call_On_CPU(apic->int_cmd.dst, apic_incoming_ipi, (void *)apic->int_cmd.val);
-    
+
+	    PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n", 
+		       apic->lapic_id.val, core->cpu_id,
+		       apic->int_cmd.val, apic->int_cmd.dst);
+
+	    if (route_ipi(apic_dev, apic, &(apic->int_cmd)) == -1) { 
+		PrintError("IPI Routing failure\n");
+		return -1;
+	    }
+
 	    break;
+
 	case INT_CMD_HI_OFFSET:
 	    apic->int_cmd.hi = op_val;
 	    break;
-	    // Unhandled Registers
 
+
+	// Unhandled Registers
 	case EXT_APIC_CMD_OFFSET:
 	case SEOI_OFFSET:
 	default:
-	    PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
+	    PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n", 
+		       apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
+
 	    return -1;
     }
 
-    PrintDebug("Write finished\n");
+    PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
 
     return length;
 }
@@ -873,12 +1257,14 @@ static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_
 /* Interrupt Controller Functions */
 
 // returns 1 if an interrupt is pending, 0 otherwise
-static int apic_intr_pending(struct guest_info * info, void * private_data) {
-    struct vm_device * dev = (struct vm_device *)private_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
+static int apic_intr_pending(struct guest_info * core, void * private_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]); 
     int req_irq = get_highest_irr(apic);
     int svc_irq = get_highest_isr(apic);
 
+    //    PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
+
     if ((req_irq >= 0) && 
 	(req_irq > svc_irq)) {
 	return 1;
@@ -887,9 +1273,9 @@ static int apic_intr_pending(struct guest_info * info, void * private_data) {
     return 0;
 }
 
-static int apic_get_intr_number(struct guest_info * info, void * private_data) {
-    struct vm_device * dev = (struct vm_device *)private_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
+static int apic_get_intr_number(struct guest_info * core, void * private_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]); 
     int req_irq = get_highest_irr(apic);
     int svc_irq = get_highest_isr(apic);
 
@@ -902,67 +1288,79 @@ static int apic_get_intr_number(struct guest_info * info, void * private_data) {
     return -1;
 }
 
-static int apic_raise_intr(struct guest_info * info, void * private_data, int irq) {
-#ifdef CONFIG_CRAY_XT
-    // The Seastar is connected directly to the LAPIC via LINT0 on the ICC bus
 
-    if (irq == 238) {
-	struct vm_device * dev = (struct vm_device *)private_data;
-	struct apic_state * apic = (struct apic_state *)dev->private_data;
+int v3_apic_send_ipi(struct v3_vm_info * vm, struct vm_device * dev, 
+		     struct v3_gen_ipi * ipi) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
+    struct int_cmd_reg tmp_icr;
 
-	return activate_apic_irq(apic, irq);
-    }
-#endif
+    // zero out all the fields
+    tmp_icr.val = 0;
 
-    return 0;
-}
 
-static int apic_lower_intr(struct guest_info * info, void * private_data, int irq) {
-    return 0;
+    tmp_icr.vec = ipi->vector;
+    tmp_icr.del_mode = ipi->mode;
+    tmp_icr.dst_mode = ipi->logical;
+    tmp_icr.trig_mode = ipi->trigger_mode;
+    tmp_icr.dst_shorthand = ipi->dst_shorthand;
+    tmp_icr.dst = ipi->dst;
+    
+
+    return route_ipi(apic_dev, NULL, &tmp_icr);
 }
 
-static int apic_begin_irq(struct guest_info * info, void * private_data, int irq) {
-    struct vm_device * dev = (struct vm_device *)private_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
-    int major_offset = (irq & ~0x00000007) >> 3;
-    int minor_offset = irq & 0x00000007;
-    uchar_t * req_location = apic->int_req_reg + major_offset;
-    uchar_t * svc_location = apic->int_svc_reg + major_offset;
-    uchar_t flag = 0x01 << minor_offset;
 
-    *svc_location |= flag;
-    *req_location &= ~flag;
+int v3_apic_raise_intr(struct v3_vm_info * vm, struct vm_device * dev, 
+		       uint32_t irq, uint32_t dst) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
+    struct apic_state * apic = &(apic_dev->apics[dst]); 
 
-#ifdef CONFIG_CRAY_XT
-    if ((irq == 238) || (irq == 239)) {
-	PrintError("APIC: Begin IRQ %d (ISR=%x), (IRR=%x)\n", irq, *svc_location, *req_location);
+    PrintDebug("apic %u core ?: raising interrupt IRQ %u (dst = %u).\n", apic->lapic_id.val, irq, dst); 
+
+    activate_apic_irq(apic, irq);
+
+    if (V3_Get_CPU() != dst) {
+	v3_interrupt_cpu(vm, dst, 0);
     }
-#endif
 
     return 0;
 }
 
 
 
-int v3_apic_raise_intr(struct guest_info * info, struct vm_device * apic_dev, int intr_num) {
-    struct apic_state * apic = (struct apic_state *)apic_dev->private_data;
-
-    if (activate_apic_irq(apic, intr_num) == -1) {
-	PrintError("Error: Could not activate apic_irq\n");
-	return -1;
-    } 
+static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]); 
+    int major_offset = (irq & ~0x00000007) >> 3;
+    int minor_offset = irq & 0x00000007;
+    uint8_t * req_location = apic->int_req_reg + major_offset;
+    uint8_t * svc_location = apic->int_svc_reg + major_offset;
+    uint8_t flag = 0x01 << minor_offset;
 
-    v3_interrupt_cpu(info, 0);
+    if (*req_location & flag) {
+	// we will only pay attention to a begin irq if we
+	// know that we initiated it!
+	*svc_location |= flag;
+	*req_location &= ~flag;
+    } else {
+	// do nothing... 
+	//PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
+	//	   apic->lapic_id.val, core->cpu_id, irq);
+    }
 
     return 0;
 }
 
 
 
+
 /* Timer Functions */
-static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
-    struct vm_device * dev = (struct vm_device *)priv_data;
-    struct apic_state * apic = (struct apic_state *)dev->private_data;
+static void apic_update_time(struct guest_info * core, 
+			     uint64_t cpu_cycles, uint64_t cpu_freq, 
+			     void * priv_data) {
+    struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
+    struct apic_state * apic = &(apic_dev->apics[core->cpu_id]); 
+
     // The 32 bit GCC runtime is a pile of shit
 #ifdef __V3_64BIT__
     uint64_t tmr_ticks = 0;
@@ -970,7 +1368,7 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo
     uint32_t tmr_ticks = 0;
 #endif
 
-    uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
+    uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
     uint_t shift_num = 0;
 
 
@@ -980,7 +1378,7 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo
     if ((apic->tmr_init_cnt == 0) || 
 	( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
 	  (apic->tmr_cur_cnt == 0))) {
-	//PrintDebug("APIC timer not yet initialized\n");
+	//PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
 	return;
     }
 
@@ -1011,7 +1409,8 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo
 	    shift_num = 7;
 	    break;
 	default:
-	    PrintError("Invalid Timer Divider configuration\n");
+	    PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
+		       apic->lapic_id.val, core->cpu_id);
 	    return;
     }
 
@@ -1025,15 +1424,19 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo
 	apic->tmr_cur_cnt = 0;
 
 	// raise irq
-	PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n", 
+	PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
+		   apic->lapic_id.val, core->cpu_id,
 		   apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
 
-	if (apic_intr_pending(info, priv_data)) {
-	    PrintDebug("Overriding pending IRQ %d\n", apic_get_intr_number(dev->vm, priv_data));
+	if (apic_intr_pending(core, priv_data)) {
+	    PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n", 
+		       apic->lapic_id.val, core->cpu_id, 
+		       apic_get_intr_number(core, priv_data));
 	}
 
 	if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
-	    PrintError("Could not raise Timer interrupt\n");
+	    PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
+		       apic->lapic_id.val, core->cpu_id);
 	}
     
 	if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
@@ -1045,68 +1448,25 @@ static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullo
 
 }
 
-static void apic_incoming_ipi(void *val)
-{
-PrintError("In apic_incoming_ipi, val=%p\n", val);
-	struct int_cmd_reg int_cmd;
-	char *type = NULL, *dest;
-	char foo[8];
-	int_cmd.val = (uint64_t)val;
-	switch (int_cmd.dst_shorthand)
-	{
-	case 0x0:
-		sprintf(foo, "%d", int_cmd.dst);
-		dest = foo;
-		break;
-	case 0x1:
-		dest = "(self)";
-		break;
-	case 0x2:
-		dest = "(broadcast inclusive)";
-		break;
-	case 0x3:
-		dest = "(broadcast)";
-		break;
-	}
-	switch (int_cmd.msg_type) 
-	{
-	case 0x0:
-		type = "";
-		break;
-	case 0x4:
-		type = "(NMI)";
-		break;
-	case 0x5:
-		type = "(INIT)";
-		break;
-	case 0x6:
-		type = "(Startup)";
-		break;
-	}
-	PrintError("Receieved IPI on CPU %d type=%s dest=%s\n",
-			V3_Get_CPU(), type, dest);
-//%p %s to CPU %d on CPU %d.\n", val, foo, type, dest, (int)V3_Get_CPU());
-	return;
-}
-
 
 static struct intr_ctrl_ops intr_ops = {
     .intr_pending = apic_intr_pending,
     .get_intr_number = apic_get_intr_number,
-    .raise_intr = apic_raise_intr,
     .begin_irq = apic_begin_irq,
-    .lower_intr = apic_lower_intr, 
 };
 
 
 static struct vm_timer_ops timer_ops = {
-    .update_time = apic_update_time,
+    .update_timer = apic_update_time,
 };
 
 
 
 
 static int apic_free(struct vm_device * dev) {
+
+    /* TODO: This should crosscall to force an unhook on each CPU */
+
     //   struct apic_state * apic = (struct apic_state *)dev->private_data;
 
     v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
@@ -1124,27 +1484,57 @@ static struct v3_device_ops dev_ops = {
 
 
 
+
+
 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
-    PrintDebug("Creating APIC\n");
-    char * name = v3_cfg_val(cfg, "name");
+    char * dev_id = v3_cfg_val(cfg, "ID");
+    struct apic_dev_state * apic_dev = NULL;
+    int i = 0;
+
+    PrintDebug("apic: creating an APIC for each core\n");
 
-    struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state));
+    apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) + 
+						  sizeof(struct apic_state) * vm->num_cores);
 
-    struct vm_device * dev = v3_allocate_device(name, &dev_ops, apic);
+    apic_dev->num_apics = vm->num_cores;
+
+    struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, apic_dev);
 
     if (v3_attach_device(vm, dev) == -1) {
-	PrintError("Could not attach device %s\n", name);
+	PrintError("apic: Could not attach device %s\n", dev_id);
 	return -1;
     }
 
-    v3_register_intr_controller(vm, &intr_ops, dev);
-    v3_add_timer(vm, &timer_ops, dev);
+    
+    for (i = 0; i < vm->num_cores; i++) {
+	struct apic_state * apic = &(apic_dev->apics[i]);
+	struct guest_info * core = &(vm->cores[i]);
+
+	apic->core = core;
+
+	init_apic_state(apic, i);
+
+    	v3_register_intr_controller(core, &intr_ops, apic_dev);
+
+    	v3_add_timer(core, &timer_ops, apic_dev);
+
+	v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
+
+	PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
+    }
+
+#ifdef CONFIG_DEBUG_APIC
+    for (i = 0; i < vm->num_cores; i++) {
+	struct apic_state * apic = &(apic_dev->apics[i]);
+	PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n",
+		   i, apic, apic->lapic_id.val, apic->base_addr_msr.value);
+    }
+#endif
 
-    init_apic_state(apic);
 
-    v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
+    PrintDebug("apic: priv_data is at %p\n", apic_dev);
 
-    v3_hook_full_mem(vm, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev);
+    v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
 
     return 0;
 }