X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fapic.c;h=7424b55bf496057255a82b10c2a993a4ad4ab9df;hb=83d70dd81c80079c767cc99b0f7349d58b8b44e4;hp=cb588233fd784a6153c52b2fa343a01b9de82a1b;hpb=4bc3ee757b44d3e466fd89e348106c47fa5511ee;p=palacios.git diff --git a/palacios/src/devices/apic.c b/palacios/src/devices/apic.c index cb58823..7424b55 100644 --- a/palacios/src/devices/apic.c +++ b/palacios/src/devices/apic.c @@ -277,7 +277,7 @@ static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) { -static int apic_do_eoi(struct apic_state * apic) { +static int get_highest_isr(struct apic_state * apic) { int i = 0, j = 0; // We iterate backwards to find the highest priority @@ -288,13 +288,72 @@ static int apic_do_eoi(struct apic_state * apic) { for (j = 7; j >= 0; j--) { uchar_t flag = 0x1 << j; if ((*svc_major) & flag) { - *svc_major &= ~flag; - return 0; + + + return ((i * 8) + j); + } + } + } + } + + return -1; +} + + + +static int get_highest_irr(struct apic_state * apic) { + int i = 0, j = 0; + + // We iterate backwards to find the highest priority + for (i = 31; i >= 0; i--) { + uchar_t * req_major = apic->int_req_reg + i; + + if ((*req_major) & 0xff) { + for (j = 7; j >= 0; j--) { + uchar_t flag = 0x1 << j; + if ((*req_major) & flag) { + + + return ((i * 8) + j); } } } } + return -1; +} + + + + +static int apic_do_eoi(struct apic_state * apic) { + int isr_irq = get_highest_isr(apic); + + if (isr_irq != -1) { + int major_offset = (isr_irq & ~0x00000007) >> 3; + int minor_offset = isr_irq & 0x00000007; + uchar_t flag = 0x1 << minor_offset; + uchar_t * svc_location = apic->int_svc_reg + major_offset; + + PrintDebug("Received APIC EOI\n"); + + *svc_location &= ~flag; + +#ifdef CRAY_XT + + if ((isr_irq == 238) || + (isr_irq == 239)) { + PrintError("Acking IRQ %d\n", isr_irq); + } + + if (isr_irq == 238) { + V3_ACK_IRQ(238); + } +#endif + } else { + PrintError("Spurious EOI...\n"); + } + return 0; } @@ -739,14 +798,13 @@ static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_ // Action Registers + case EOI_OFFSET: + // do eoi + apic_do_eoi(apic); + break; + case INT_CMD_LO_OFFSET: case INT_CMD_HI_OFFSET: - case EOI_OFFSET: - { - // do eoi - apic_do_eoi(apic); - break; - } // Unhandled Registers case EXT_INT_LOC_VEC_TBL_OFFSET0: case EXT_INT_LOC_VEC_TBL_OFFSET1: @@ -768,45 +826,47 @@ static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_ /* Interrupt Controller Functions */ +// returns 1 if an interrupt is pending, 0 otherwise static int apic_intr_pending(void * private_data) { struct vm_device * dev = (struct vm_device *)private_data; struct apic_state * apic = (struct apic_state *)dev->private_data; - int i = 0; - + int req_irq = get_highest_irr(apic); + int svc_irq = get_highest_isr(apic); - // just scan the request register looking for any set bit - // we should probably just do this with uint64 casts - for (i = 0; i < 32; i++) { - if (apic->int_req_reg[i] & 0xff) { - return 1; - } + if ((req_irq >= 0) && + (req_irq > svc_irq)) { + return 1; } + return 0; } static int apic_get_intr_number(void * private_data) { struct vm_device * dev = (struct vm_device *)private_data; struct apic_state * apic = (struct apic_state *)dev->private_data; - int i = 0, j = 0; - + int req_irq = get_highest_irr(apic); + int svc_irq = get_highest_isr(apic); - // We iterate backwards to find the highest priority - for (i = 31; i >= 0; i--) { - uchar_t req_major = apic->int_req_reg[i]; - - if (req_major & 0xff) { - for (j = 7; j >= 0; j--) { - if ((req_major >> j) == 0x1) { - return (i * 8) + j; - } - } - } + if (svc_irq == -1) { + return req_irq; + } else if (svc_irq < req_irq) { + return req_irq; } return -1; } static int apic_raise_intr(void * private_data, int irq) { +#ifdef CRAY_XT + // The Seastar is connected directly to the LAPIC via LINT0 on the ICC bus + + if (irq == 238) { + struct vm_device * dev = (struct vm_device *)private_data; + struct apic_state * apic = (struct apic_state *)dev->private_data; + + return activate_apic_irq(apic, irq); + } +#endif return 0; } @@ -826,6 +886,12 @@ static int apic_begin_irq(void * private_data, int irq) { *svc_location |= flag; *req_location &= ~flag; +#ifdef CRAY_XT + if ((irq == 238) || (irq == 239)) { + PrintError("APIC: Begin IRQ %d (ISR=%x), (IRR=%x)\n", irq, *svc_location, *req_location); + } +#endif + return 0; } @@ -895,7 +961,7 @@ static void apic_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priv } tmr_ticks = cpu_cycles >> shift_num; - // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks); + PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks); if (tmr_ticks < apic->tmr_cur_cnt) { apic->tmr_cur_cnt -= tmr_ticks; @@ -906,6 +972,7 @@ static void apic_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priv // raise irq PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n", apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num); + if (activate_internal_irq(apic, APIC_TMR_INT) == -1) { PrintError("Could not raise Timer interrupt\n"); }