X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2Fapic.c;h=6b21f81ae48193d026c5cd0d96f9f7b1c03f098f;hb=504a6fd3bf01d7299ec69f80d5117dea3014ea28;hp=b2b7969cb94778d23ff73c3a43573f569c57c830;hpb=ad78e7627af59b2ebbfebdd05b479a021174efe4;p=palacios-OLD.git

diff --git a/palacios/src/devices/apic.c b/palacios/src/devices/apic.c
index b2b7969..6b21f81 100644
--- a/palacios/src/devices/apic.c
+++ b/palacios/src/devices/apic.c
@@ -1215,7 +1215,7 @@ static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, ui
 	*val_ptr = *(((uint8_t *)&val) + byte_addr);
 
     } else if ((length == 2) && 
-	       ((reg_addr & 0x3) == 0x3)) {
+	       ((reg_addr & 0x3) != 0x3)) {
 	uint_t byte_addr = reg_addr & 0x3;
 	uint16_t * val_ptr = (uint16_t *)dst;
 	*val_ptr = *(((uint16_t *)&val) + byte_addr);
@@ -1357,6 +1357,8 @@ static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, u
 	    apic->tmr_cur_cnt = op_val;
 	    break;
 	case TMR_DIV_CFG_OFFSET:
+	    PrintDebug("apic %u: core %u: setting tmr_div_cfg to 0x%x\n",
+		       apic->lapic_id.val, core->vcpu_id, op_val);
 	    apic->tmr_div_cfg.val = op_val;
 	    break;
 
@@ -1650,6 +1652,19 @@ static void apic_update_time(struct guest_info * core,
 	}
     
 	if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
+	    static unsigned int nexits = 0;
+	    static unsigned int missed_ints = 0;
+
+	    nexits++;
+	    missed_ints += tmr_ticks / apic->tmr_init_cnt;
+
+	    if ((missed_ints > 0) && (nexits >= 5000)) {
+	        V3_Print("apic %u: core %u: missed %u timer interrupts total in last %u exits.\n",
+		         apic->lapic_id.val, core->vcpu_id, missed_ints, nexits); 
+		missed_ints = 0;
+		nexits = 0;
+	    }
+
 	    tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
 	    apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
 	}
@@ -1699,9 +1714,109 @@ static int apic_free(struct apic_dev_state * apic_dev) {
     return 0;
 }
 
+#ifdef V3_CONFIG_CHECKPOINT
+static int apic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
+    struct apic_dev_state * apic_state = (struct apic_dev_state *)private_data;
+    int i = 0;
+
+    V3_CHKPT_STD_SAVE(ctx, apic_state->num_apics);
+
+    //V3_CHKPT_STD_SAVE(ctx,apic_state->state_lock);
+    for (i = 0; i < apic_state->num_apics; i++) {
+
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].base_addr);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].base_addr_msr);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].lapic_id);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].apic_ver);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ext_apic_ctrl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].local_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_div_cfg);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].lint0_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].lint1_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].perf_ctr_loc_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].therm_loc_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].err_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].err_status);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].spurious_int);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_cmd);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].log_dst);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].dst_fmt);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].arb_prio);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].task_prio);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].proc_prio);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ext_apic_feature);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].spec_eoi);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_cur_cnt);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].tmr_init_cnt);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ext_intr_vec_tbl);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].rem_rd_data);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].ipi_state);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_req_reg);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_svc_reg);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].int_en_reg);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].trig_mode_reg);
+	V3_CHKPT_STD_SAVE(ctx, apic_state->apics[i].eoi);
+
+    }
+
+    return 0;
+}
+
+static int apic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
+    struct apic_dev_state *apic_state = (struct apic_dev_state *)private_data;
+    int i = 0;
+
+    V3_CHKPT_STD_LOAD(ctx,apic_state->num_apics);
+
+    for (i = 0; i < apic_state->num_apics; i++) {
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].base_addr);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].base_addr_msr);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].lapic_id);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].apic_ver);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ext_apic_ctrl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].local_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_div_cfg);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].lint0_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].lint1_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].perf_ctr_loc_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].therm_loc_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].err_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].err_status);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].spurious_int);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_cmd);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].log_dst);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].dst_fmt);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].arb_prio);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].task_prio);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].proc_prio);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ext_apic_feature);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].spec_eoi);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_cur_cnt);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].tmr_init_cnt);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ext_intr_vec_tbl);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].rem_rd_data);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].ipi_state);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_req_reg);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_svc_reg);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].int_en_reg);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].trig_mode_reg);
+	V3_CHKPT_STD_LOAD(ctx, apic_state->apics[i].eoi);
+    }
+
+
+    return 0;
+}
+
+#endif
 
 static struct v3_device_ops dev_ops = {
     .free = (int (*)(void *))apic_free,
+#ifdef V3_CONFIG_CHECKPOINT
+    .save = apic_save,
+    .load = apic_load
+#endif
 };