X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8259a.c;h=bf3a1390457eea09a3a9a6dc04ef28a9df331000;hb=2377d33e71ba625a547b414916949181db2a49da;hp=9bbef1e4ce4689dee24b94fe1af1e8b5c648ee39;hpb=72420d58d18ec71d4777d029daaf0c6a1c820b32;p=palacios.git diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c index 9bbef1e..bf3a139 100644 --- a/palacios/src/devices/8259a.c +++ b/palacios/src/devices/8259a.c @@ -23,8 +23,9 @@ #include #include #include +#include -#ifndef CONFIG_DEBUG_PIC +#ifndef V3_CONFIG_DEBUG_PIC #undef PrintDebug #define PrintDebug(fmt, args...) #endif @@ -123,113 +124,133 @@ struct ocw3 { struct pic_internal { - uchar_t master_irr; - uchar_t slave_irr; + uint8_t master_irr; + uint8_t slave_irr; - uchar_t master_isr; - uchar_t slave_isr; + uint8_t master_isr; + uint8_t slave_isr; - uchar_t master_elcr; - uchar_t slave_elcr; - uchar_t master_elcr_mask; - uchar_t slave_elcr_mask; + uint8_t master_elcr; + uint8_t slave_elcr; + uint8_t master_elcr_mask; + uint8_t slave_elcr_mask; - uchar_t master_icw1; - uchar_t master_icw2; - uchar_t master_icw3; - uchar_t master_icw4; + uint8_t master_icw1; + uint8_t master_icw2; + uint8_t master_icw3; + uint8_t master_icw4; - uchar_t slave_icw1; - uchar_t slave_icw2; - uchar_t slave_icw3; - uchar_t slave_icw4; + uint8_t slave_icw1; + uint8_t slave_icw2; + uint8_t slave_icw3; + uint8_t slave_icw4; - uchar_t master_imr; - uchar_t slave_imr; - uchar_t master_ocw2; - uchar_t master_ocw3; - uchar_t slave_ocw2; - uchar_t slave_ocw3; + uint8_t master_imr; + uint8_t slave_imr; + uint8_t master_ocw2; + uint8_t master_ocw3; + uint8_t slave_ocw2; + uint8_t slave_ocw3; pic_state_t master_state; pic_state_t slave_state; + + struct guest_info * core; + + struct { + int (*ack)(struct guest_info * core, uint32_t irq, void * private_data); + void * private_data; + } irq_ack_cbs[15]; + + + void * router_handle; + void * controller_handle; }; static void DumpPICState(struct pic_internal *p) { - PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state); - PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr); - PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr); - PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_state=0x%x\n",p->master_state); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_irr=0x%x\n",p->master_irr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_isr=0x%x\n",p->master_isr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_imr=0x%x\n",p->master_imr); - PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2); - PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_ocw2=0x%x\n",p->master_ocw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_ocw3=0x%x\n",p->master_ocw3); - PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1); - PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2); - PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3); - PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw1=0x%x\n",p->master_icw1); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw2=0x%x\n",p->master_icw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw3=0x%x\n",p->master_icw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw4=0x%x\n",p->master_icw4); - PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state); - PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr); - PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr); - PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_state=0x%x\n",p->slave_state); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_irr=0x%x\n",p->slave_irr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_isr=0x%x\n",p->slave_isr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_imr=0x%x\n",p->slave_imr); - PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2); - PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3); - PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1); - PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2); - PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3); - PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw1=0x%x\n",p->slave_icw1); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw2=0x%x\n",p->slave_icw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw3=0x%x\n",p->slave_icw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw4=0x%x\n",p->slave_icw4); } -static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, int irq) { +static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) { struct pic_internal * state = (struct pic_internal*)private_data; + uint8_t irq_num = irq->irq; - if (irq == 2) { - irq = 9; - state->master_irr |= 0x04; // PAD + if (irq_num == 2) { + irq_num = 9; + state->master_irr |= 0x04; } - PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq); + PrintDebug(vm, VCORE_NONE, "8259 PIC: Raising irq %d in the PIC\n", irq_num); - if (irq <= 7) { - state->master_irr |= 0x01 << irq; - } else if ((irq > 7) && (irq < 16)) { - state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq + if (irq_num <= 7) { + state->master_irr |= 0x01 << irq_num; + } else if ((irq_num > 7) && (irq_num < 16)) { + state->slave_irr |= 0x01 << (irq_num - 8); } else { - PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq); + PrintDebug(vm, VCORE_NONE, "8259 PIC: Invalid IRQ raised (%d)\n", irq_num); return -1; } - v3_interrupt_cpu(vm, 0, 0); + state->irq_ack_cbs[irq_num].ack = irq->ack; + state->irq_ack_cbs[irq_num].private_data = irq->private_data; + + if (V3_Get_CPU() != vm->cores[0].pcpu_id) { + // guest is running on another core, interrupt it to deliver irq + v3_interrupt_cpu(vm, 0, 0); + } return 0; } -static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, int irq) { +static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) { struct pic_internal * state = (struct pic_internal*)private_data; + uint8_t irq_num = irq->irq; - PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq); - if (irq <= 7) { - state->master_irr &= ~(1 << irq); + PrintDebug(vm, VCORE_NONE, "[pic_lower_intr] IRQ line %d now low\n", irq_num); + if (irq_num <= 7) { + + state->master_irr &= ~(1 << irq_num); if ((state->master_irr & ~(state->master_imr)) == 0) { - PrintDebug("\t\tFIXME: Master maybe should do sth\n"); + PrintDebug(vm, VCORE_NONE, "\t\tFIXME: Master maybe should do sth\n"); } - } else if ((irq > 7) && (irq < 16)) { + } else if ((irq_num > 7) && (irq_num < 16)) { - state->slave_irr &= ~(1 << (irq - 8)); + state->slave_irr &= ~(1 << (irq_num - 8)); if ((state->slave_irr & (~(state->slave_imr))) == 0) { - PrintDebug("\t\tFIXME: Slave maybe should do sth\n"); + PrintDebug(vm, VCORE_NONE, "\t\tFIXME: Slave maybe should do sth\n"); } } return 0; @@ -253,8 +274,8 @@ static int pic_get_intr_number(struct guest_info * info, void * private_data) { int i = 0; int irq = -1; - PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr); - PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr); + PrintDebug(info->vm_info, info, "8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr); + PrintDebug(info->vm_info, info, "8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr); for (i = 0; i < 16; i++) { if (i <= 7) { @@ -262,7 +283,7 @@ static int pic_get_intr_number(struct guest_info * info, void * private_data) { //state->master_isr |= (0x1 << i); // reset the irr //state->master_irr &= ~(0x1 << i); - PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2); + PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2); irq = i + state->master_icw2; break; } @@ -270,7 +291,7 @@ static int pic_get_intr_number(struct guest_info * info, void * private_data) { if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) { //state->slave_isr |= (0x1 << (i - 8)); //state->slave_irr &= ~(0x1 << (i - 8)); - PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2); + PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2); irq = (i - 8) + state->slave_icw2; break; } @@ -286,7 +307,7 @@ static int pic_get_intr_number(struct guest_info * info, void * private_data) { if (i == 16) { return -1; } else { - PrintDebug("8259 PIC: get num is returning %d\n",irq); + PrintDebug(info->vm_info, info, "8259 PIC: get num is returning %d\n",irq); return irq; } } @@ -303,7 +324,7 @@ static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) irq &= 0x7; irq += 8; } else { - // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq); + // PrintError(info->vm_info, info, "8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq); return -1; } @@ -316,7 +337,7 @@ static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) state->master_irr &= ~(0x1 << irq); } } else { - PrintDebug("8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n",irq); + PrintDebug(info->vm_info, info, "8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n", irq); } } else { @@ -328,11 +349,12 @@ static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) state->slave_irr &= ~(0x1 << (irq - 8)); } } else { - PrintDebug("8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n",irq); + PrintDebug(info->vm_info, info, "8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n", irq); } - } + + return 0; } @@ -361,16 +383,16 @@ static int read_master_port1(struct guest_info * core, ushort_t port, void * dst struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Master1)\n"); return -1; } if ((state->master_ocw3 & 0x03) == 0x02) { - *(uchar_t *)dst = state->master_irr; + *(uint8_t *)dst = state->master_irr; } else if ((state->master_ocw3 & 0x03) == 0x03) { - *(uchar_t *)dst = state->master_isr; + *(uint8_t *)dst = state->master_isr; } else { - *(uchar_t *)dst = 0; + *(uint8_t *)dst = 0; } return 1; @@ -380,11 +402,11 @@ static int read_master_port2(struct guest_info * core, ushort_t port, void * dst struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Master2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Master2)\n"); return -1; } - *(uchar_t *)dst = state->master_imr; + *(uint8_t *)dst = state->master_imr; return 1; @@ -394,16 +416,16 @@ static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Slave1)\n"); return -1; } if ((state->slave_ocw3 & 0x03) == 0x02) { - *(uchar_t*)dst = state->slave_irr; + *(uint8_t*)dst = state->slave_irr; } else if ((state->slave_ocw3 & 0x03) == 0x03) { - *(uchar_t *)dst = state->slave_isr; + *(uint8_t *)dst = state->slave_isr; } else { - *(uchar_t *)dst = 0; + *(uint8_t *)dst = 0; } return 1; @@ -413,11 +435,11 @@ static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Slave2)\n"); return -1; } - *(uchar_t *)dst = state->slave_imr; + *(uint8_t *)dst = state->slave_imr; return 1; } @@ -425,12 +447,12 @@ static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { struct pic_internal * state = (struct pic_internal *)priv_data; - uchar_t cw = *(uchar_t *)src; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write master port 1 with 0x%x\n",cw); if (length != 1) { - PrintError("8259 PIC: Invalid Write length (wr_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Write length (wr_Master1)\n"); return -1; } @@ -438,7 +460,7 @@ static int write_master_port1(struct guest_info * core, ushort_t port, void * sr if (IS_ICW1(cw)) { - PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw); state->master_icw1 = cw; state->master_state = ICW2; @@ -448,43 +470,59 @@ static int write_master_port1(struct guest_info * core, ushort_t port, void * sr // handle the EOI here struct ocw2 * cw2 = (struct ocw2*)&cw; - PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw); if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { // specific EOI; state->master_isr &= ~(0x01 << cw2->level); + + + /* + // ack the irq if requested + if (state->irq_ack_cbs[irq].ack) { + state->irq_ack_cbs[irq].ack(info, irq, state->irq_ack_cbs[irq].private_data); + } + */ + } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { int i; // Non-specific EOI - PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr); + PrintDebug(core->vm_info, core, "8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr); for (i = 0; i < 8; i++) { if (state->master_isr & (0x01 << i)) { state->master_isr &= ~(0x01 << i); break; } - } - PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr); + } + PrintDebug(core->vm_info, core, "8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr); } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) { - PrintDebug("8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level); + PrintDebug(core->vm_info, core, "8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level); } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) { - PrintDebug("8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level); + PrintDebug(core->vm_info, core, "8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level); } else { - PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Command not handled, or in error (wr_Master1)\n"); return -1; } + if (cw2->EOI) { + if (pic_get_intr_number(core, state) != -1) { + PrintError(core->vm_info, core, "Interrupt pending after EOI\n"); + } + } + + state->master_ocw2 = cw; } else if (IS_OCW3(cw)) { - PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw); state->master_ocw3 = cw; } else { - PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n"); - PrintError("8259 PIC: CW=%x\n", cw); + PrintError(core->vm_info, core, "8259 PIC: Invalid OCW to PIC (wr_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: CW=%x\n", cw); return -1; } } else { - PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n"); - PrintError("8259 PIC: CW=%x\n", cw); + PrintError(core->vm_info, core, "8259 PIC: Invalid PIC State (wr_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: CW=%x\n", cw); return -1; } @@ -493,12 +531,12 @@ static int write_master_port1(struct guest_info * core, ushort_t port, void * sr static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { struct pic_internal * state = (struct pic_internal *)priv_data; - uchar_t cw = *(uchar_t *)src; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write master port 2 with 0x%x\n",cw); if (length != 1) { - PrintError("8259 PIC: Invalid Write length (wr_Master2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Write length (wr_Master2)\n"); return -1; } @@ -507,7 +545,7 @@ static int write_master_port2(struct guest_info * core, ushort_t port, void * sr if (state->master_state == ICW2) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw); state->master_icw2 = cw; @@ -525,7 +563,7 @@ static int write_master_port2(struct guest_info * core, ushort_t port, void * sr } else if (state->master_state == ICW3) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw); state->master_icw3 = cw; @@ -536,15 +574,15 @@ static int write_master_port2(struct guest_info * core, ushort_t port, void * sr } } else if (state->master_state == ICW4) { - PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw); state->master_icw4 = cw; state->master_state = READY; } else if ((state->master_state == ICW1) || (state->master_state == READY)) { - PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting IMR = %x (wr_Master2)\n", cw); state->master_imr = cw; } else { // error - PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n", + PrintError(core->vm_info, core, "8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n", state->master_state); return -1; } @@ -554,20 +592,20 @@ static int write_master_port2(struct guest_info * core, ushort_t port, void * sr static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { struct pic_internal * state = (struct pic_internal *)priv_data; - uchar_t cw = *(uchar_t *)src; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write slave port 1 with 0x%x\n",cw); if (length != 1) { // error - PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Write length (wr_Slave1)\n"); return -1; } v3_clear_pending_intr(core); if (IS_ICW1(cw)) { - PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw); state->slave_icw1 = cw; state->slave_state = ICW2; } else if (state->slave_state == READY) { @@ -575,7 +613,7 @@ static int write_slave_port1(struct guest_info * core, ushort_t port, void * src // handle the EOI here struct ocw2 * cw2 = (struct ocw2 *)&cw; - PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw); if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { // specific EOI; @@ -583,30 +621,38 @@ static int write_slave_port1(struct guest_info * core, ushort_t port, void * src } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { int i; // Non-specific EOI - PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr); + PrintDebug(core->vm_info, core, "8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr); for (i = 0; i < 8; i++) { if (state->slave_isr & (0x01 << i)) { state->slave_isr &= ~(0x01 << i); break; } } - PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr); + PrintDebug(core->vm_info, core, "8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr); } else { - PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Command not handled or invalid (wr_Slave1)\n"); return -1; } + if (cw2->EOI) { + if (pic_get_intr_number(core, state) != -1) { + PrintError(core->vm_info, core, "Interrupt pending after EOI\n"); + } + } + + + state->slave_ocw2 = cw; } else if (IS_OCW3(cw)) { // Basically sets the IRR/ISR read flag - PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw); state->slave_ocw3 = cw; } else { - PrintError("8259 PIC: Invalid command work (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid command work (wr_Slave1)\n"); return -1; } } else { - PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid State writing (wr_Slave1)\n"); return -1; } @@ -615,12 +661,12 @@ static int write_slave_port1(struct guest_info * core, ushort_t port, void * src static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { struct pic_internal * state = (struct pic_internal *)priv_data; - uchar_t cw = *(uchar_t *)src; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write slave port 2 with 0x%x\n",cw); if (length != 1) { - PrintError("8259 PIC: Invalid write length (wr_Slave2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid write length (wr_Slave2)\n"); return -1; } @@ -630,7 +676,7 @@ static int write_slave_port2(struct guest_info * core, ushort_t port, void * src if (state->slave_state == ICW2) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw); state->slave_icw2 = cw; @@ -645,7 +691,7 @@ static int write_slave_port2(struct guest_info * core, ushort_t port, void * src } else if (state->slave_state == ICW3) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw); state->slave_icw3 = cw; @@ -656,14 +702,14 @@ static int write_slave_port2(struct guest_info * core, ushort_t port, void * src } } else if (state->slave_state == ICW4) { - PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw); state->slave_icw4 = cw; state->slave_state = READY; } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) { - PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw); state->slave_imr = cw; } else { - PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid State at write (wr_Slave2)\n"); return -1; } @@ -677,7 +723,7 @@ static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, u struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("ELCR read of invalid length %d\n", length); + PrintError(core->vm_info, core, "ELCR read of invalid length %d\n", length); return -1; } @@ -687,7 +733,7 @@ static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, u } else if (port == ELCR2_PORT) { *(uint8_t *)dst = state->slave_elcr; } else { - PrintError("Invalid port %x\n", port); + PrintError(core->vm_info, core, "Invalid port %x\n", port); return -1; } @@ -699,7 +745,7 @@ static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("ELCR read of invalid length %d\n", length); + PrintError(core->vm_info, core, "ELCR read of invalid length %d\n", length); return -1; } @@ -709,7 +755,7 @@ static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, } else if (port == ELCR2_PORT) { state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask; } else { - PrintError("Invalid port %x\n", port); + PrintError(core->vm_info, core, "Invalid port %x\n", port); return -1; } @@ -718,28 +764,120 @@ static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, +static int pic_free(struct pic_internal * state) { + struct guest_info * core = state->core; + + v3_remove_intr_controller(core, state->controller_handle); + v3_remove_intr_router(core->vm_info, state->router_handle); + + V3_Free(state); + return 0; +} + +#ifdef V3_CONFIG_CHECKPOINT +static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) { + struct pic_internal * pic = (struct pic_internal *)private_data; + + V3_CHKPT_SAVE(ctx, "MASTER_IRR", pic->master_irr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_IRR", pic->slave_irr, savefailout); + + V3_CHKPT_SAVE(ctx, "MASTER_ISR", pic->master_isr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ISR", pic->slave_isr, savefailout); + + V3_CHKPT_SAVE(ctx, "MASTER_ELCR", pic->master_elcr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ELCR", pic->slave_elcr, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ELCR_MASK", pic->master_elcr_mask, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ELCR_MASK", pic->slave_elcr_mask, savefailout); + + V3_CHKPT_SAVE(ctx, "MASTER_ICW1", pic->master_icw1, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ICW2", pic->master_icw2, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ICW3", pic->master_icw3, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ICW4", pic->master_icw4, savefailout); + + V3_CHKPT_SAVE(ctx, "SLAVE_ICW1", pic->slave_icw1, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ICW2", pic->slave_icw2, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ICW3", pic->slave_icw3, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ICW4", pic->slave_icw4, savefailout); -static int pic_free(struct vm_device * dev) { + V3_CHKPT_SAVE(ctx, "MASTER_IMR", pic->master_imr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_IMR", pic->slave_imr, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_OCW2", pic->master_ocw2, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_OCW3", pic->master_ocw3, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_OCW2", pic->slave_ocw2, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_OCW3", pic->slave_ocw3, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_STATE", pic->master_state, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_STATE", pic->slave_state, savefailout); + + return 0; + + savefailout: + PrintError(VM_NONE, VCORE_NONE, "Failed to save PIC\n"); + return -1; + } +static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) { + struct pic_internal * pic = (struct pic_internal *)private_data; + + V3_CHKPT_LOAD(ctx, "MASTER_IRR", pic->master_irr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_IRR", pic->slave_irr, loadfailout); + + V3_CHKPT_LOAD(ctx, "MASTER_ISR", pic->master_isr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ISR", pic->slave_isr, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ELCR", pic->master_elcr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ELCR", pic->slave_elcr, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ELCR_MASK", pic->master_elcr_mask, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ELCR_MASK", pic->slave_elcr_mask, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW1", pic->master_icw1, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW2", pic->master_icw2, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW3", pic->master_icw3, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW4", pic->master_icw4, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW1", pic->slave_icw1, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW2", pic->slave_icw2, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW3", pic->slave_icw3, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW4", pic->slave_icw4, loadfailout); + + + V3_CHKPT_LOAD(ctx, "MASTER_IMR", pic->master_imr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_IMR", pic->slave_imr, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_OCW2", pic->master_ocw2, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_OCW3", pic->master_ocw3, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_OCW2", pic->slave_ocw2, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_OCW3", pic->slave_ocw3, loadfailout); + + V3_CHKPT_LOAD(ctx, "MASTER_STATE", pic->master_state, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_STATE", pic->slave_state, loadfailout); + + return 0; + + loadfailout: + PrintError(VM_NONE, VCORE_NONE, "Failed to load PIC\n"); + return -1; +} + +#endif -static struct v3_device_ops dev_ops = { - .free = pic_free, +static struct v3_device_ops dev_ops = { + .free = (int (*)(void *))pic_free, +#ifdef V3_CONFIG_CHECKPOINT + .save = pic_save, + .load = pic_load +#endif }; -#include + static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) { struct pic_internal * state = NULL; @@ -749,23 +887,26 @@ static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) { // PIC is only usable in non-multicore environments // just hardcode the core context struct guest_info * core = &(vm->cores[0]); - - V3_ASSERT(state != NULL); - + state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal)); - + + if (!state) { + PrintError(vm, VCORE_NONE, "Cannot allocate in init\n"); + return -1; + } struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state); if (dev == NULL) { - PrintError("Could not add device %s\n", dev_id); + PrintError(vm, VCORE_NONE, "Could not add device %s\n", dev_id); V3_Free(state); return -1; } + state->core = core; - v3_register_intr_controller(core, &intr_ops, state); - v3_register_intr_router(vm, &router_ops, state); + state->controller_handle = v3_register_intr_controller(core, &intr_ops, state); + state->router_handle = v3_register_intr_router(vm, &router_ops, state); state->master_irr = 0; state->master_isr = 0; @@ -805,7 +946,7 @@ static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) { ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port); if (ret != 0) { - PrintError("Error hooking io ports\n"); + PrintError(vm, VCORE_NONE, "Error hooking io ports\n"); v3_remove_device(dev); return -1; }