X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8259a.c;h=bf3a1390457eea09a3a9a6dc04ef28a9df331000;hb=2377d33e71ba625a547b414916949181db2a49da;hp=336c0d7a8063b3d10891a15c9d4abf1584aee067;hpb=33717ee76445b728dfa74df98863f14118c8d41d;p=palacios.git diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c index 336c0d7..bf3a139 100644 --- a/palacios/src/devices/8259a.c +++ b/palacios/src/devices/8259a.c @@ -23,8 +23,9 @@ #include #include #include +#include -#ifndef DEBUG_PIC +#ifndef V3_CONFIG_DEBUG_PIC #undef PrintDebug #define PrintDebug(fmt, args...) #endif @@ -123,112 +124,133 @@ struct ocw3 { struct pic_internal { - uchar_t master_irr; - uchar_t slave_irr; + uint8_t master_irr; + uint8_t slave_irr; - uchar_t master_isr; - uchar_t slave_isr; + uint8_t master_isr; + uint8_t slave_isr; - uchar_t master_elcr; - uchar_t slave_elcr; - uchar_t master_elcr_mask; - uchar_t slave_elcr_mask; + uint8_t master_elcr; + uint8_t slave_elcr; + uint8_t master_elcr_mask; + uint8_t slave_elcr_mask; - uchar_t master_icw1; - uchar_t master_icw2; - uchar_t master_icw3; - uchar_t master_icw4; + uint8_t master_icw1; + uint8_t master_icw2; + uint8_t master_icw3; + uint8_t master_icw4; - uchar_t slave_icw1; - uchar_t slave_icw2; - uchar_t slave_icw3; - uchar_t slave_icw4; + uint8_t slave_icw1; + uint8_t slave_icw2; + uint8_t slave_icw3; + uint8_t slave_icw4; - uchar_t master_imr; - uchar_t slave_imr; - uchar_t master_ocw2; - uchar_t master_ocw3; - uchar_t slave_ocw2; - uchar_t slave_ocw3; + uint8_t master_imr; + uint8_t slave_imr; + uint8_t master_ocw2; + uint8_t master_ocw3; + uint8_t slave_ocw2; + uint8_t slave_ocw3; pic_state_t master_state; pic_state_t slave_state; + + struct guest_info * core; + + struct { + int (*ack)(struct guest_info * core, uint32_t irq, void * private_data); + void * private_data; + } irq_ack_cbs[15]; + + + void * router_handle; + void * controller_handle; }; static void DumpPICState(struct pic_internal *p) { - PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state); - PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr); - PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr); - PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_state=0x%x\n",p->master_state); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_irr=0x%x\n",p->master_irr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_isr=0x%x\n",p->master_isr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_imr=0x%x\n",p->master_imr); - PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2); - PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_ocw2=0x%x\n",p->master_ocw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_ocw3=0x%x\n",p->master_ocw3); - PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1); - PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2); - PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3); - PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw1=0x%x\n",p->master_icw1); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw2=0x%x\n",p->master_icw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw3=0x%x\n",p->master_icw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: master_icw4=0x%x\n",p->master_icw4); - PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state); - PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr); - PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr); - PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_state=0x%x\n",p->slave_state); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_irr=0x%x\n",p->slave_irr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_isr=0x%x\n",p->slave_isr); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_imr=0x%x\n",p->slave_imr); - PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2); - PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3); - PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1); - PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2); - PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3); - PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw1=0x%x\n",p->slave_icw1); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw2=0x%x\n",p->slave_icw2); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw3=0x%x\n",p->slave_icw3); + PrintDebug(VM_NONE, VCORE_NONE, "8259 PIC: slave_icw4=0x%x\n",p->slave_icw4); } -static int pic_raise_intr(void * private_data, int irq) { +static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) { struct pic_internal * state = (struct pic_internal*)private_data; + uint8_t irq_num = irq->irq; - if (irq == 2) { - irq = 9; - state->master_irr |= 0x04; // PAD + if (irq_num == 2) { + irq_num = 9; + state->master_irr |= 0x04; } - PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq); + PrintDebug(vm, VCORE_NONE, "8259 PIC: Raising irq %d in the PIC\n", irq_num); - if (irq <= 7) { - state->master_irr |= 0x01 << irq; - } else if ((irq > 7) && (irq < 16)) { - state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq + if (irq_num <= 7) { + state->master_irr |= 0x01 << irq_num; + } else if ((irq_num > 7) && (irq_num < 16)) { + state->slave_irr |= 0x01 << (irq_num - 8); } else { - PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq); + PrintDebug(vm, VCORE_NONE, "8259 PIC: Invalid IRQ raised (%d)\n", irq_num); return -1; } + state->irq_ack_cbs[irq_num].ack = irq->ack; + state->irq_ack_cbs[irq_num].private_data = irq->private_data; + + if (V3_Get_CPU() != vm->cores[0].pcpu_id) { + // guest is running on another core, interrupt it to deliver irq + v3_interrupt_cpu(vm, 0, 0); + } + return 0; } -static int pic_lower_intr(void *private_data, int irq) { +static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) { + struct pic_internal * state = (struct pic_internal*)private_data; + uint8_t irq_num = irq->irq; - struct pic_internal *state = (struct pic_internal*)private_data; - PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq); - if (irq <= 7) { + PrintDebug(vm, VCORE_NONE, "[pic_lower_intr] IRQ line %d now low\n", irq_num); + if (irq_num <= 7) { - state->master_irr &= ~(1 << irq); + state->master_irr &= ~(1 << irq_num); if ((state->master_irr & ~(state->master_imr)) == 0) { - PrintDebug("\t\tFIXME: Master maybe should do sth\n"); + PrintDebug(vm, VCORE_NONE, "\t\tFIXME: Master maybe should do sth\n"); } - } else if ((irq > 7) && (irq < 16)) { + } else if ((irq_num > 7) && (irq_num < 16)) { - state->slave_irr &= ~(1 << (irq - 8)); + state->slave_irr &= ~(1 << (irq_num - 8)); if ((state->slave_irr & (~(state->slave_imr))) == 0) { - PrintDebug("\t\tFIXME: Slave maybe should do sth\n"); + PrintDebug(vm, VCORE_NONE, "\t\tFIXME: Slave maybe should do sth\n"); } } return 0; @@ -236,7 +258,7 @@ static int pic_lower_intr(void *private_data, int irq) { -static int pic_intr_pending(void * private_data) { +static int pic_intr_pending(struct guest_info * info, void * private_data) { struct pic_internal * state = (struct pic_internal*)private_data; if ((state->master_irr & ~(state->master_imr)) || @@ -247,42 +269,45 @@ static int pic_intr_pending(void * private_data) { return 0; } -static int pic_get_intr_number(void * private_data) { +static int pic_get_intr_number(struct guest_info * info, void * private_data) { struct pic_internal * state = (struct pic_internal *)private_data; int i = 0; int irq = -1; - PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr); - PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr); + PrintDebug(info->vm_info, info, "8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr); + PrintDebug(info->vm_info, info, "8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr); for (i = 0; i < 16; i++) { if (i <= 7) { - if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) { + if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) { //state->master_isr |= (0x1 << i); // reset the irr //state->master_irr &= ~(0x1 << i); - PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2); + PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2); irq = i + state->master_icw2; break; } } else { - if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) { + if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) { //state->slave_isr |= (0x1 << (i - 8)); //state->slave_irr &= ~(0x1 << (i - 8)); - PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2); - irq= (i - 8) + state->slave_icw2; + PrintDebug(info->vm_info, info, "8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2); + irq = (i - 8) + state->slave_icw2; break; } } } +#if 1 if ((i == 15) || (i == 6)) { DumpPICState(state); } +#endif if (i == 16) { return -1; } else { + PrintDebug(info->vm_info, info, "8259 PIC: get num is returning %d\n",irq); return irq; } } @@ -290,35 +315,46 @@ static int pic_get_intr_number(void * private_data) { /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */ -static int pic_begin_irq(void * private_data, int irq) { +static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) { struct pic_internal * state = (struct pic_internal*)private_data; - + if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) { - irq &= 0x7; + irq &= 0x7; } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) { - irq &= 0x7; - irq += 8; + irq &= 0x7; + irq += 8; } else { - // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq); - return -1; + // PrintError(info->vm_info, info, "8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq); + return -1; } - + if (irq <= 7) { - if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) { - state->master_isr |= (0x1 << irq); + // This should always be true: See pic_get_intr_number + if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) { + state->master_isr |= (0x1 << irq); - if (!(state->master_elcr & (0x1 << irq))) { - state->master_irr &= ~(0x1 << irq); - } - } - } else { - state->slave_isr |= (0x1 << (irq - 8)); + if (!(state->master_elcr & (0x1 << irq))) { + state->master_irr &= ~(0x1 << irq); + } + } else { + PrintDebug(info->vm_info, info, "8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n", irq); + } - if (!(state->slave_elcr & (0x1 << irq))) { - state->slave_irr &= ~(0x1 << (irq - 8)); + } else { + // This should always be true: See pic_get_intr_number + if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) { + state->slave_isr |= (0x1 << (irq - 8)); + + if (!(state->slave_elcr & (0x1 << (irq - 8)))) { + state->slave_irr &= ~(0x1 << (irq - 8)); + } + } else { + PrintDebug(info->vm_info, info, "8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n", irq); } } + + return 0; } @@ -334,211 +370,242 @@ static int pic_begin_irq(void * private_data, int irq) { static struct intr_ctrl_ops intr_ops = { .intr_pending = pic_intr_pending, .get_intr_number = pic_get_intr_number, - .raise_intr = pic_raise_intr, - .begin_irq = pic_begin_irq, - .lower_intr = pic_lower_intr, - + .begin_irq = pic_begin_irq }; +static struct intr_router_ops router_ops = { + .raise_intr = pic_raise_intr, + .lower_intr = pic_lower_intr +}; - -static int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; +static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Master1)\n"); return -1; } if ((state->master_ocw3 & 0x03) == 0x02) { - *(uchar_t *)dst = state->master_irr; + *(uint8_t *)dst = state->master_irr; } else if ((state->master_ocw3 & 0x03) == 0x03) { - *(uchar_t *)dst = state->master_isr; + *(uint8_t *)dst = state->master_isr; } else { - *(uchar_t *)dst = 0; + *(uint8_t *)dst = 0; } return 1; } -static int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; +static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Master2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Master2)\n"); return -1; } - *(uchar_t *)dst = state->master_imr; + *(uint8_t *)dst = state->master_imr; return 1; } -static int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; +static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Slave1)\n"); return -1; } if ((state->slave_ocw3 & 0x03) == 0x02) { - *(uchar_t*)dst = state->slave_irr; + *(uint8_t*)dst = state->slave_irr; } else if ((state->slave_ocw3 & 0x03) == 0x03) { - *(uchar_t *)dst = state->slave_isr; + *(uint8_t *)dst = state->slave_isr; } else { - *(uchar_t *)dst = 0; + *(uint8_t *)dst = 0; } return 1; } -static int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; +static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Read length (rd_Slave2)\n"); return -1; } - *(uchar_t *)dst = state->slave_imr; + *(uint8_t *)dst = state->slave_imr; return 1; } -static int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; - uchar_t cw = *(uchar_t *)src; +static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write master port 1 with 0x%x\n",cw); if (length != 1) { - PrintError("8259 PIC: Invalid Write length (wr_Master1)\n"); - return -1; + PrintError(core->vm_info, core, "8259 PIC: Invalid Write length (wr_Master1)\n"); + return -1; } - + + v3_clear_pending_intr(core); + if (IS_ICW1(cw)) { - PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw); - - state->master_icw1 = cw; - state->master_state = ICW2; + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw); + + state->master_icw1 = cw; + state->master_state = ICW2; } else if (state->master_state == READY) { - if (IS_OCW2(cw)) { - // handle the EOI here - struct ocw2 * cw2 = (struct ocw2*)&cw; + if (IS_OCW2(cw)) { + // handle the EOI here + struct ocw2 * cw2 = (struct ocw2*)&cw; - PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw); - - if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { - // specific EOI; - state->master_isr &= ~(0x01 << cw2->level); - } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { - int i; - // Non-specific EOI - PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr); - for (i = 0; i < 8; i++) { - if (state->master_isr & (0x01 << i)) { - state->master_isr &= ~(0x01 << i); - break; - } - } - PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr); + PrintDebug(core->vm_info, core, "8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw); + + if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { + // specific EOI; + state->master_isr &= ~(0x01 << cw2->level); + + + /* + // ack the irq if requested + if (state->irq_ack_cbs[irq].ack) { + state->irq_ack_cbs[irq].ack(info, irq, state->irq_ack_cbs[irq].private_data); + } + */ + + } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { + int i; + // Non-specific EOI + PrintDebug(core->vm_info, core, "8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr); + for (i = 0; i < 8; i++) { + if (state->master_isr & (0x01 << i)) { + state->master_isr &= ~(0x01 << i); + break; + } + } + PrintDebug(core->vm_info, core, "8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr); + } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) { + PrintDebug(core->vm_info, core, "8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level); + } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) { + PrintDebug(core->vm_info, core, "8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level); } else { - PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n"); - return -1; + PrintError(core->vm_info, core, "8259 PIC: Command not handled, or in error (wr_Master1)\n"); + return -1; + } + + if (cw2->EOI) { + if (pic_get_intr_number(core, state) != -1) { + PrintError(core->vm_info, core, "Interrupt pending after EOI\n"); + } } - state->master_ocw2 = cw; - } else if (IS_OCW3(cw)) { - PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw); - state->master_ocw3 = cw; - } else { - PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n"); - PrintError("8259 PIC: CW=%x\n", cw); - return -1; - } + + state->master_ocw2 = cw; + } else if (IS_OCW3(cw)) { + PrintDebug(core->vm_info, core, "8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw); + state->master_ocw3 = cw; + } else { + PrintError(core->vm_info, core, "8259 PIC: Invalid OCW to PIC (wr_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: CW=%x\n", cw); + return -1; + } } else { - PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n"); - PrintError("8259 PIC: CW=%x\n", cw); - return -1; + PrintError(core->vm_info, core, "8259 PIC: Invalid PIC State (wr_Master1)\n"); + PrintError(core->vm_info, core, "8259 PIC: CW=%x\n", cw); + return -1; } return 1; } -static int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; - uchar_t cw = *(uchar_t *)src; +static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; + uint8_t cw = *(uint8_t *)src; + + PrintDebug(core->vm_info, core, "8259 PIC: Write master port 2 with 0x%x\n",cw); - PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw); - if (length != 1) { - PrintError("8259 PIC: Invalid Write length (wr_Master2)\n"); - return -1; + PrintError(core->vm_info, core, "8259 PIC: Invalid Write length (wr_Master2)\n"); + return -1; } - + + v3_clear_pending_intr(core); + if (state->master_state == ICW2) { - struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw); + state->master_icw2 = cw; + + + + if (cw1->sngl == 0) { + state->master_state = ICW3; + } else if (cw1->ic4 == 1) { + state->master_state = ICW4; + } else { + state->master_state = READY; + } - PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw); - state->master_icw2 = cw; - if (cw1->sngl == 0) { - state->master_state = ICW3; - } else if (cw1->ic4 == 1) { - state->master_state = ICW4; - } else { - state->master_state = READY; - } } else if (state->master_state == ICW3) { - struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw); - state->master_icw3 = cw; + state->master_icw3 = cw; - if (cw1->ic4 == 1) { - state->master_state = ICW4; - } else { - state->master_state = READY; - } + if (cw1->ic4 == 1) { + state->master_state = ICW4; + } else { + state->master_state = READY; + } } else if (state->master_state == ICW4) { - PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw); - state->master_icw4 = cw; - state->master_state = READY; - } else if (state->master_state == READY) { - PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw); - state->master_imr = cw; + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw); + state->master_icw4 = cw; + state->master_state = READY; + } else if ((state->master_state == ICW1) || (state->master_state == READY)) { + PrintDebug(core->vm_info, core, "8259 PIC: Setting IMR = %x (wr_Master2)\n", cw); + state->master_imr = cw; } else { - // error - PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n"); - return -1; + // error + PrintError(core->vm_info, core, "8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n", + state->master_state); + return -1; } return 1; } -static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; - uchar_t cw = *(uchar_t *)src; +static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write slave port 1 with 0x%x\n",cw); if (length != 1) { // error - PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid Write length (wr_Slave1)\n"); return -1; } + v3_clear_pending_intr(core); + if (IS_ICW1(cw)) { - PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw); state->slave_icw1 = cw; state->slave_state = ICW2; } else if (state->slave_state == READY) { @@ -546,7 +613,7 @@ static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm // handle the EOI here struct ocw2 * cw2 = (struct ocw2 *)&cw; - PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw); if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { // specific EOI; @@ -554,85 +621,96 @@ static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { int i; // Non-specific EOI - PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr); + PrintDebug(core->vm_info, core, "8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr); for (i = 0; i < 8; i++) { if (state->slave_isr & (0x01 << i)) { state->slave_isr &= ~(0x01 << i); break; } } - PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr); + PrintDebug(core->vm_info, core, "8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr); } else { - PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Command not handled or invalid (wr_Slave1)\n"); return -1; } + if (cw2->EOI) { + if (pic_get_intr_number(core, state) != -1) { + PrintError(core->vm_info, core, "Interrupt pending after EOI\n"); + } + } + + + state->slave_ocw2 = cw; } else if (IS_OCW3(cw)) { // Basically sets the IRR/ISR read flag - PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw); state->slave_ocw3 = cw; } else { - PrintError("8259 PIC: Invalid command work (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid command work (wr_Slave1)\n"); return -1; } } else { - PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n"); + PrintError(core->vm_info, core, "8259 PIC: Invalid State writing (wr_Slave1)\n"); return -1; } return 1; } -static int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; - uchar_t cw = *(uchar_t *)src; +static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; + uint8_t cw = *(uint8_t *)src; - PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw); + PrintDebug(core->vm_info, core, "8259 PIC: Write slave port 2 with 0x%x\n",cw); if (length != 1) { - PrintError("8259 PIC: Invalid write length (wr_Slave2)\n"); - return -1; + PrintError(core->vm_info, core, "8259 PIC: Invalid write length (wr_Slave2)\n"); + return -1; } + v3_clear_pending_intr(core); + + if (state->slave_state == ICW2) { - struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw); - state->slave_icw2 = cw; + state->slave_icw2 = cw; - if (cw1->sngl == 0) { - state->slave_state = ICW3; - } else if (cw1->ic4 == 1) { - state->slave_state = ICW4; - } else { - state->slave_state = READY; - } + if (cw1->sngl == 0) { + state->slave_state = ICW3; + } else if (cw1->ic4 == 1) { + state->slave_state = ICW4; + } else { + state->slave_state = READY; + } } else if (state->slave_state == ICW3) { - struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw); + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw); - state->slave_icw3 = cw; + state->slave_icw3 = cw; - if (cw1->ic4 == 1) { - state->slave_state = ICW4; - } else { - state->slave_state = READY; - } + if (cw1->ic4 == 1) { + state->slave_state = ICW4; + } else { + state->slave_state = READY; + } } else if (state->slave_state == ICW4) { - PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw); - state->slave_icw4 = cw; - state->slave_state = READY; - } else if (state->slave_state == READY) { - PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw); - state->slave_imr = cw; + PrintDebug(core->vm_info, core, "8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw); + state->slave_icw4 = cw; + state->slave_state = READY; + } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) { + PrintDebug(core->vm_info, core, "8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw); + state->slave_imr = cw; } else { - PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n"); - return -1; + PrintError(core->vm_info, core, "8259 PIC: Invalid State at write (wr_Slave2)\n"); + return -1; } return 1; @@ -641,11 +719,11 @@ static int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm -static int read_elcr_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; +static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("ELCR read of invalid length %d\n", length); + PrintError(core->vm_info, core, "ELCR read of invalid length %d\n", length); return -1; } @@ -655,7 +733,7 @@ static int read_elcr_port(ushort_t port, void * dst, uint_t length, struct vm_de } else if (port == ELCR2_PORT) { *(uint8_t *)dst = state->slave_elcr; } else { - PrintError("Invalid port %x\n", port); + PrintError(core->vm_info, core, "Invalid port %x\n", port); return -1; } @@ -663,11 +741,11 @@ static int read_elcr_port(ushort_t port, void * dst, uint_t length, struct vm_de } -static int write_elcr_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) { - struct pic_internal * state = (struct pic_internal*)dev->private_data; +static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) { + struct pic_internal * state = (struct pic_internal *)priv_data; if (length != 1) { - PrintError("ELCR read of invalid length %d\n", length); + PrintError(core->vm_info, core, "ELCR read of invalid length %d\n", length); return -1; } @@ -677,7 +755,7 @@ static int write_elcr_port(ushort_t port, void * src, uint_t length, struct vm_d } else if (port == ELCR2_PORT) { state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask; } else { - PrintError("Invalid port %x\n", port); + PrintError(core->vm_info, core, "Invalid port %x\n", port); return -1; } @@ -686,47 +764,149 @@ static int write_elcr_port(ushort_t port, void * src, uint_t length, struct vm_d +static int pic_free(struct pic_internal * state) { + struct guest_info * core = state->core; + + v3_remove_intr_controller(core, state->controller_handle); + v3_remove_intr_router(core->vm_info, state->router_handle); + + V3_Free(state); + return 0; +} + +#ifdef V3_CONFIG_CHECKPOINT +static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) { + struct pic_internal * pic = (struct pic_internal *)private_data; + + V3_CHKPT_SAVE(ctx, "MASTER_IRR", pic->master_irr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_IRR", pic->slave_irr, savefailout); + + V3_CHKPT_SAVE(ctx, "MASTER_ISR", pic->master_isr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ISR", pic->slave_isr, savefailout); + + V3_CHKPT_SAVE(ctx, "MASTER_ELCR", pic->master_elcr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ELCR", pic->slave_elcr, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ELCR_MASK", pic->master_elcr_mask, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ELCR_MASK", pic->slave_elcr_mask, savefailout); + + V3_CHKPT_SAVE(ctx, "MASTER_ICW1", pic->master_icw1, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ICW2", pic->master_icw2, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ICW3", pic->master_icw3, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_ICW4", pic->master_icw4, savefailout); + + V3_CHKPT_SAVE(ctx, "SLAVE_ICW1", pic->slave_icw1, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ICW2", pic->slave_icw2, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ICW3", pic->slave_icw3, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_ICW4", pic->slave_icw4, savefailout); -static int pic_free(struct vm_device * dev) { - v3_dev_unhook_io(dev, MASTER_PORT1); - v3_dev_unhook_io(dev, MASTER_PORT2); - v3_dev_unhook_io(dev, SLAVE_PORT1); - v3_dev_unhook_io(dev, SLAVE_PORT2); + V3_CHKPT_SAVE(ctx, "MASTER_IMR", pic->master_imr, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_IMR", pic->slave_imr, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_OCW2", pic->master_ocw2, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_OCW3", pic->master_ocw3, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_OCW2", pic->slave_ocw2, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_OCW3", pic->slave_ocw3, savefailout); + V3_CHKPT_SAVE(ctx, "MASTER_STATE", pic->master_state, savefailout); + V3_CHKPT_SAVE(ctx, "SLAVE_STATE", pic->slave_state, savefailout); + + return 0; + + savefailout: + PrintError(VM_NONE, VCORE_NONE, "Failed to save PIC\n"); + return -1; + } +static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) { + struct pic_internal * pic = (struct pic_internal *)private_data; + + + V3_CHKPT_LOAD(ctx, "MASTER_IRR", pic->master_irr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_IRR", pic->slave_irr, loadfailout); + + V3_CHKPT_LOAD(ctx, "MASTER_ISR", pic->master_isr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ISR", pic->slave_isr, loadfailout); + + V3_CHKPT_LOAD(ctx, "MASTER_ELCR", pic->master_elcr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ELCR", pic->slave_elcr, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ELCR_MASK", pic->master_elcr_mask, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ELCR_MASK", pic->slave_elcr_mask, loadfailout); + + V3_CHKPT_LOAD(ctx, "MASTER_ICW1", pic->master_icw1, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW2", pic->master_icw2, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW3", pic->master_icw3, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_ICW4", pic->master_icw4, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW1", pic->slave_icw1, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW2", pic->slave_icw2, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW3", pic->slave_icw3, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_ICW4", pic->slave_icw4, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_IMR", pic->master_imr, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_IMR", pic->slave_imr, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_OCW2", pic->master_ocw2, loadfailout); + V3_CHKPT_LOAD(ctx, "MASTER_OCW3", pic->master_ocw3, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_OCW2", pic->slave_ocw2, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_OCW3", pic->slave_ocw3, loadfailout); + + V3_CHKPT_LOAD(ctx, "MASTER_STATE", pic->master_state, loadfailout); + V3_CHKPT_LOAD(ctx, "SLAVE_STATE", pic->slave_state, loadfailout); + + return 0; + + loadfailout: + PrintError(VM_NONE, VCORE_NONE, "Failed to load PIC\n"); + return -1; +} + +#endif static struct v3_device_ops dev_ops = { - .free = pic_free, - .reset = NULL, - .start = NULL, - .stop = NULL, + .free = (int (*)(void *))pic_free, +#ifdef V3_CONFIG_CHECKPOINT + .save = pic_save, + .load = pic_load +#endif }; -static int pic_init(struct guest_info * vm, void * cfg_data) { + + +static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) { struct pic_internal * state = NULL; + char * dev_id = v3_cfg_val(cfg, "ID"); + int ret = 0; + + // PIC is only usable in non-multicore environments + // just hardcode the core context + struct guest_info * core = &(vm->cores[0]); + state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal)); - V3_ASSERT(state != NULL); - struct vm_device * dev = v3_allocate_device("8259A", &dev_ops, state); + if (!state) { + PrintError(vm, VCORE_NONE, "Cannot allocate in init\n"); + return -1; + } + + struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state); - if (v3_attach_device(vm, dev) == -1) { - PrintError("Could not attach device %s\n", "8259A"); + if (dev == NULL) { + PrintError(vm, VCORE_NONE, "Could not add device %s\n", dev_id); + V3_Free(state); return -1; } + state->core = core; - v3_register_intr_controller(vm, &intr_ops, state); + state->controller_handle = v3_register_intr_controller(core, &intr_ops, state); + state->router_handle = v3_register_intr_router(vm, &router_ops, state); state->master_irr = 0; state->master_isr = 0; @@ -756,14 +936,20 @@ static int pic_init(struct guest_info * vm, void * cfg_data) { state->slave_state = ICW1; - v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1); - v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2); - v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1); - v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2); + ret |= v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1); + ret |= v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2); + ret |= v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1); + ret |= v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2); - v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port); - v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port); + ret |= v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port); + ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port); + + if (ret != 0) { + PrintError(vm, VCORE_NONE, "Error hooking io ports\n"); + v3_remove_device(dev); + return -1; + } return 0; }