X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8259a.c;h=6fe165e131f8fa98f963c212daae0b4eccfcc8ce;hb=56f8088296ee4116a4811a2f4f843edd80a7748d;hp=963e7a89ab908bf4b6bf120808e9de8adca5aafa;hpb=2b1f4ef19d766727f873476861c64339c8836a40;p=palacios.git diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c index 963e7a8..6fe165e 100644 --- a/palacios/src/devices/8259a.c +++ b/palacios/src/devices/8259a.c @@ -1,8 +1,16 @@ +/* (c) 2008, Jack Lange */ +/* (c) 2008, The V3VEE Project */ + #include #include #include #include +#ifndef DEBUG_PIC +#undef PrintDebug +#define PrintDebug(fmt, args...) +#endif + typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t; @@ -11,9 +19,11 @@ static const uint_t MASTER_PORT2 = 0x21; static const uint_t SLAVE_PORT1 = 0xA0; static const uint_t SLAVE_PORT2 = 0xA1; +#define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1) #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0) #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1) + struct icw1 { uint_t ic4 : 1; // ICW4 has to be read uint_t sngl : 1; // single (only one PIC) @@ -91,58 +101,116 @@ struct ocw3 { struct pic_internal { - char master_irr; - char slave_irr; + uchar_t master_irr; + uchar_t slave_irr; - char master_isr; - char slave_isr; + uchar_t master_isr; + uchar_t slave_isr; - char master_icw1; - char master_icw2; - char master_icw3; - char master_icw4; + uchar_t master_icw1; + uchar_t master_icw2; + uchar_t master_icw3; + uchar_t master_icw4; - char slave_icw1; - char slave_icw2; - char slave_icw3; - char slave_icw4; + uchar_t slave_icw1; + uchar_t slave_icw2; + uchar_t slave_icw3; + uchar_t slave_icw4; - char master_imr; - char slave_imr; - char master_ocw2; - char master_ocw3; - char slave_ocw2; - char slave_ocw3; + uchar_t master_imr; + uchar_t slave_imr; + uchar_t master_ocw2; + uchar_t master_ocw3; + uchar_t slave_ocw2; + uchar_t slave_ocw3; pic_state_t master_state; pic_state_t slave_state; }; +static void DumpPICState(struct pic_internal *p) +{ + + PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state); + PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr); + PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr); + PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr); + + PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2); + PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3); + + PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1); + PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2); + PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3); + PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4); + + PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state); + PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr); + PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr); + PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr); + + PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2); + PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3); + + PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1); + PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2); + PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3); + PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4); + +} + -static int pic_raise_intr(void * private_data, int irq, int error_code) { +static int pic_raise_intr(void * private_data, int irq) { struct pic_internal * state = (struct pic_internal*)private_data; if (irq == 2) { irq = 9; + state->master_irr |= 0x04; // PAD } - PrintDebug("Raising irq %d in the PIC\n", irq); + PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq); if (irq <= 7) { state->master_irr |= 0x01 << irq; } else if ((irq > 7) && (irq < 16)) { - state->slave_irr |= 0x01 << (irq - 7); + state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq } else { - PrintDebug("Invalid IRQ raised (%d)\n", irq); + PrintError("8259 PIC: Invalid IRQ raised (%d)\n", irq); return -1; } return 0; } + +/*Zheng 07/30/2008*/ + +static int pic_lower_intr(void *private_data, int irq_no) { + + struct pic_internal *state = (struct pic_internal*)private_data; + + PrintDebug("[pic_lower_intr] IRQ line %d now low\n", (unsigned) irq_no); + if (irq_no <= 7) { + + state->master_irr &= ~(1 << irq_no); + if ((state->master_irr & ~(state->master_imr)) == 0) { + PrintDebug("\t\tFIXME: Master maybe should do sth\n"); + } + } else if ((irq_no > 7) && (irq_no <= 15)) { + + state->slave_irr &= ~(1 << (irq_no - 8)); + if ((state->slave_irr & (~(state->slave_imr))) == 0) { + PrintDebug("\t\tFIXME: Slave maybe should do sth\n"); + } + } + return 0; +} + + + static int pic_intr_pending(void * private_data) { struct pic_internal * state = (struct pic_internal*)private_data; @@ -155,48 +223,90 @@ static int pic_intr_pending(void * private_data) { } static int pic_get_intr_number(void * private_data) { - struct pic_internal * state = (struct pic_internal*)private_data; - int i; + struct pic_internal * state = (struct pic_internal *)private_data; + int i = 0; + int irq = -1; + + PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr); + PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr); for (i = 0; i < 16; i++) { if (i <= 7) { if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) { - state->master_isr |= (0x1 << i); + //state->master_isr |= (0x1 << i); // reset the irr - state->master_irr &= ~(0x1 << i); - PrintDebug("IRQ: %d, icw2: %x\n", i, state->master_icw2); - return i + state->master_icw2; + //state->master_irr &= ~(0x1 << i); + PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2); + irq= i + state->master_icw2; + break; } } else { if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) { - state->slave_isr |= (0x1 << (i - 8)); - state->slave_irr &= ~(0x1 << (i - 8)); - return (i - 8) + state->slave_icw2; + //state->slave_isr |= (0x1 << (i - 8)); + //state->slave_irr &= ~(0x1 << (i - 8)); + PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2); + irq= (i - 8) + state->slave_icw2; + break; } } } - return 0; + if ((i == 15) || (i == 6)) { + DumpPICState(state); + } + + if (i == 16) { + return -1; + } else { + return irq; + } } + +/* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */ static int pic_begin_irq(void * private_data, int irq) { + struct pic_internal * state = (struct pic_internal*)private_data; + + if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) { + irq &= 0x7; + } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) { + irq &= 0x7; + irq += 8; + } else { + PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq); + return -1; + } + + if (irq <= 7) { + if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) { + state->master_isr |= (0x1 << irq); + state->master_irr &= ~(0x1 << irq); + } + } else { + state->slave_isr |= (0x1 << (irq - 8)); + state->slave_irr &= ~(0x1 << (irq - 8)); + } return 0; } + /* static int pic_end_irq(void * private_data, int irq) { - return 0; } */ + +/*Zheng 07/30/2008*/ static struct intr_ctrl_ops intr_ops = { .intr_pending = pic_intr_pending, .get_intr_number = pic_get_intr_number, .raise_intr = pic_raise_intr, .begin_irq = pic_begin_irq, + .lower_intr = pic_lower_intr, //Zheng added + }; @@ -204,16 +314,18 @@ static struct intr_ctrl_ops intr_ops = { int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - //error + PrintError("8259 PIC: Invalid Read length (rd_Master1)\n"); + return -1; } if ((state->master_ocw3 & 0x03) == 0x02) { - *(char *)dst = state->master_irr; + *(uchar_t *)dst = state->master_irr; } else if ((state->master_ocw3 & 0x03) == 0x03) { - *(char *)dst = state->master_isr; + *(uchar_t *)dst = state->master_isr; } else { - *(char *)dst = 0; + *(uchar_t *)dst = 0; } return 1; @@ -221,11 +333,13 @@ int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - // error + PrintError("8259 PIC: Invalid Read length (rd_Master2)\n"); + return -1; } - *(char *)dst = state->master_imr; + *(uchar_t *)dst = state->master_imr; return 1; @@ -233,16 +347,18 @@ int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - // error + PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n"); + return -1; } if ((state->slave_ocw3 & 0x03) == 0x02) { - *(char*)dst = state->slave_irr; + *(uchar_t*)dst = state->slave_irr; } else if ((state->slave_ocw3 & 0x03) == 0x03) { - *(char *)dst = state->slave_isr; + *(uchar_t *)dst = state->slave_isr; } else { - *(char *)dst = 0; + *(uchar_t *)dst = 0; } return 1; @@ -250,11 +366,13 @@ int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - // error + PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n"); + return -1; } - *(char *)dst = state->slave_imr; + *(uchar_t *)dst = state->slave_imr; return 1; } @@ -262,13 +380,19 @@ int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; - char cw = *(char *)src; + uchar_t cw = *(uchar_t *)src; + + PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw); if (length != 1) { - // error + PrintError("8259 PIC: Invalid Write length (wr_Master1)\n"); + return -1; } - if (state->master_state == ICW1) { + if (IS_ICW1(cw)) { + + PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw); + state->master_icw1 = cw; state->master_state = ICW2; @@ -277,6 +401,7 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic // handle the EOI here struct ocw2 * cw2 = (struct ocw2*)&cw; + PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw); if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { // specific EOI; @@ -284,26 +409,32 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { int i; // Non-specific EOI - PrintDebug("Pre ISR = %x\n", state->master_isr); + PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr); for (i = 0; i < 8; i++) { if (state->master_isr & (0x01 << i)) { state->master_isr &= ~(0x01 << i); break; } } - PrintDebug("Post ISR = %x\n", state->master_isr); + PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr); } else { - // error; + PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n"); + return -1; } state->master_ocw2 = cw; } else if (IS_OCW3(cw)) { + PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw); state->master_ocw3 = cw; } else { - // error + PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n"); + PrintError("8259 PIC: CW=%x\n", cw); + return -1; } } else { - // error + PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n"); + PrintError("8259 PIC: CW=%x\n", cw); + return -1; } return 1; @@ -311,16 +442,19 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; - char cw = *(char *)src; + uchar_t cw = *(uchar_t *)src; + PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw); + if (length != 1) { - //error + PrintError("8259 PIC: Invalid Write length (wr_Master2)\n"); + return -1; } if (state->master_state == ICW2) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); - PrintDebug("Setting ICW2 = %x\n", cw); + PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw); state->master_icw2 = cw; if (cw1->sngl == 0) { @@ -334,6 +468,8 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic } else if (state->master_state == ICW3) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw); + state->master_icw3 = cw; if (cw1->ic4 == 1) { @@ -343,12 +479,16 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic } } else if (state->master_state == ICW4) { + PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw); state->master_icw4 = cw; state->master_state = READY; } else if (state->master_state == READY) { + PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw); state->master_imr = cw; } else { // error + PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n"); + return -1; } return 1; @@ -356,19 +496,26 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; - char cw = *(char *)src; + uchar_t cw = *(uchar_t *)src; + + PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw); if (length != 1) { // error + PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n"); + return -1; } - if (state->slave_state == ICW1) { + if (IS_ICW1(cw)) { + PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw); state->slave_icw1 = cw; state->slave_state = ICW2; } else if (state->slave_state == READY) { if (IS_OCW2(cw)) { // handle the EOI here struct ocw2 * cw2 = (struct ocw2 *)&cw; + + PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw); if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { // specific EOI; @@ -376,27 +523,31 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { int i; // Non-specific EOI - PrintDebug("Pre ISR = %x\n", state->slave_isr); + PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr); for (i = 0; i < 8; i++) { if (state->slave_isr & (0x01 << i)) { state->slave_isr &= ~(0x01 << i); break; } } - PrintDebug("Post ISR = %x\n", state->slave_isr); + PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr); } else { - // error; + PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n"); + return -1; } state->slave_ocw2 = cw; } else if (IS_OCW3(cw)) { // Basically sets the IRR/ISR read flag + PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw); state->slave_ocw3 = cw; } else { - // error + PrintError("8259 PIC: Invalid command work (wr_Slave1)\n"); + return -1; } } else { - // error + PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n"); + return -1; } return 1; @@ -404,15 +555,20 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; - char cw = *(char *)src; + uchar_t cw = *(uchar_t *)src; + + PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw); if (length != 1) { - //error + PrintError("8259 PIC: Invalid write length (wr_Slave2)\n"); + return -1; } if (state->slave_state == ICW2) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw); + state->slave_icw2 = cw; if (cw1->sngl == 0) { @@ -426,6 +582,8 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device } else if (state->slave_state == ICW3) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw); + state->slave_icw3 = cw; if (cw1->ic4 == 1) { @@ -435,12 +593,15 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device } } else if (state->slave_state == ICW4) { + PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw); state->slave_icw4 = cw; state->slave_state = READY; } else if (state->slave_state == READY) { + PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw); state->slave_imr = cw; } else { - // error + PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n"); + return -1; } return 1; @@ -517,7 +678,8 @@ static struct vm_device_ops dev_ops = { struct vm_device * create_pic() { struct pic_internal * state = NULL; - V3_Malloc(struct pic_internal *, state, sizeof(struct pic_internal)); + state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal)); + V3_ASSERT(state != NULL); struct vm_device *device = create_device("8259A", &dev_ops, state);