X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8259a.c;h=31aa28adf6fae61374736ef896c9a21bc68cf479;hb=4b013fe3750a387fc034352a7e4379f025dad7c2;hp=efa14e45624223fd7ac471916f942aff59a71c81;hpb=881733821ac0efab7d80485e86eb6bbb0e92e59e;p=palacios.git

diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c
index efa14e4..31aa28a 100644
--- a/palacios/src/devices/8259a.c
+++ b/palacios/src/devices/8259a.c
@@ -129,11 +129,14 @@ static int pic_raise_intr(void * private_data, int irq, int error_code) {
     irq = 9;
   }
 
+  PrintDebug("Raising irq %d in the PIC\n", irq);
+
   if (irq <= 7) {
     state->master_irr |= 0x01 << irq;
   } else if ((irq > 7) && (irq < 16)) {
     state->slave_irr |= 0x01 << (irq - 7);
   } else {
+    PrintDebug("Invalid IRQ raised (%d)\n", irq);
     return -1;
   }
 
@@ -158,11 +161,17 @@ static int pic_get_intr_number(void * private_data) {
   for (i = 0; i < 16; i++) {
     if (i <= 7) {
       if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
-	return i;
+	state->master_isr |= (0x1 << i);
+	// reset the irr
+	state->master_irr &= ~(0x1 << i);
+	PrintDebug("IRQ: %d, icw2: %x\n", i, state->master_icw2);
+	return i + state->master_icw2;
       }
     } else {
-      if (((state->slave_irr & ~(state->slave_imr)) >> i) == 0x01) {
-	return i;
+      if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
+	state->slave_isr |= (0x1 << (i - 8));
+	state->slave_irr &= ~(0x1 << (i - 8));
+	return (i - 8) + state->slave_icw2;
       }
     }
   }
@@ -171,30 +180,28 @@ static int pic_get_intr_number(void * private_data) {
 }
 
 
-static int begin_irq(void * private_data, int irq) {
+static int pic_begin_irq(void * private_data, int irq) {
 
   return 0;
 }
 
-static int end_irq(void * private_data, int irq) {
+/*
+static int pic_end_irq(void * private_data, int irq) {
 
   return 0;
 }
-
+*/
 
 static struct intr_ctrl_ops intr_ops = {
   .intr_pending = pic_intr_pending,
   .get_intr_number = pic_get_intr_number,
   .raise_intr = pic_raise_intr,
-  .begin_irq = begin_irq,
+  .begin_irq = pic_begin_irq,
 };
 
 
 
 
-
-
-
 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
   struct pic_internal * state = (struct pic_internal*)dev->private_data;
   if (length != 1) {
@@ -264,14 +271,27 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic
   if (state->master_state == ICW1) {
     state->master_icw1 = cw;
     state->master_state = ICW2;
+
   } else if (state->master_state == READY) {
     if (IS_OCW2(cw)) {
       // handle the EOI here
-      struct ocw2 * cw2 =  (struct ocw2 *)cw;
+      struct ocw2 * cw2 =  (struct ocw2*)&cw;
+
       
       if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
 	// specific EOI;
 	state->master_isr &= ~(0x01 << cw2->level);
+      } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
+	int i;
+	// Non-specific EOI
+	PrintDebug("Pre ISR = %x\n", state->master_isr);
+	for (i = 0; i < 8; i++) {
+	  if (state->master_isr & (0x01 << i)) {
+	    state->master_isr &= ~(0x01 << i);
+	    break;
+	  }
+	}	
+       	PrintDebug("Post ISR = %x\n", state->master_isr);
       } else {
 	// error;
       }
@@ -300,6 +320,7 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic
     if (state->master_state == ICW2) {
       struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
 
+      PrintDebug("Setting ICW2 = %x\n", cw);
       state->master_icw2 = cw;
 
       if (cw1->sngl == 0) {
@@ -347,11 +368,22 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device
   } else if (state->slave_state == READY) {
     if (IS_OCW2(cw)) {
       // handle the EOI here
-      struct ocw2 * cw2 =  (struct ocw2 *)cw;
+      struct ocw2 * cw2 =  (struct ocw2 *)&cw;
       
       if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
 	// specific EOI;
 	state->slave_isr &= ~(0x01 << cw2->level);
+      } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
+	int i;
+	// Non-specific EOI
+	PrintDebug("Pre ISR = %x\n", state->slave_isr);
+	for (i = 0; i < 8; i++) {
+	  if (state->slave_isr & (0x01 << i)) {
+	    state->slave_isr &= ~(0x01 << i);
+	    break;
+	  }
+	}	
+       	PrintDebug("Post ISR = %x\n", state->slave_isr);
       } else {
 	// error;
       }