X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8259a.c;h=0f712b0f2085066f0ec05363ba506956dadeb180;hb=d8e510143aa094363d5bf21d6cb7e31a29a6e826;hp=2e305e9a88d5b86d111e2dcd7c27c9fed4007c11;hpb=159356d2478ab200cda0a0aa726d8f1bfa4ffeeb;p=palacios.git diff --git a/palacios/src/devices/8259a.c b/palacios/src/devices/8259a.c index 2e305e9..0f712b0 100644 --- a/palacios/src/devices/8259a.c +++ b/palacios/src/devices/8259a.c @@ -11,9 +11,11 @@ static const uint_t MASTER_PORT2 = 0x21; static const uint_t SLAVE_PORT1 = 0xA0; static const uint_t SLAVE_PORT2 = 0xA1; +#define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1) #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0) #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1) + struct icw1 { uint_t ic4 : 1; // ICW4 has to be read uint_t sngl : 1; // single (only one PIC) @@ -122,18 +124,21 @@ struct pic_internal { -static int pic_raise_intr(void * private_data, int irq, int error_code) { +static int pic_raise_intr(void * private_data, int irq) { struct pic_internal * state = (struct pic_internal*)private_data; if (irq == 2) { irq = 9; } + PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq); + if (irq <= 7) { - state->master_irr |= 0x1 << irq; + state->master_irr |= 0x01 << irq; } else if ((irq > 7) && (irq < 16)) { - state->slave_irr |= 0x1 << (irq - 7); + state->slave_irr |= 0x01 << (irq - 7); } else { + PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq); return -1; } @@ -157,12 +162,18 @@ static int pic_get_intr_number(void * private_data) { for (i = 0; i < 16; i++) { if (i <= 7) { - if (((state->master_irr & ~(state->master_imr)) >> i) == 0x1) { - return i; + if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) { + //state->master_isr |= (0x1 << i); + // reset the irr + //state->master_irr &= ~(0x1 << i); + PrintDebug("8259 PIC: IRQ: %d, icw2: %x\n", i, state->master_icw2); + return i + state->master_icw2; } } else { - if (((state->slave_irr & ~(state->slave_imr)) >> i) == 0x1) { - return i; + if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) { + //state->slave_isr |= (0x1 << (i - 8)); + //state->slave_irr &= ~(0x1 << (i - 8)); + return (i - 8) + state->slave_icw2; } } } @@ -171,27 +182,62 @@ static int pic_get_intr_number(void * private_data) { } + +/* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */ +static int pic_begin_irq(void * private_data, int irq) { + struct pic_internal * state = (struct pic_internal*)private_data; + + if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) { + irq &= 0x7; + } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) { + irq &= 0x7; + irq += 8; + } else { + PrintDebug("8259 PIC: Could not find IRQ to Begin\n"); + return -1; + } + + if (irq <= 7) { + if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) { + state->master_isr |= (0x1 << irq); + state->master_irr &= ~(0x1 << irq); + } + } else { + state->slave_isr |= (0x1 << (irq - 8)); + state->slave_irr &= ~(0x1 << (irq - 8)); + } + + return 0; +} + + +/* +static int pic_end_irq(void * private_data, int irq) { + return 0; +} +*/ + static struct intr_ctrl_ops intr_ops = { .intr_pending = pic_intr_pending, .get_intr_number = pic_get_intr_number, - .raise_intr = pic_raise_intr + .raise_intr = pic_raise_intr, + .begin_irq = pic_begin_irq, }; - - - int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - //error + PrintDebug("8259 PIC: Invalid Read length (rd_Master1)\n"); + return -1; } - if ((state->master_ocw3 & 0x3) == 0x2) { + if ((state->master_ocw3 & 0x03) == 0x02) { *(char *)dst = state->master_irr; - } else if ((state->master_ocw3 & 0x3) == 0x3) { + } else if ((state->master_ocw3 & 0x03) == 0x03) { *(char *)dst = state->master_isr; } else { *(char *)dst = 0; @@ -202,8 +248,10 @@ int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - // error + PrintDebug("8259 PIC: Invalid Read length (rd_Master2)\n"); + return -1; } *(char *)dst = state->master_imr; @@ -214,13 +262,15 @@ int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - // error + PrintDebug("8259 PIC: Invalid Read length (rd_Slave1)\n"); + return -1; } - if ((state->slave_ocw3 & 0x3) == 0x2) { + if ((state->slave_ocw3 & 0x03) == 0x02) { *(char*)dst = state->slave_irr; - } else if ((state->slave_ocw3 & 0x3) == 0x3) { + } else if ((state->slave_ocw3 & 0x03) == 0x03) { *(char *)dst = state->slave_isr; } else { *(char *)dst = 0; @@ -231,8 +281,10 @@ int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) { struct pic_internal * state = (struct pic_internal*)dev->private_data; + if (length != 1) { - // error + PrintDebug("8259 PIC: Invalid Read length (rd_Slave2)\n"); + return -1; } *(char *)dst = state->slave_imr; @@ -246,22 +298,51 @@ int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_devic char cw = *(char *)src; if (length != 1) { - // error + PrintDebug("8259 PIC: Invalid Write length (wr_Master1)\n"); + return -1; } - if (state->master_state == ICW1) { + if (IS_ICW1(cw)) { state->master_icw1 = cw; state->master_state = ICW2; + } else if (state->master_state == READY) { if (IS_OCW2(cw)) { + // handle the EOI here + struct ocw2 * cw2 = (struct ocw2*)&cw; + + + if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { + // specific EOI; + state->master_isr &= ~(0x01 << cw2->level); + } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { + int i; + // Non-specific EOI + PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr); + for (i = 0; i < 8; i++) { + if (state->master_isr & (0x01 << i)) { + state->master_isr &= ~(0x01 << i); + break; + } + } + PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr); + } else { + PrintDebug("8259 PIC: Command not handled, or in error (wr_Master1)\n"); + return -1; + } + state->master_ocw2 = cw; } else if (IS_OCW3(cw)) { state->master_ocw3 = cw; } else { - // error + PrintDebug("8259 PIC: Invalid OCW to PIC (wr_Master1)\n"); + PrintDebug("8259 PIC: CW=%x\n", cw); + return -1; } } else { - // error + PrintDebug("8259 PIC: Invalid PIC State (wr_Master1)\n"); + PrintDebug("8259 PIC: CW=%x\n", cw); + return -1; } return 1; @@ -272,12 +353,14 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic char cw = *(char *)src; if (length != 1) { - //error + PrintDebug("8259 PIC: Invalid Write length (wr_Master2)\n"); + return -1; } if (state->master_state == ICW2) { struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1); + PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw); state->master_icw2 = cw; if (cw1->sngl == 0) { @@ -306,6 +389,8 @@ int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_devic state->master_imr = cw; } else { // error + PrintDebug("8259 PIC: Invalid master PIC State (wr_Master2)\n"); + return -1; } return 1; @@ -317,21 +402,48 @@ int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device if (length != 1) { // error + PrintDebug("8259 PIC: Invalid Write length (wr_Slave1)\n"); + return -1; } - if (state->slave_state == ICW1) { + if (IS_ICW1(cw)) { state->slave_icw1 = cw; state->slave_state = ICW2; } else if (state->slave_state == READY) { if (IS_OCW2(cw)) { + // handle the EOI here + struct ocw2 * cw2 = (struct ocw2 *)&cw; + + if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) { + // specific EOI; + state->slave_isr &= ~(0x01 << cw2->level); + } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) { + int i; + // Non-specific EOI + PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr); + for (i = 0; i < 8; i++) { + if (state->slave_isr & (0x01 << i)) { + state->slave_isr &= ~(0x01 << i); + break; + } + } + PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr); + } else { + PrintDebug("8259 PIC: Command not handled or invalid (wr_Slave1)\n"); + return -1; + } + state->slave_ocw2 = cw; } else if (IS_OCW3(cw)) { + // Basically sets the IRR/ISR read flag state->slave_ocw3 = cw; } else { - // error + PrintDebug("8259 PIC: Invalid command work (wr_Slave1)\n"); + return -1; } } else { - // error + PrintDebug("8259 PIC: Invalid State writing (wr_Slave1)\n"); + return -1; } return 1; @@ -342,7 +454,8 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device char cw = *(char *)src; if (length != 1) { - //error + PrintDebug("8259 PIC: Invalid write length (wr_Slave2)\n"); + return -1; } if (state->slave_state == ICW2) { @@ -375,7 +488,8 @@ int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device } else if (state->slave_state == READY) { state->slave_imr = cw; } else { - // error + PrintDebug("8259 PIC: Invalid State at write (wr_Slave2)\n"); + return -1; } return 1; @@ -401,7 +515,7 @@ int pic_init(struct vm_device * dev) { state->master_icw4 = 0; state->master_imr = 0; state->master_ocw2 = 0; - state->master_ocw3 = 0x2; + state->master_ocw3 = 0x02; state->master_state = ICW1; @@ -413,7 +527,7 @@ int pic_init(struct vm_device * dev) { state->slave_icw4 = 0; state->slave_imr = 0; state->slave_ocw2 = 0; - state->slave_ocw3 = 0x2; + state->slave_ocw3 = 0x02; state->slave_state = ICW1; @@ -452,7 +566,8 @@ static struct vm_device_ops dev_ops = { struct vm_device * create_pic() { struct pic_internal * state = NULL; - VMMMalloc(struct pic_internal *, state, sizeof(struct pic_internal)); + state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal)); + V3_ASSERT(state != NULL); struct vm_device *device = create_device("8259A", &dev_ops, state);