X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Fsrc%2Fdevices%2F8254.c;h=df0c169933b7a3647a8843baa6d2d81bc0294674;hb=9dd0a80f28ca47a1fb69992dcd96e7526bf5175c;hp=65a1e01649884036a1723f4e5c1148f98f21d5da;hpb=bf091be03d4a623fa1a9b3151698a4564a8339ba;p=palacios.git

diff --git a/palacios/src/devices/8254.c b/palacios/src/devices/8254.c
index 65a1e01..df0c169 100644
--- a/palacios/src/devices/8254.c
+++ b/palacios/src/devices/8254.c
@@ -2,10 +2,14 @@
 #include <palacios/vmm.h>
 #include <palacios/vmm_time.h>
 #include <palacios/vmm_util.h>
+#include <palacios/vmm_intr.h>
 
 
 
-
+#ifndef DEBUG_PIT
+#undef PrintDebug
+#define PrintDebug(fmt, args...)
+#endif
 
 
 
@@ -239,7 +243,7 @@ static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priva
     if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
       // raise interrupt
       PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
-      dev->vm->vm_ops.raise_irq(dev->vm, 0);
+      v3_raise_irq(dev->vm, 0);
     }
 
     //handle_crystal_tics(dev, &(state->ch_1), oscillations);
@@ -401,7 +405,7 @@ static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_
   char * val = (char *)dst;
 
   if (length != 1) {
-    PrintDebug("8254 PIT: Invalid Read Write length \n");
+    PrintError("8254 PIT: Invalid Read Write length \n");
     return -1;
   }
 
@@ -424,7 +428,7 @@ static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_
     }
     break;
   default:
-    PrintDebug("8254 PIT: Read from invalid port (%d)\n", port);
+    PrintError("8254 PIT: Read from invalid port (%d)\n", port);
     return -1;
   }
 
@@ -438,7 +442,7 @@ static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm
   char val = *(char *)src;
 
   if (length != 1) {
-    PrintDebug("8254 PIT: Invalid Write Length\n");
+    PrintError("8254 PIT: Invalid Write Length\n");
     return -1;
   }
 
@@ -462,7 +466,7 @@ static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm
     }
     break;
   default:
-    PrintDebug("8254 PIT: Write to invalid port (%d)\n", port);
+    PrintError("8254 PIT: Write to invalid port (%d)\n", port);
     return -1;
   }
 
@@ -479,7 +483,7 @@ static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm
   PrintDebug("8254 PIT: Write to PIT Command port\n");
   PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
   if (length != 1) {
-    PrintDebug("8254 PIT: Write of Invalid length to command port\n");
+    PrintError("8254 PIT: Write of Invalid length to command port\n");
     return -1;
   }
 
@@ -548,10 +552,11 @@ static int pit_init(struct vm_device * dev) {
   dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
   dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
 
+#ifdef DEBUG_PIT
   PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
   PrintTraceLL(reload_val);
   PrintDebug("\n");
-
+#endif
 
   v3_add_timer(dev->vm, &timer_ops, dev);
 
@@ -567,9 +572,11 @@ static int pit_init(struct vm_device * dev) {
   init_channel(&(state->ch_1));
   init_channel(&(state->ch_2));
 
+#ifdef DEBUG_PIT
   PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
   PrintTraceLL(state->pit_counter);
   PrintDebug("\n");
+#endif
 
   return 0;
 }