X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Finclude%2Fpalacios%2Fvmx_hw_info.h;h=c11dcb1c849ef538bb4ab5ee12c0e0148c70f95a;hb=5614cff13837121053e831419f569b4e6e32bcd9;hp=baade9cc44a61c5a0698aa018b60ebc9facc2e46;hpb=15f1869089d6d3c4dc745ac2673e3cc0dd315962;p=palacios.git

diff --git a/palacios/include/palacios/vmx_hw_info.h b/palacios/include/palacios/vmx_hw_info.h
index baade9c..c11dcb1 100644
--- a/palacios/include/palacios/vmx_hw_info.h
+++ b/palacios/include/palacios/vmx_hw_info.h
@@ -24,6 +24,7 @@
 #ifdef __V3VEE__
 
 
+
 #define VMX_BASIC_MSR               0x00000480
 #define VMX_PINBASED_CTLS_MSR       0x00000481
 #define VMX_PROCBASED_CTLS_MSR      0x00000482
@@ -35,44 +36,136 @@
 #define VMX_CR4_FIXED0_MSR          0x00000488
 #define VMX_CR4_FIXED1_MSR          0x00000489
 #define VMX_VMCS_ENUM_MSR           0x0000048A
-
+#define VMX_PROCBASED_CTLS2_MSR     0x0000048B
+#define VMX_EPT_VPID_CAP_MSR        0x0000048C
+#define VMX_TRUE_PINBASED_CTLS_MSR  0x0000048D
+#define VMX_TRUE_PROCBASED_CTLS_MSR 0x0000048E
+#define VMX_TRUE_EXIT_CTLS_MSR      0x0000048F
+#define VMX_TRUE_ENTRY_CTLS_MSR     0x00000490
 
 
 
 struct vmx_basic_msr {
     union {
-	uint32_t lo;
-	uint32_t hi;
 	struct {
-	    uint32_t revision;
-	    uint32_t regionSize   : 13;
-	    uint8_t rsvd1         : 4; /* Always 0 */
-	    uint8_t physWidth     : 1; /* VMCS address field widths 
+	    uint32_t lo;
+	    uint32_t hi;
+	} __attribute__((packed));
+
+	struct {    uint32_t revision;
+	    uint64_t regionSize   : 13;
+	    uint64_t rsvd1         : 3; /* Always 0 */
+	    uint64_t physWidth     : 1; /* VMCS address field widths 
 					  (1=32bits, 0=natural width) */
-	    uint8_t smm           : 1; // Always 1
-	    uint8_t memType       : 4; /* 0 = UC, 6 = WriteBack */
-	    uint8_t io_str_info   : 1;
-	    uint8_t def1_maybe_0  : 1; /* 1="Any VMX ctrls that default to 1 may be cleared to 0" */
-	    uint32_t rsvd2        : 8; /* Always 0 */
+	    uint64_t smm           : 1;
+	    uint64_t memType       : 4; /* 0 = UC, 6 = WriteBack */
+	    uint64_t io_str_info   : 1;
+	    uint64_t def1_maybe_0  : 1; /* 1="Any VMX ctrls that default to 1 may be cleared to 0" */
+	    uint64_t rsvd2        : 8; /* Always 0 */
 	}  __attribute__((packed));
     }  __attribute__((packed));
 }  __attribute__((packed));
 
 
+struct vmx_misc_msr {
+    union {
+	struct {
+	    uint32_t lo;
+	    uint32_t hi;
+	} __attribute__((packed));
+
+	struct {
+	    uint64_t tsc_multiple       : 5; /* Bit position in TSC field that drives vmx timer step */
+	    uint64_t exits_store_LMA    : 1;
+	    uint64_t can_halt           : 1;
+	    uint64_t can_shtdown        : 1;
+	    uint64_t can_wait_for_sipi  : 1;
+	    uint64_t rsvd1              : 7;
+	    uint64_t num_cr3_targets    : 9;
+	    uint64_t max_msr_cache_size : 3; /* (512 * (max_msr_cache_size + 1)) == max msr load/store list size */
+	    uint64_t SMM_ctrl_avail     : 1;
+	    uint64_t rsvd2              : 3; 
+	    uint64_t MSEG_rev_id;
+	}  __attribute__((packed));
+    }  __attribute__((packed));
+} __attribute__((packed));
+
+
+struct vmx_ept_msr {
+    union {
+	struct {
+	    uint32_t lo;
+	    uint32_t hi;
+	} __attribute__((packed));
+
+	struct {
+	    uint64_t exec_only_ok             : 1;
+	    uint64_t rsvd1                    : 5;
+	    uint64_t pg_walk_len4             : 1; /* support for a page walk of length 4 */
+	    uint64_t rsvd2                    : 1;
+	    uint64_t ept_uc_ok                : 1; /* EPT page tables can be uncacheable */
+	    uint64_t rsvd3                    : 5;
+	    uint64_t ept_wb_ok                : 1; /* EPT page tables can be writeback */
+	    uint64_t rsvd4                    : 1;
+	    uint64_t ept_2MB_ok               : 1; /* 2MB EPT pages supported */
+	    uint64_t ept_1GB_ok               : 1; /* 1GB EPT pages supported */
+	    uint64_t rsvd5                    : 2;
+	    uint64_t INVEPT_avail             : 1; /* INVEPT instruction is available */
+	    uint64_t rsvd6                    : 4;
+	    uint64_t INVEPT_single_ctx_avail  : 1;
+	    uint64_t INVEPT_all_ctx_avail     : 1;
+	    uint64_t rsvd7                    : 5;
+	    uint64_t INVVPID_avail            : 1;
+	    uint64_t rsvd8                    : 7;
+	    uint64_t INVVPID_1addr_avail      : 1;
+	    uint64_t INVVPID_single_ctx_avail : 1;
+	    uint64_t INVVPID_all_ctx_avail    : 1;
+	    uint64_t INVVPID_single_ctx_w_glbls_avail : 1;
+	    uint64_t rsvd9                   : 20;
+	}  __attribute__((packed));
+    }  __attribute__((packed));
+}__attribute__((packed));
+
+
+struct vmx_ctrl_field {
+    uint32_t def_val;
+    uint32_t req_val;  /* Required values: field_val & req_mask == req_val */ 
+    uint32_t req_mask; /* If a mask bit is set it's value is restricted (i.e. the VMM cannot change it) */
+};
+
+
+struct vmx_cr_field {
+    uint64_t def_val;
+    uint64_t req_val;  /* Required values: field_val & req_mask == req_val */ 
+    uint64_t req_mask; /* If a mask bit is set it's value is restricted (i.e. the VMM cannot change it) */
+};
+
 
 
 
 struct vmx_hw_info {
     struct vmx_basic_msr basic_info;
-    
+    struct vmx_misc_msr misc_info;
+    struct vmx_ept_msr ept_info;
 
+    struct vmx_ctrl_field pin_ctrls;
+    struct vmx_ctrl_field proc_ctrls;
+    struct vmx_ctrl_field exit_ctrls;
+    struct vmx_ctrl_field entry_ctrls;
+    struct vmx_ctrl_field sec_proc_ctrls;
+
+    struct vmx_cr_field cr0;
+    struct vmx_cr_field cr4;
 
 };
 
 
-int v3_init_vmx_hw();
 
 
+int v3_init_vmx_hw(struct vmx_hw_info * hw_info);
+
+uint32_t v3_vmx_get_ctrl_features(struct vmx_ctrl_field * fields);
+
 
 
 #endif