X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Finclude%2Fextensions%2Ftrans_mem.h;h=f3c165413c4456e8d0e7e7ffc32a8266a1960fae;hb=b0056428ce1c60d7d9b6ac0a2cd11df597b58a92;hp=f8d980e368fff726fd177e497409dbff5403232d;hpb=1675f10b6a5173570788c4fc5e013925c0189fea;p=palacios.git

diff --git a/palacios/include/extensions/trans_mem.h b/palacios/include/extensions/trans_mem.h
index f8d980e..f3c1654 100644
--- a/palacios/include/extensions/trans_mem.h
+++ b/palacios/include/extensions/trans_mem.h
@@ -19,6 +19,36 @@
  * This is free software.  You are permitted to use,
  * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
  *
+ 
+RTM Implementation Wishlist (roughly in order of priority)
+Kyle Hale, Maciek Swiech 2014
+
+From Intel Architecture Instruction Set Extensions Programming Reference, Section 8.3, p.8-6
+link: http://software.intel.com/sites/default/files/m/9/2/3/41604
+
+- architectural registers need to be saved / restored 
+- abort on interrupts, asynchronous events
+- abort on CPUID, PAUSE
+- abort on non-writeback memory ops, including ifetches to uncacheable mem
+- RTM-debugger support
+- RTM nesting
+- parameterized cache model, for generating hardware configuration-based aborts
+
+- to be able to model specific implementations, add options (runtime or compiletime) to abort on:
+    * x86/mmx state changes, (also fxstor, fxsave),
+    * cli, sti, popfd, popfq, clts
+    * mov to segment regs, pop segment regs, lds, les, lfs, lgs, lss, swapgs, wrfsbase, wrgsbase, lgdt, sgdt, lidt, sidt, lldt, sldt, ltr, 
+      str, far call, far jmp, far ret, far iret, mov to DRx, mov to cr0-4, cr8 lmsw
+    * sysenter, syscall, sysexit, sysret
+    * clflush, invd, wbinvd, invlpg, invpcid
+    * memory instructions with temporal hints (e.g. movntdqa)
+    * xsave, xsaveopt, xrstor
+    * interrupts: INTn, INTO
+    * IO: in, ins, rep ins, out, outs, rep outs, and variants
+    * VMX instructions
+    * smx: getsec
+    * ud2, rsm, rdmsr, wrmsr, hlt, monitor, mwait, xsetbv, vzeroupper, maskmovq, v/maskmovdqu
+    
  *
  *
  * We claim that we can have a single, shared "cache"-like box
@@ -104,6 +134,22 @@
 #define XABORT_INSTR_LEN 0x3
 #define XTEST_INSTR_LEN  0x3
 
+/* abort status definitions (these are bit indeces) */
+#define ABORT_XABORT     0x0 // xabort instr
+#define ABORT_RETRY      0x1 // may succeed on retry (must be clear if bit 0 set)
+#define ABORT_CONFLICT   0x2 // another process accessed memory in the transaction
+#define ABORT_OFLOW      0x3 // internal buffer overflowed
+#define ABORT_BKPT       0x4 // debug breakpoint was hit
+#define ABORT_NESTED     0x5 // abort occured during nested transaction (not currently used)
+
+
+typedef enum tm_abrt_cause {
+    TM_ABORT_XABORT,
+    TM_ABORT_CONFLICT,
+    TM_ABORT_INTERNAL,
+    TM_ABORT_BKPT,
+    TM_ABORT_UNSPECIFIED,
+} tm_abrt_cause_t;
 
 struct v3_tm_access_type {
     uint8_t r : 1;
@@ -214,7 +260,9 @@ int v3_restore_dirty_instr(struct guest_info *core);
 int v3_restore_abort_instr(struct guest_info *core);
 
 // handles abort cleanup, called from INT/EXCP or XABORT
-int v3_handle_trans_abort(struct guest_info *core);
+int v3_handle_trans_abort(struct guest_info *core,
+                         tm_abrt_cause_t cause,
+                         uint8_t xabort_reason);
 
 // record a memory access in hashes
 int tm_record_access (struct v3_trans_mem * tm,