X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Finclude%2Fdevices%2Fpci.h;h=bbb61c50f022cded5653fcaaa5666f351bc04b7d;hb=60ad6a41c6d0ee08ed689e8505eb0c3df0c2a289;hp=9bf46326ce96b5a8bb23e9c7dea6a04c049c1722;hpb=8300df0450154d7a2db08a7afbd2aca32ce38f70;p=palacios.git diff --git a/palacios/include/devices/pci.h b/palacios/include/devices/pci.h index 9bf4632..bbb61c5 100644 --- a/palacios/include/devices/pci.h +++ b/palacios/include/devices/pci.h @@ -27,13 +27,22 @@ #include #include +#include #include - struct vm_device; +typedef enum { PCI_CMD_DMA_DISABLE = 1, + PCI_CMD_DMA_ENABLE = 2, + PCI_CMD_INTX_DISABLE = 3, + PCI_CMD_INTX_ENABLE = 4, + PCI_CMD_MSI_DISABLE = 5, + PCI_CMD_MSI_ENABLE = 6, + PCI_CMD_MSIX_DISABLE = 7, + PCI_CMD_MSIX_ENABLE = 8 } pci_cmd_t; + typedef enum { PCI_BAR_IO, PCI_BAR_MEM24, PCI_BAR_MEM32, @@ -83,7 +92,7 @@ struct v3_pci_bar { // Internal PCI data uint32_t val; - int updated; + uint8_t updated; uint32_t mask; }; @@ -104,6 +113,13 @@ struct v3_pci_bar { #define PCI_MEM64_BASE_LO(bar_val) (bar_val & PCI_MEM64_MASK_LO) #define PCI_EXP_ROM_BASE(rom_val) (rom_val & PCI_EXP_ROM_MASK) +#define PCI_IO_BAR_VAL(addr) ((addr & PCI_IO_MASK) | 0x1) +#define PCI_MEM24_BAR_VAL(addr, prefetch) (((addr & PCI_MEM24_MASK) | 0x2) | ((prefetch) != 0) << 3) +#define PCI_MEM32_BAR_VAL(addr, prefetch) (((addr & PCI_MEM_MASK) | ((prefetch) != 0) << 3)) +#define PCI_MEM64_HI_BAR_VAL(addr, prefetch) (addr & PCI_MEM64_MASK_HI) +#define PCI_MEM64_LO_BAR_VAL(addr, prefetch) ((((addr) & PCI_MEM64_MASK_LO) | 0x4) | ((prefetch) != 0) << 3) +#define PCI_EXP_ROM_VAL(addr, enable) (((addr) & PCI_EXP_ROM_MASK) | ((enable) != 0)) + struct pci_device { @@ -134,30 +150,45 @@ struct pci_device { char name[64]; - int (*config_update)(uint_t reg_num, void * src, uint_t length, void * priv_data); - - int (*cmd_update)(struct pci_device * pci_dev, uchar_t io_enabled, uchar_t mem_enabled); + int (*config_write)(struct pci_device * pci_dev, uint32_t reg_num, void * src, + uint_t length, void * priv_data); + int (*config_read)(struct pci_device * pci_dev, uint32_t reg_num, void * dst, + uint_t length, void * priv_data); + int (*cmd_update)(struct pci_device * pci_dev, pci_cmd_t cmd, uint64_t arg, void * priv_data); int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * private_data); - int (*config_write)(uint_t reg_num, void * src, uint_t length, void * private_data); - int (*config_read)(uint_t reg_num, void * dst, uint_t length, void * private_data); + struct v3_vm_info * vm; + struct list_head cfg_hooks; + struct list_head capabilities; - int exp_rom_update_flag; - int bar_update_flag; + struct msi_msg_ctrl * msi_cap; + struct msix_cap * msix_cap; + struct vm_device * apic_dev; + + enum {IRQ_NONE, IRQ_INTX, IRQ_MSI, IRQ_MSIX} irq_type; void * priv_data; }; int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num, - int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev), - int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev), - struct vm_device * bridge_dev); + int (*raise_pci_irq)(struct pci_device * pci_dev, void * dev_data, struct v3_irq * vec), + int (*lower_pci_irq)(struct pci_device * pci_dev, void * dev_data, struct v3_irq * vec), + void * dev_data); + + +/* Raising a PCI IRQ requires the specification of a vector index. + * If you are not sure, set vec_index to 0. + * For IntX IRQs, the index is the interrupt line the device is using (INTA=0, INTB=1, ...) - only used in multi-function devices + * For MSI and MSIX, the index is the vector index if multi-vectors are enabled + */ +int v3_pci_raise_irq(struct vm_device * pci_bus, struct pci_device * dev, uint32_t vec_index); +int v3_pci_lower_irq(struct vm_device * pci_bus, struct pci_device * dev, uint32_t vec_index); -int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev); -int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev); +int v3_pci_raise_acked_irq(struct vm_device * pci_bus, struct pci_device * dev, struct v3_irq vec); +int v3_pci_lower_acked_irq(struct vm_device * pci_bus, struct pci_device * dev, struct v3_irq vec); struct pci_device * v3_pci_register_device(struct vm_device * pci, @@ -167,21 +198,34 @@ v3_pci_register_device(struct vm_device * pci, int fn_num, const char * name, struct v3_pci_bar * bars, - int (*config_update)(uint_t reg_num, void * src, uint_t length, void * private_data), - int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled), + int (*config_write)(struct pci_device * pci_dev, uint32_t reg_num, void * src, + uint_t length, void * private_data), + int (*config_read)(struct pci_device * pci_dev, uint32_t reg_num, void * dst, + uint_t length, void * private_data), + int (*cmd_update)(struct pci_device *pci_dev, pci_cmd_t cmd, uint64_t arg, void * priv_data), int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * private_data), void * priv_data); -struct pci_device * -v3_pci_register_passthrough_device(struct vm_device * pci, - int bus_num, - int dev_num, - int fn_num, - const char * name, - int (*config_write)(uint_t reg_num, void * src, uint_t length, void * private_data), - int (*config_read)(uint_t reg_num, void * dst, uint_t length, void * private_data), - void * private_data); + +int v3_pci_hook_config_range(struct pci_device * pci, + uint32_t start, uint32_t length, + int (*write)(struct pci_device * pci_dev, uint32_t offset, + void * src, uint_t length, void * private_data), + int (*read)(struct pci_device * pci_dev, uint32_t offset, + void * src, uint_t length, void * private_data), + void * private_data); + + + + +typedef enum { PCI_CAP_INVALID = 0, + PCI_CAP_PM = 0x1, + PCI_CAP_MSI = 0x5, + PCI_CAP_MSIX = 0x11, + PCI_CAP_PCIE = 0x10 } pci_cap_type_t; + +int v3_pci_enable_capability(struct pci_device * pci, pci_cap_type_t cap_type); #endif