X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Finclude%2Fdevices%2Fpci.h;h=68ac2dcafb9dd69ad165a7f7304ffa315e293e97;hb=8a441df14ef65bb559ce090249343ec1dac1a7fc;hp=66841a808f9fac89e3bd4f2efde68d948b4c8ebb;hpb=a0e1d8274aef54adcf50dce0b3843489f2a3cd21;p=palacios.git

diff --git a/palacios/include/devices/pci.h b/palacios/include/devices/pci.h
index 66841a8..68ac2dc 100644
--- a/palacios/include/devices/pci.h
+++ b/palacios/include/devices/pci.h
@@ -24,17 +24,29 @@
 
 #ifdef __V3VEE__
 
-#include <palacios/vm_dev.h>
+
 #include <palacios/vmm_types.h>
 #include <palacios/vmm_rbtree.h>
 
 #include <devices/pci_types.h>
 
 
-typedef enum {PCI_BAR_IO, PCI_BAR_MEM16, PCI_BAR_MEM32, PCI_BAR_MEM64_LOW, PCI_BAR_MEM64_HIGH, PCI_BAR_NONE} pci_bar_type_t;
+typedef enum { PCI_BAR_IO, 
+	       PCI_BAR_MEM16, 
+	       PCI_BAR_MEM32, 
+	       PCI_BAR_MEM64_LOW, 
+	       PCI_BAR_MEM64_HIGH, 
+	       PCI_BAR_NONE } pci_bar_type_t;
 
 typedef enum {PCI_STD_DEVICE, PCI_TO_PCI_BRIDGE, PCI_CARDBUS, PCI_MULTIFUNCTION} pci_device_type_t;
 
+
+
+// For the rest of the subclass codes see:
+// http://www.acm.uiuc.edu/sigops/roll_your_own/7.c.1.html
+
+#define PCI_AUTO_DEV_NUM (-1)
+
 struct pci_device;
 
 struct v3_pci_bar {
@@ -51,10 +63,12 @@ struct v3_pci_bar {
 	struct {
 	    int num_ports;
 	    uint16_t default_base_port;
-	    int (*io_read)(ushort_t port, void * dst, uint_t length, struct vm_device * dev);
-	    int (*io_write)(ushort_t port, void * src, uint_t length, struct vm_device * dev);
+	    int (*io_read)(ushort_t port, void * dst, uint_t length, void * private_data);
+	    int (*io_write)(ushort_t port, void * src, uint_t length, void * private_data);
 	};
     };
+    
+    void * private_data;
 
     // Internal PCI data
     uint32_t val;
@@ -63,8 +77,11 @@ struct v3_pci_bar {
 };
 
 
-#define PCI_IO_BASE(bar_val) (bar_val & 0xfffffffc)
-#define PCI_MEM32_BASE(bar_val) (bar_val & 0xfffffff0)
+#define PCI_IO_MASK 0xfffffffc
+#define PCI_MEM32_MASK 0xfffffff0
+
+#define PCI_IO_BASE(bar_val) (bar_val & PCI_IO_MASK)
+#define PCI_MEM32_BASE(bar_val) (bar_val & PCI_MEM32_MASK)
 
 struct pci_device {
 
@@ -107,8 +124,14 @@ struct pci_device {
 };
 
 
+int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
+			  int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev), 
+			  int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev), 
+			  struct vm_device * bridge_dev);
+
 
-struct vm_device * v3_create_pci();
+int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev);
+int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev);
 
 struct pci_device * 
 v3_pci_register_device(struct vm_device * pci,