X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Finclude%2Fdevices%2Fpci.h;h=68ac2dcafb9dd69ad165a7f7304ffa315e293e97;hb=8a441df14ef65bb559ce090249343ec1dac1a7fc;hp=62060c577d72aa8d2c158c3d4bf9d74baf258ec5;hpb=57164c930523141c4ef53782de214d2a9f468269;p=palacios.git

diff --git a/palacios/include/devices/pci.h b/palacios/include/devices/pci.h
index 62060c5..68ac2dc 100644
--- a/palacios/include/devices/pci.h
+++ b/palacios/include/devices/pci.h
@@ -63,10 +63,12 @@ struct v3_pci_bar {
 	struct {
 	    int num_ports;
 	    uint16_t default_base_port;
-	    int (*io_read)(ushort_t port, void * dst, uint_t length, struct vm_device * dev);
-	    int (*io_write)(ushort_t port, void * src, uint_t length, struct vm_device * dev);
+	    int (*io_read)(ushort_t port, void * dst, uint_t length, void * private_data);
+	    int (*io_write)(ushort_t port, void * src, uint_t length, void * private_data);
 	};
     };
+    
+    void * private_data;
 
     // Internal PCI data
     uint32_t val;
@@ -75,8 +77,11 @@ struct v3_pci_bar {
 };
 
 
-#define PCI_IO_BASE(bar_val) (bar_val & 0xfffffffc)
-#define PCI_MEM32_BASE(bar_val) (bar_val & 0xfffffff0)
+#define PCI_IO_MASK 0xfffffffc
+#define PCI_MEM32_MASK 0xfffffff0
+
+#define PCI_IO_BASE(bar_val) (bar_val & PCI_IO_MASK)
+#define PCI_MEM32_BASE(bar_val) (bar_val & PCI_MEM32_MASK)
 
 struct pci_device {
 
@@ -120,11 +125,13 @@ struct pci_device {
 
 
 int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
-			  int (*raise_pci_irq)(struct vm_device * dev, uint_t intr_line), 
+			  int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev), 
+			  int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev), 
 			  struct vm_device * bridge_dev);
 
 
 int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev);
+int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev);
 
 struct pci_device * 
 v3_pci_register_device(struct vm_device * pci,