X-Git-Url: http://v3vee.org/palacios/gitweb/gitweb.cgi?a=blobdiff_plain;f=palacios%2Finclude%2Fdevices%2Flnx_virtio_pci.h;fp=palacios%2Finclude%2Fdevices%2Flnx_virtio_pci.h;h=d60f05d8878bad8e63d0ed711813fc6f74709c90;hb=ec75f3ad6503e3c7996e7a445404b8813740804d;hp=0000000000000000000000000000000000000000;hpb=33717ee76445b728dfa74df98863f14118c8d41d;p=palacios.git

diff --git a/palacios/include/devices/lnx_virtio_pci.h b/palacios/include/devices/lnx_virtio_pci.h
new file mode 100644
index 0000000..d60f05d
--- /dev/null
+++ b/palacios/include/devices/lnx_virtio_pci.h
@@ -0,0 +1,104 @@
+/* 
+ * This file is part of the Palacios Virtual Machine Monitor developed
+ * by the V3VEE Project with funding from the United States National 
+ * Science Foundation and the Department of Energy.  
+ *
+ * The V3VEE Project is a joint project between Northwestern University
+ * and the University of New Mexico.  You can find out more at 
+ * http://www.v3vee.org
+ *
+ * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
+ * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org> 
+ * All rights reserved.
+ *
+ * Author: Jack Lange <jarusl@cs.northwestern.edu>
+ *
+ * This is free software.  You are permitted to use,
+ * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
+ */
+
+
+#ifndef __DEVICES_LNX_VIRTIO_PCI_H__
+#define __DEVICES_LNX_VIRTIO_PCI_H__
+
+#ifdef __V3VEE__
+
+
+/* PCI Vendor IDs (from Qemu) */
+#define VIRTIO_VENDOR_ID    0x1af4 // Redhat/Qumranet
+#define VIRTIO_SUBVENDOR_ID 0x1af4 // Redhat/Qumranet
+#define VIRTIO_SUBDEVICE_ID 0x1100 // Qemu
+
+// PCI Device IDs
+#define VIRTIO_NET_DEV_ID         0x1000
+#define VIRTIO_BLOCK_DEV_ID       0x1001
+#define VIRTIO_BALLOON_DEV_ID     0x1002
+#define VIRTIO_CONSOLE_DEV_ID     0x1003
+
+#define VIRTIO_BLOCK_SUBDEVICE_ID 2
+
+
+
+#define HOST_FEATURES_PORT 0
+#define GUEST_FEATURES_PORT 4
+#define VRING_PG_NUM_PORT 8
+#define VRING_SIZE_PORT 12
+#define VRING_Q_SEL_PORT 14
+#define VRING_Q_NOTIFY_PORT 16
+#define VIRTIO_STATUS_PORT 18
+#define VIRTIO_ISR_PORT 19
+
+
+
+/* The virtio configuration space is a hybrid io/memory mapped model 
+ * All IO is done via IO port accesses
+ * The IO ports access fields in a virtio data structure, and the base io port 
+ *    coincides with the base address of the in memory structure
+ * There is a standard virtio structure of 20 bytes, followed by a 
+ *    device specific structure of n bytes.
+ * 
+ */
+struct virtio_config {
+    uint32_t host_features;
+    uint32_t guest_features;
+    uint32_t vring_page_num;
+    uint16_t vring_ring_size;
+    uint16_t vring_queue_selector;
+    uint16_t vring_queue_notifier;
+    uint8_t status;
+    uint8_t pci_isr;
+} __attribute__((packed));
+
+
+struct vring_desc {
+    uint64_t addr_gpa;
+    uint32_t length;
+    uint16_t flags;
+    uint16_t next;
+} __attribute__((packed));
+
+struct vring_avail {
+    uint16_t flags;
+    uint16_t index;
+    uint16_t ring[0];
+} __attribute__((packed));
+
+
+struct vring_used_elem {
+    uint32_t id;
+    uint32_t length;
+} __attribute__((packed));
+
+struct vring_used {
+    uint16_t flags;
+    uint16_t index;
+    struct vring_used_elem ring[0];
+} __attribute__((packed));
+
+
+
+
+
+#endif
+
+#endif