// Intel VMX Feature MSRs
+uint32_t v3_vmx_get_ctrl_features(struct vmx_ctrl_field * fields) {
+ // features are available if they are hardwired to 1, or the mask is 0 (they can be changed)
+ uint32_t features = 0;
+
+ features = fields->req_val;
+ features |= ~(fields->req_mask);
+
+ return features;
+}
+
static int get_ex_ctrl_caps(struct vmx_hw_info * hw_info, struct vmx_ctrl_field * field,
- uint32_t old_msr, uint32_t true_msr) {
+ uint32_t old_msr, uint32_t true_msr) {
uint32_t old_0; /* Bit is 1 => MB1 */
uint32_t old_1; /* Bit is 0 => MBZ */
uint32_t true_0; /* Bit is 1 => MB1 */
v3_get_msr(VMX_BASIC_MSR, &(hw_info->basic_info.hi), &(hw_info->basic_info.lo));
v3_get_msr(VMX_MISC_MSR, &(hw_info->misc_info.hi), &(hw_info->misc_info.lo));
- v3_get_msr(VMX_EPT_VPID_CAP_MSR, &(hw_info->ept_info.hi), &(hw_info->ept_info.lo));
+
PrintError("BASIC_MSR: Lo: %x, Hi: %x\n", hw_info->basic_info.lo, hw_info->basic_info.hi);
get_ex_ctrl_caps(hw_info, &(hw_info->exit_ctrls), VMX_EXIT_CTLS_MSR, VMX_TRUE_EXIT_CTLS_MSR);
get_ex_ctrl_caps(hw_info, &(hw_info->entry_ctrls), VMX_ENTRY_CTLS_MSR, VMX_TRUE_ENTRY_CTLS_MSR);
+
/* Get secondary PROCBASED controls if secondary controls are available (optional or required) */
/* Intel Manual 3B. Sect. G.3.3 */
if ( ((hw_info->proc_ctrls.req_mask & 0x80000000) == 0) ||
((hw_info->proc_ctrls.req_val & 0x80000000) == 1) ) {
+
get_ctrl_caps(&(hw_info->sec_proc_ctrls), VMX_PROCBASED_CTLS2_MSR);
+
+ /* Get EPT data only if available - Intel 3B, G.10 */
+ /* EPT is available if processor has secondary controls (already tested) */
+ /* and if procbased_ctls2[33]==1 or procbased_ctrls2[37]==1 */
+
+ struct v3_msr proc2;
+
+ v3_get_msr(VMX_PROCBASED_CTLS2_MSR,&(proc2.hi),&(proc2.lo));
+
+ if ( (proc2.hi & 0x2) || (proc2.hi & 0x20) ) {
+ v3_get_msr(VMX_EPT_VPID_CAP_MSR, &(hw_info->ept_info.hi), &(hw_info->ept_info.lo));
+ }
}
-
+
get_cr_fields(&(hw_info->cr0), VMX_CR0_FIXED1_MSR, VMX_CR0_FIXED0_MSR);
get_cr_fields(&(hw_info->cr4), VMX_CR4_FIXED1_MSR, VMX_CR4_FIXED0_MSR);