instr->instr_length += length;
#ifdef V3_CONFIG_DEBUG_DECODER
+ V3_Print("Decoding Instr at %p\n", (void *)core->rip);
v3_print_instr(instr);
+ V3_Print("CS DB FLag=%x\n", core->segments.cs.db);
#endif
return 0;
case AND_IMM2:
case OR_IMM2:
case SUB_IMM2:
- case XOR_IMM2:
- case MOV_IMM2:{
+ case XOR_IMM2:
+ case MOV_IMM2: {
uint8_t reg_code = 0;
ret = decode_rm_operand(core, instr_ptr, form, instr, &(instr->dst_operand), ®_code);
instr->src_operand.operand = *(uint16_t *)instr_ptr;
} else if (operand_width == 4) {
instr->src_operand.operand = *(uint32_t *)instr_ptr;
+ } else if (operand_width == 8) {
+ instr->src_operand.operand = *(sint32_t *)instr_ptr; // This is a special case for sign extended 64bit ops
} else {
PrintError("Illegal operand width (%d)\n", operand_width);
return -1;
instr->is_str_op = 1;
if (instr->prefixes.rep == 1) {
- instr->str_op_length = MASK(core->vm_regs.rcx, operand_width);
+ instr->str_op_length = MASK(core->vm_regs.rcx, addr_width);
} else {
instr->str_op_length = 1;
}
instr->is_str_op = 1;
if (instr->prefixes.rep == 1) {
- instr->str_op_length = MASK(core->vm_regs.rcx, operand_width);
+ instr->str_op_length = MASK(core->vm_regs.rcx, addr_width);
} else {
instr->str_op_length = 1;
}
break;
}
+ case INT: {
+ instr->dst_operand.type = IMM_OPERAND;
+ instr->dst_operand.size = operand_width;
+ instr->dst_operand.operand = *(uint8_t *)instr_ptr;
+ instr_ptr += operand_width;
+ instr->num_operands = 1;
+
+ break;
+ }
case INVLPG: {
uint8_t reg_code = 0;
case INVLPG:
return V3_OP_INVLPG;
+ case INT:
+ return V3_OP_INT;
+
case MOV_CR2:
return V3_OP_MOVCR2;
case MOV_2CR:
return V3_OP_MOV2CR;
-
case MOV_MEM2_8:
case MOV_MEM2:
case MOV_2MEM_8: