#include <palacios/vm_guest_mem.h>
#include <palacios/vm_guest.h>
+// Reference: AMD Software Developer Manual Vol.2 Ch.5 "Page Translation and Protection"
+static int get_page_size() {
-static inline int handle_passthrough_pagefault_64(struct guest_info * info,
- addr_t fault_addr,
- pf_error_t error_code) {
- pml4e64_t * pml = NULL;
- pdpe64_t * pdpe = NULL;
- pde64_t * pde = NULL;
- pte64_t * pte = NULL;
- addr_t host_addr = 0;
+ // Need to fix this....
+ return PAGE_SIZE_4KB;
+}
+
+
+static inline int handle_passthrough_pagefault_64(struct guest_info * core, addr_t fault_addr, pf_error_t error_code) {
+ pml4e64_t * pml = NULL;
+ pdpe64_t * pdpe = NULL;
+ pde64_t * pde = NULL;
+ pde64_2MB_t * pde2mb = NULL;
+ pte64_t * pte = NULL;
+ addr_t host_addr = 0;
- int pml_index = PML4E64_INDEX(fault_addr);
+ int pml_index = PML4E64_INDEX(fault_addr);
int pdpe_index = PDPE64_INDEX(fault_addr);
- int pde_index = PDE64_INDEX(fault_addr);
- int pte_index = PTE64_INDEX(fault_addr);
+ int pde_index = PDE64_INDEX(fault_addr);
+ int pte_index = PTE64_INDEX(fault_addr);
+ struct v3_mem_region * region = v3_get_mem_region(core->vm_info, core->cpu_id, fault_addr);
+ int page_size = PAGE_SIZE_4KB;
-
- struct v3_mem_region * region = v3_get_mem_region(info->vm_info, info->cpu_id, fault_addr);
-
- if (region == NULL) {
- PrintError("Invalid region in passthrough page fault 64, addr=%p\n",
- (void *)fault_addr);
- return -1;
+ /* Check if:
+ * 1. the guest is configured to use large pages and
+ * 2. the memory regions can be referenced by a large page
+ */
+ if ((core->use_large_pages == 1) ) {
+ page_size = get_page_size();
}
- host_addr = v3_get_shadow_addr(region, info->cpu_id, fault_addr);
- //
-
+
// Lookup the correct PML address based on the PAGING MODE
- if (info->shdw_pg_mode == SHADOW_PAGING) {
- pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
+ if (core->shdw_pg_mode == SHADOW_PAGING) {
+ pml = CR3_TO_PML4E64_VA(core->ctrl_regs.cr3);
} else {
- pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
+ pml = CR3_TO_PML4E64_VA(core->direct_map_pt);
}
//Fix up the PML entry
pml[pml_index].writable = 1;
pml[pml_index].user_page = 1;
- pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));
+ pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR_4KB((addr_t)V3_PAddr(pdpe));
} else {
- pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
+ pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR_4KB(pml[pml_index].pdp_base_addr));
}
// Fix up the PDPE entry
pdpe[pdpe_index].writable = 1;
pdpe[pdpe_index].user_page = 1;
- pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));
+ pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR_4KB((addr_t)V3_PAddr(pde));
} else {
- pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
+ pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR_4KB(pdpe[pdpe_index].pd_base_addr));
}
+
+ // Continue with the 4KiB page heirarchy
+
// Fix up the PDE entry
if (pde[pde_index].present == 0) {
pte = (pte64_t *)create_generic_pt_page();
pde[pde_index].writable = 1;
pde[pde_index].user_page = 1;
- pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
+ pde[pde_index].pt_base_addr = PAGE_BASE_ADDR_4KB((addr_t)V3_PAddr(pte));
} else {
- pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
+ pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR_4KB(pde[pde_index].pt_base_addr));
}
-
// Fix up the PTE entry
if (pte[pte_index].present == 0) {
pte[pte_index].user_page = 1;
pte[pte_index].writable = 0;
}
- pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
+ if (v3_gpa_to_hpa(core, fault_addr, &host_addr) == -1) {
+ PrintError("Error Could not translate fault addr (%p)\n", (void *)fault_addr);
+ return -1;
+ }
+
+ pte[pte_index].page_base_addr = PAGE_BASE_ADDR_4KB(host_addr);
} else {
- return region->unhandled(info, fault_addr, fault_addr, region, error_code);
+ return region->unhandled(core, fault_addr, fault_addr, region, error_code);
}
} else {
// We fix all permissions on the first pass,
// so we only get here if its an unhandled exception
- return region->unhandled(info, fault_addr, fault_addr, region, error_code);
+ return region->unhandled(core, fault_addr, fault_addr, region, error_code);
}
return 0;
}
-static inline int invalidate_addr_64(struct guest_info * info, addr_t inv_addr) {
+static inline int invalidate_addr_64(struct guest_info * core, addr_t inv_addr) {
pml4e64_t * pml = NULL;
pdpe64_t * pdpe = NULL;
pde64_t * pde = NULL;
// Lookup the correct PDE address based on the PAGING MODE
- if (info->shdw_pg_mode == SHADOW_PAGING) {
- pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
+ if (core->shdw_pg_mode == SHADOW_PAGING) {
+ pml = CR3_TO_PML4E64_VA(core->ctrl_regs.cr3);
} else {
- pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
+ pml = CR3_TO_PML4E64_VA(core->direct_map_pt);
}
if (pml[pml_index].present == 0) {
if (pdpe[pdpe_index].present == 0) {
return 0;
- } else if (pdpe[pdpe_index].large_page == 1) {
+ } else if (pdpe[pdpe_index].large_page == 1) { // 1GiB
pdpe[pdpe_index].present = 0;
return 0;
}
if (pde[pde_index].present == 0) {
return 0;
- } else if (pde[pde_index].large_page == 1) {
+ } else if (pde[pde_index].large_page == 1) { // 2MiB
pde[pde_index].present = 0;
return 0;
}
pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
- pte[pte_index].present = 0;
+ pte[pte_index].present = 0; // 4KiB
return 0;
}
