// availability
for (j = 0; j < 8; j++) {
if (!(bus->dev_map[i] & (0x1 << j))) {
- return i * 8 + j;
+ return ((i * 8) + j);
}
}
}
}
static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
- int major = dev_num / 8;
+ int major = (dev_num / 8);
int minor = dev_num % 8;
bus->dev_map[major] |= (0x1 << minor);
pci_dev->config_header.revision = 0x0002;
pci_dev->config_header.subclass = 0x00; // SubClass: host2pci
pci_dev->config_header.class = 0x06; // Class: PCI bridge
- pci_dev->config_header.header_type = 0x00;
pci_dev->bus_num = 0;
return 0;
}
+/*
+static void test_devices(struct vm_device * dev) {
+ struct pci_device * pci_dev = NULL;
+ struct v3_pci_bar bars[6];
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ bars[i].type = PCI_BAR_NONE;
+ bars[i].mem_hook = 0;
+ bars[i].num_pages = 0;
+ bars[i].bar_update = NULL;
+ }
+
+
+ pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "", 0, bars,
+ NULL, NULL, NULL, NULL);
+
+ pci_dev->config_header.vendor_id = 0x8086;
+ pci_dev->config_header.device_id = 0x0101;
+ pci_dev->config_header.revision = 0x0002;
+ pci_dev->config_header.subclass = 0x01; // SubClass: host2pci
+ pci_dev->config_header.class = 0x01; // Class: PCI bridge
+
+ pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "", 0, bars,
+ NULL, NULL, NULL, NULL);
+
+ pci_dev->config_header.vendor_id = 0x8086;
+ pci_dev->config_header.device_id = 0x0101;
+ pci_dev->config_header.revision = 0x0002;
+ pci_dev->config_header.subclass = 0x00; // SubClass: host2pci
+ pci_dev->config_header.class = 0x02; // Class: PCI bridge
+
+
+
+
+}
+
+*/
static void init_pci_busses(struct pci_internal * pci_state) {
int i;
return -1;
}
+ //test_devices(dev);
+
PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
for (i = 0; i < 4; i++) {
int bar_offset = 0x10 + 4 * i;
if (pci_dev->bar[i].type == PCI_BAR_IO) {
+ //pci_dev->bar[i].mask = 0x0000fffd;
+ pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_io_ports) - 1)) | 0x01;
+
*(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000001;
} else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
- pci_dev->bar[i].mask = (pci_dev->bar[i].num_pages << 12) - 1;
+ pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
*(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000008;
PrintError("Invalid BAR type for bar #%d\n", i);
return -1;
}
-
-
}
return 0;
}
-
// if dev_num == -1, auto assign
struct pci_device * v3_pci_register_device(struct vm_device * pci,
pci_device_type_t dev_type,
pci_dev->priv_data = private_data;
-
+
//copy bars
for (i = 0; i < 6; i ++){
- pci_dev->bar[i].type = bars[i].type;
- pci_dev->bar[i].num_pages = bars[i].num_pages;
- pci_dev->bar[i].mem_hook = bars[i].mem_hook;
- pci_dev->bar[i].bar_update = bars[i].bar_update;
+ pci_dev->bar[i].type = bars[i].type;
+
+ if (pci_dev->bar[i].type == PCI_BAR_IO) {
+ pci_dev->bar[i].num_io_ports = bars[i].num_io_ports;
+ } else {
+ pci_dev->bar[i].num_pages = bars[i].num_pages;
+ }
+
+ pci_dev->bar[i].mem_hook = bars[i].mem_hook;
+ pci_dev->bar[i].bar_update = bars[i].bar_update;
}
if (init_bars(pci_dev) == -1) {
return NULL;
}
- pci_dev->cmd_update = cmd_update;
- pci_dev->ext_rom_update = ext_rom_update;
-
// add the device
add_device_to_bus(bus, pci_dev);
-
#ifdef DEBUG_PCI
pci_dump_state(pci_state);
#endif